Course Handout VLSI Design

SRINIVASAN ENGINEERING COLLEGE - Perambalur-621212

Department of Electronics and Communication EngineeringEven Semester 2013 – 2014

DATE: 10.12.2013

Course Handout L T P C 3 0 0 3

Course No : EC 2354 Course Title : VLSI designCourse Instructor : P. Selvakumar, Instructor incharge : A. Balasubramaniyan.

COURSE OBJECTIVES:

To learn the basic CMOS circuits. To learn the CMOS process technology. To learn the techniques of chip design using programmable devices. To learn the concepts of designing VLSI subsystems. To learn the concepts of modeling a digital system using Hardware Description Language.

COURSE OUTCOME:

Upon successful completion of this course, a student will be able to

To synthesize static and dynamic logic cells based on knowledge of MOS device physics, modeling and circuit topologies.

Designing and implementing combinational and sequential CMOS digital circuits and optimize them with respect to different constraints, such as area, delay, power, or reliability.

To insert elementary testing hardware into the VLSI chip. Be capable of implementing a complete design verification process using computer-automated

tools for layout, extraction, simulation, and timing analysis. Design a hardware circuit in terms of HDL.

TEXT BOOK(S) [TB]:

1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 20052. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002.

REFERENCE BOOK(S) [RB]:

1. D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 20032. Wayne Wolf, Modern VLSI design, Pearson Education, 20033. M.J.S.Smith: Application specific integrated circuits, Pearson Education, 19974. J.Bhasker: Verilog HDL primer, BS publication, 20015. Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003

COURSE PLAN / SCHEDULE:

S.No Topics to be covered Learning objectives Ref. to Text Book

No. of lectures

UNIT-I CMOS TECHNOLOGY1 A brief History-MOS To study the basic operation of T1-5 1

Format No.: FM2/ Issue: 01/Revision: 00

transistor NMOS & PMOS transistors

2 CMOS logic To study about the basic concepts of CMOS T1-7 1

3 Ideal I-V characteristics To study the various regions of operation of an transistor T1-42 1

4 C-V characteristics To study about the various capacitance models T1-45 1

5 Non ideal IV effects To study about various effects of MOS transistor T1-51 1

6 DC transfer characteristics To study the transfer characteristics of a transistor T1-60 1

7 Pass transistor To study about their DC characteristics T1-66 1

8 CMOS technologies To study about p-well and n-well process T1-73 1

9 Layout design Rules To study the rules of layout design T1-83 1

10 CMOS process enhancements

To study about interconnect and circuit elements T1-91 1

11 Technology related CAD issues

To study about DRC and circuit extraction T1-105 1

12 Manufacturing issues To study the antenna and layer density rules T1-107 1

UNIT-II CIRCUIT CHARACTERIZATION AND SIMULATION13 Delay estimation To study about RC models T1-111 114 Logical effort To study the delay in logic gate T1-120 1

15 Transistor sizing To study multistage logic networks T1-123 1

16 Power dissipation To study about static and dynamic dissipation T1-129 1

17 Interconnect To study about resistance, capacitance, delay and crosstalk T1-135 1

18 Design margin To study about the supply voltage and temperature T1-145 1

19 Reliability, Scaling To understand the reliability terminologies and scaling types T1-148 1

20 SPICE tutorial To know about transistor analysis & HSPICE commands T1-179 1

21 Device models To describe the level 1,2,3 models T1-190 1

22 Device characterization To describe the I - V characteristics T1-193 1

23 Circuit characterization To study the DC transfer characteristics T1-205 1

24 Interconnect simulation To study about the interconnect parasitics T1-210 1

UNIT-III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN25 Circuit families To know about static CMOS T1-216 1

of 5Format No: FM2 / Issue: 01 / Revision: 00

26 Dynamic Circuits To study about pre-charge and evaluation of dynamic circuits T1-226 1

27 Low power logic design To deal with level conversion circuits T1-242 1

28 Comparison of circuit families

To summarize the characteristics of circuit families T1-243 1

29 Sequencing static circuits To study about the sequencing methods and delay constraints T1-251 1

30 Circuit design of latches To deal about conventional CMOS latches T1-265 1

31 Circuit design of flip flops To deal about conventional CMOS FF and differential FF T1-268 1

32 Static sequencing element methodology

To study about low power sequential design T1-275 1

33 Two phase timing types To describe about various timing clocks T1-278 1

34 Sequencing dynamic circuits

To study about the domino circuits T1-284 1

35 Synchronizers To deal about simple synchronizer and metastability T1-289 1

36Communicating between asynchronous clock domains

To study the two phase and four phase handshake signals T1-294 1

UNIT-IV CMOS TESTING

37 Need for testing To know about the various needs of testing T1-531 1

38 Basic digital debugging hints

To know about typical debugging hints T1-534 1

39 Testers, Text fixtures To study about testing a chip after fabrication T1-537 1

40 Test programs To know about how to test a chip using programs T1-539 1

41 Logic verification To know the usage of test benches T1-541 1

42 Version control, Bug tracking

To deal about tools used for testing T1-542 1

43 Silicon debug principles To study the various debugging principles T1-542 1

44 Manufacturing test To study about the faults T1-544 1

45 ATPG, DFT To describe inbuilt testing of a chip T1-548 1

46 Design for testability To study about the Adhoc testing T1-548 1

47 BIST To know about various testing procedures T1-555 1

48 Boundary scan To study the boundary scan architecture T1-559 1


UNIT-V SPECIFICATION USING VERILOG HDL

49 Basic concepts, identifiers To explain various basic concepts in verilog R4-69 1

50 Gate primitives, gate delays To explain different gate delays R4-105,121 1

51 Operators, timing controls To study about various operator R4-137,171 1

52 Procedural assignments, conditional statements

To study about different types of assignments R4-166,179 1

53 Data flow and RTL To explain about various types of modeling R4-131 1

54 Structural gate level switch level modeling

To design the circuit using structural modeling R4-277 1

55 Design hierarchies To explain the top down and bottom up methodology R4-53 1

56 Behavioral and RTL modelling, Test benches

To study about sequential designing R4-161 1

57 Structural gate level description of decoder

To design decoder using structural type R4-284 1

58 Equality detector, comparator

To design comparator using verilog R4-201 1

59 Priority encoder, half & full adder, Ripple carry adder

To design this circuits using verilog

R4-150 1

60 D latch and D flip flop R4-152 1Total number of classes planned: 60

EVALUATION SCHEME – INTERNAL ASSESSMENT


EC No.

Evaluation Components

Duration Weightage Date & Time Venue

1 Slip Tests 40 min 20% Monday-Friday &8.30am to 9.15am

To

bean

noun

ced

late

r

2 Cycle Test 1 1.30hr

30%

27-01-2014 To 01-02-2014 &8.30am to 10.00am

3 Cycle Test 2 1.30hr 17-02-2014 To 24-02-2014 &8.30am to 10.00am

4 Cycle Test 3 1.30hr 10-03-2014 To 15-03-2014 &8.30am to 10.00am

5 Model Exam 3hr 30% 05-04-2014 To 11-04-2014 &1.00pm to 4.00pm

6 Attendance Percentage

Continuous 20%

LINKS: Question Bank : www.sriengg.comUniversity Question Paper: www.sriengg.com

HOD INSTRUCTOR INCHRGE COURSE INSTRUCTOR B.Karthiga A. Balasubramaniyan. P. Selvakumar,


Course Handout VLSI Design

Documents

Transcript of Course Handout VLSI Design