Course Code: Cap211 Course Name: Computer Organization

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Course Code: CAP211 Course Name: COMPUTER ORGANIZATION AND ARCHITECTURE HOME WORK -2 HOME WORK -2 COURSE CODE- COURSE CODE- CAP211 CAP211 COURSE INSTRUCTOR – Miss Kuljeet COURSE TUTOR – Miss Kuljeet DATE OF ALLOTMENT – DATE OF ALLOTMENT – 25-09-09 DOS: DOS: 13/09/09 STUDENT ROLL.NO-RD3803B52 STUDENT ROLL.NO-RD3803B52 SECTION NO. SECTION NO. D3803 D3803 DECELERATION: - DECELERATION: - I declare that this assignment is my individual I declare that this assignment is my individual work. work. I have not copied from other students work or from any other I have not copied from other students work or from any other source except where due acknowledgement is made explicitly in the source except where due acknowledgement is made explicitly in the text, not has any part being written for me by another person. text, not has any part being written for me by another person. Jivtesh Singh Ahuja Jivtesh Singh Ahuja Evaluator comments……………. Evaluator comments…………….

Transcript of Course Code: Cap211 Course Name: Computer Organization

Page 1: Course Code: Cap211 Course Name: Computer Organization

Course Code: CAP211Course Name: COMPUTER ORGANIZATION AND ARCHITECTURE

HOME WORK -2 HOME WORK -2 COURSE CODE-CAP211COURSE CODE-CAP211

COURSE INSTRUCTOR – Miss Kuljeet COURSE TUTOR – Miss Kuljeet

DATE OF ALLOTMENT – DATE OF ALLOTMENT – 25-09-09 DOS:DOS: 13/09/09

STUDENT ROLL.NO-RD3803B52 STUDENT ROLL.NO-RD3803B52 SECTION NO. SECTION NO. D3803D3803

DECELERATION: - DECELERATION: - I declare that this assignment is my individual work. I declare that this assignment is my individual work. I have I have not copied from other students work or from any other source except where due acknowledgement is not copied from other students work or from any other source except where due acknowledgement is made explicitly in the text, not has any part being written for me by another person. made explicitly in the text, not has any part being written for me by another person.

Jivtesh Singh Ahuja Jivtesh Singh Ahuja

Evaluator comments…………….Evaluator comments…………….

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PART-A

Q1 Design a four bit combinational circuit incrementer and decrementer using full adders.

4-bit combinational circuit using full adder: As increment means adding 1 bit to the least significant bit of the input.. For getting its increment we have to add one carry to each of the full hadder.Full adder increment=A+1

4 bit combinational circuit decremented: We have to perm the operation A-1A-1=A+2’s complement of 1(i.e. 1111)

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Q2. Register A holds the 8 bit binary 11011001. Determine the B operand and the logic microoperation to be performed in order to change the value in A to (a) 01101101 (b) 11111101

Using 01101101A 11011001B 10110100

------------------------A A B 01101101

Using 1111101

A 11011001B 11111101

------------------------AAV B 11111101

Q3. Starting from initial value of R=11011101, determine the sequence of binary values in R after a logic shift left followed by circular shift right, followed by a logical shift right and a circular shiftANS:

Initial value of R= 11011101Logical Shift left= 10111010Circular shift right= 01011101Logical shift right= 00101110Circular right shift= 01011100

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PART-B

Q4. Determine the micro operation that will be executed in the processor when following 14 bit control words are applies 0010100110010100000000000000ANSWER:

(a) 00101001100101:

selA selb seld opr r1 r2 r3 sub

microoperaition= r3 r1— r2(b) 00000000000000:

selA selb seld opr input input none tsfa

microoperation:

output input

Q5.Convert the following arithmetic expressions from infix to RPN

A * B + C * D + E * FA * B + C * D + E F *A * B + C * D E F * +A * B + C D * E F * +AB*CD*EF*++

A * B + A * ( B * D + C * E )

A * B + A * ( B D * C E * + ) A * B + A ( B D * C E * + ) * A B * A ( B D * C E * + ) * + A B * A B D * A C E * + * +

A + B* [ C * D + E * ( F + G )]A +B *[C * D + E * F G + ]A + B * [ C D * + E * F G +]F G + E * C D * + B * A +

A*[B+C*(D+E)] F*(G+H))

A * [ B + C * ( D + E ) ] F G H + * /

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A * [ B + C D E + * ] F G H + * /A B C D E + * + * F G H + * /

Q6. Convert the following from RPN to infixA B C D E + * - /

A B C D + E * - /A B C * D + E - /A B – C * ( D + E) /A / B – C * ( D + E )

A B C * / D - E F / + A B * C / D – E F / +A / B * C D – E F / +A / (B * C – D) E F / +A / (B * C – D) E / F +A / (B * C) – D + E / F