Cost-Oriented Design of a 14-bit Current Steering DAC Macrocell

Ohio UniversityOhio University

School of Electrical School of Electrical Engineering and Engineering and

Computer ScienceComputer Science

May 25-28th, 2003

IEEE International Symposium on Circuits and Systems

Russell P. MohnSarnoff Corporation

Janusz A. StarzykOhio University

May 25-28th, 2003

Outline

• Introduction

• Statistical Yield Model

• Reduction of Systematic Errors

• Design Cost Consideration

• DAC Implementation

• Conclusion and Future Work

May 25-28th, 2003

Introduction Design Consideration based On the Statistical Model Current Source Analysis Reference Circuit Design and Analysis Spreading of the Composite Transistors and Random Walk Thermometer Circuit Design Glitches and Dynamic Performance Architectures and Layout Top Level Simulation Results Estimated Design Performance

May 25-28th, 2003

Organization

• The DNL and INL Specifications

• Design Consideration based On the Statistical Model

• Segmentation of the Composite Transistors and Random Walk

• Glitches and Dynamic Performance

• Architectures and Layout

• Simulation Results

• Summary and Estimated Design Performance Figures

May 25-28th, 2003

INL yield vs. relative current-source matching

May 25-28th, 2003

DNL standard deviation

• for the segmented architecture

• B=4, so to meet the requirements for DNL

LSBI

II B )(

12)( 1

0898.0)(

5.0)(

5678.5)(

I

I

soLSBLSBI

II

May 25-28th, 2003

Segmentation of the Composite Transistors and Random Walk

• depends on the transistor area A and spacing D as

• where A, AVT and S are process related constants

I

I )(

22

2

22

24

2

1)(DS

VV

AA

AI

I

CSTGS

VT

May 25-28th, 2003

Mismatch parameters as reported for various processes

Process 2.5 m CMOS 0.8 m CMOS 0.5 m CMOS 0.25 m CMOS

A % 3.2 2.4 2 1

AVT mVum 35 24 12 8

S %/mm 2 1.2

May 25-28th, 2003

Segmentation of the Composite Transistors and Random Walk

• The random errors are determined by mismatch

• The systematic errors are determined by process,

temperature, and electrical gradients

• In optimally designed DAC the INL and DNL errors

depend only on the random errors level

• Increasing transistor area reduces the random errors.

• The systematic errors are layout-dependent and are

minimized by transistor switching scheme.

May 25-28th, 2003

Random errors - unit transistor requirements

• The minimum area of the unit transistor

2

22

2

4

)(2

1

CSTGS

VT

VV

AA

II

A

Parameters A and AVT are technology dependent

May 25-28th, 2003

The Level of Systematic Errors

• where k=Acell /A>1 is a current cell layout coefficient with Acell -unit current cell area

AkSVV

AA

AI

I N

CSTGS

VT

comb

122

22 2

4

2

1)(

May 25-28th, 2003

Current-source Matching vs. the Design Area

for 12 bit DAC

Green line indicates the effect of systematic errors

May 25-28th, 2003

Basic Current Source

May 25-28th, 2003

Current Source Analysis uneven output voltage

Iout1=13.33mA, Iout2=0 mA, Vout1=1V, Vout2=0 V

reduced output current (uneven load - max voltage on one output zero on another)

Vin Vout VR Vbias Io uA Ioff nA dI nA Vd src Vd c Vgs-Vtc Vdsc Vgs-Vt Vdss vdd

1.2 1 2.12 1.3 1.65 0.05 0.1 2.59 1.57 0.59 1.02 0.58 0.71 3.3

1.2 1 2.12 1.2 1.65 0.06 0.3 2.5 1.53 0.6 0.97 0.58 0.8 3.3

1.2 1 2.12 1.1 1.651 0.05 0.5 2.43 1.53 0.63 0.9 0.58 0.87 3.3

1.2 1 2.12 1 1.651 0.06 0.8 2.35 1.53 0.65 0.82 0.58 0.95 3.3

1.2 1 2.12 0.9 1.652 0.06 0.9 2.27 1.53 0.67 0.74 0.58 1.03 3.3

1 1 1.82 1 1.656 0.1 0.5 2.29 1.48 0.59 0.81 0.58 0.71 3

1 1 1.82 0.9 1.657 0.1 1 2.21 1.5 0.61 0.73 0.58 0.79 3

May 25-28th, 2003

Current Source Analysis uneven output voltage

Vout2Vout1

Io

Vd src

Vd c

Ioff

dI

In order to achieve satisfactory INL levelwe must keep the cut-off current low

ALSBIIINL offoff 65.12

15.90

8192

2

nAA

Ioff 2.185.90

65.1

So the cut-off current is limited by

May 25-28th, 2003

Current Source Analysis even output voltage

Iout1=Iout2=6.66 mA, Vout1=Vout2=0.5V

reduced output current (balanced load - equal output voltages)

Vin Vout VR Vbias Io uA Ioff nA dI nA Vd src Vd c Vgs-Vtc Vdsc Vgs-Vt Vdss vdd

1.2 0.5 2.12 1.3 1.65 0.05 1.8 2.58 1.5 0.58 1.08 0.58 0.72 3.3

1.2 0.5 2.12 1.2 1.65 0.05 1.8 2.5 1.5 0.6 1 0.58 0.8 3.3

1.2 0.5 2.12 1.1 1.65 0.05 2 2.43 1.5 0.63 0.93 0.58 0.87 3.3

1.2 0.5 2.12 1 1.65 0.05 2.1 2.35 1.5 0.65 0.85 0.58 0.95 3.3

1.2 0.5 2.12 0.9 1.651 0.05 2.2 2.27 1.5 0.67 0.77 0.58 1.03 3.3

1 0.5 1.82 1 1.655 0.1 2.2 2.29 1.46 0.59 0.83 0.58 0.71 3

1 0.5 1.82 0.9 1.655 0.05 3.1 2.21 1.46 0.61 0.75 0.58 0.79 3

May 25-28th, 2003

Rrefkohm

VR Vout V Iout mA

0.0001 0.772 2.874 38.320.001 0.776 2.8738 38.317330.036 0.878 2.858 38.106670.075 0.971 2.842 37.89333

0.15 1.112 2.813 37.506670.3 1.3042 2.7585 36.78

0.62 1.5491 2.6436 35.2481.2 1.8297 2.2896 30.5281.8 1.985 1.5588 20.7842.7 2.112 1.0409 13.878674.7 2.2462 0.598 7.97333310 2.3765 0.282 3.7620 2.4591 0.14 1.86666740 2.5196 0.07 0.93333380 2.5666 0.035 0.466667

160 2.6056 0.017 0.226667320 2.64 0.009 0.12

1000 2.6912 0.003 0.04

Reference Resistor and Output Current

][

37][R ref mAI

kout

The following empirical relation holds for Iout<20mA

May 25-28th, 2003

Reference Resistor and Output Current

-3 -2 -1 0 1 2 30

5

10

15

20

25

30

35

40Output current as a function of the reference resistance

log10(Rref)

Iout

in

mA

May 25-28th, 2003

Layout specifications of the 12-bit DAC

DAC is built as a segmented architecture with 8-bit thermometer and 4-bit binary sections (to lower the glitches)

LSB cell area (1/4 of unary source cell) is A=308 m2 with W=17 m and L=18 m

8-bit thermometer decoder is designed in two groups- one with 3 thermometer bits and second with 5 bits (MSBs)

Random walk is implemented with derived permutation sequence to minimize systematic errors

Symmetrical layout, synchronization of control signals, synchronization of unary and binary current source transistor switching, and the cascode structure of the unit current sources control dynamic performance.

May 25-28th, 2003

Spreading of the Composite Transistors and Random Walk

• The random errors are determined by mismatch

• The systematic errors are determined by process,

temperature, and electrical gradients

• In optimally designed DAC the INL and DNL errors

depend only on the random errors level

• Increasing transistor area reduces the random errors.

• The systematic errors are layout-dependent and are

minimized by transistor switching scheme.

May 25-28th, 2003

Reduction of Linear Systematic Errors

• To compensate for linear errors a symmetrical splitting is required

• Each transistor will be split into 4 locations

May 25-28th, 2003

Spreading and random walk comparison

May 25-28th, 2003

Permutation array 2 8 14 25 39 54 72 92 101 118 134 152 168 178 190 194 5 18 33 45 60 78 97 122 145 166 201 205 225 231 240 248 11 29 48 66 84 107 128 158 203 214 243 255 172 169 143 132 21 42 63 86 112 142 174 212 238 186 153 113 28 237 247 77 36 57 81 109 147 183 223 253 164 105 242 256 254 249 244 236 51 75 104 139 181 227 208 129 32 252 56 234 226 224 217 27 69 95 125 171 218 195 116 91 62 239 230 211 209 196 193 184 89 120 155 207 250 126 83 65 41 222 204 189 16 173 162 157 99 136 188 235 156 24 59 38 215 200 180 167 149 144 133 127 115 163 210 179 102 71 232 220 198 13 154 141 121 111 106 103 131 199 221 148 80 53 228 202 177 151 7 117 100 90 85 73 150 197 219 110 68 47 31 187 165 138 114 93 82 64 58 52 160 216 161 17 251 44 206 175 146 119 98 79 61 46 40 37 176 229 137 94 246 35 20 170 135 108 87 67 43 34 26 19 185 233 140 88 241 213 191 159 130 4 76 55 1 22 12 9 192 245 123 74 50 23 182 10 124 96 70 49 30 15 6 3

May 25-28th, 2003

Wiring over the current source array

May 25-28th, 2003

May 25-28th, 2003

Wiring - via Placementin Current Sources

Current sources are connected to horizontal wires sequentially

May 25-28th, 2003

Wiring - Latch to Current Source Connection

May 25-28th, 2003

Wiring - programmable via placement

May 25-28th, 2003

Programmable via placement

second quadrant

May 25-28th, 2003

Layout•Signal S2(32)

•Large capacitive load

•Connects 4 symmetrically spread current sources

•Unary current source 256 turned OFF

May 25-28th, 2003

Layout•Signals S2(32) and S2(33)

•Current sources controlled by S2(33) are far away from those controlled by S2(32)

•Switching sequence designed to minimize systematic errors

May 25-28th, 2003

Layout•Signals S2(32), S2(33), and S2(34)

May 25-28th, 2003

Glitches

• The glitch current

• where Agl is the glitch amplitude, tgl is the glitch period,

and t0 is the synchronization mismatch (delay time)

2

2tanh

2

2sgnexp

2sin

10

1

000

ii

gl

ii

glglglgl

levelleveltt

t

levellevel

ttt

ttttt

Ai

May 25-28th, 2003

Dynamic Performance

• For dynamic performance of DAC due to glitches and parasitic effects the following are recommended: synchronize the control signals of the switching transistors; reduce the voltage fluctuation on the drains of the current sources

during switching carefully switch the current source transistor on/off reduce coupling of the control signals through lowering the

voltage of the power supply of the latches.

increase the output resistance in high frequency applications

May 25-28th, 2003

Dynamic Performance

• The synchronization is achieved by equalizing each latch output load capacitance.

• Using a large channel length unit current source transistor and tuning the crossing point of the switching control signals such that both switches are never switched off at the same time solves voltage fluctuation at the drain problem

• Using an additional cascode transistor increases output impedance for high frequency applications – This architecture has an additional advantage of lowering glitch

energy due to the drain voltage variations of the unit source.

May 25-28th, 2003

Layout

•1 column (8 rows) of latches

•Vertical green wires:

•Latch input from D flip-flops

•Latch output to current source array

•Equal load

May 25-28th, 2003

Simulated Test Conditions

1 2 3Library SSTemp. –40o CVDD 1 VAHVDD 2.97 V

Library TTTemp. 27o CVDD 1.2 VAHVDD 3.3 V

Library FFTemp. 125o CVDD 1.32 VAHVDD 3.63 V

May 25-28th, 2003

Binary Driven LSB Current Sources

May 25-28th, 2003

Layout•Equalizing capacitive load between binary latches and unary latches

•Load determined by total length of wires to unary current sources

Binary wire

Unary wire

May 25-28th, 2003

DNL and INL for Unbalanced Load

0 20 40 60 80 100 120 140-0.06

-0.04

-0.02

0

0.02

0.04

DN

L (L

SB

)

Differential Nonlinearity (DNL), Full Scale V = 1.0V

Condition 2

0 20 40 60 80 100 120 140-0.04

-0.02

0

0.02

0.04

0.06

INL

(LS

B)

input code (base 10)

Integral Nonlinearity (INL), Full Scale V = 1.0V

Condition 2

May 25-28th, 2003

Equalizing the Binary/Unary Latch Loads

May 25-28th, 2003

Digital Sine Excitations

May 25-28th, 2003

Sine Output

May 25-28th, 2003

Single tone output spectrum unmatched latch load

0 1 2 3 4 5 6 7 8 9

x 10-6

-1

-0.5

0

0.5

1

time (s)

sig

na

l

0 1 2 3 4 5 6 7 8 9

x 107

-150

-100

-50

0

Frequency, 0 - 90MHzsource: 180MSPS Binary Latch Load NOT Equalized, Spline Interp

Ma

gn

itu

de

(d

B)

Power Spectrum, fs=180MHz, r=4.789600e+001

SFDR = 73.46 dBSNR = 72.8 dB

May 25-28th, 2003

DNL and INL for Balanced Load Condition 2

0 20 40 60 80 100 120 1400

0.002

0.004

0.006

0.008

0.01

0.012D

NL

(L

SB

)Differential Nonlinearity (DNL)

Condition 2

0 20 40 60 80 100 120 140-3

-2

-1

0

1

2

3x 10

-3

INL

(L

SB

)

input code (base 10)

Integral Nonlinearity (INL)

Condition 2

May 25-28th, 2003

DNL and INL for Balanced Load Condition 1

0 20 40 60 80 100 120 140-0.01

0

0.01

0.02

0.03D

NL

(L

SB

)

Differential Nonlinearity (DNL)

Condition 1

0 20 40 60 80 100 120 140-0.015

-0.01

-0.005

0

0.005

0.01

0.015

INL

(L

SB

)

input code (base 10)

Integral Nonlinearity (INL)

Condition 1

Wider Unary Switches

Wider Unary Switches

May 25-28th, 2003

DNL and INL for Balanced Load Condition 3

0 20 40 60 80 100 120 140-5

0

5

10

15

20x 10

-3

DN

L (

LS

B)

Differential Nonlinearity (DNL)

Condition 3

0 20 40 60 80 100 120 140-6

-4

-2

0

2

4

6x 10

-3

INL

(L

SB

)

input code (base 10)

Integral Nonlinearity (INL)

Condition 3

May 25-28th, 2003

2^12 Ramp

May 25-28th, 2003

2^12 Ramp INL & DNL

•Unbalanced capacitive unary and binary loads

•INL(2^12) < 10*INL(2^7)

•17 days simulation versus 8 hours simulation

0 20 40 60 80 100 120 140-0.06

-0.04

-0.02

0

0.02

0.04

DN

L (L

SB

)

Differential Nonlinearity (DNL), Full Scale V = 1.0V

Condition 2

0 20 40 60 80 100 120 140-0.04

-0.02

0

0.02

0.04

0.06

INL

(LS

B)

input code (base 10)

Integral Nonlinearity (INL), Full Scale V = 1.0V

Condition 2

0 500 1000 1500 2000 2500 3000 3500 4000 4500-0.3

-0.2

-0.1

0

0.1

0.2

DN

L (L

SB

)

Differential Nonlinearity (DNL), Full Scale V = 1.0V

Condition 2

0 500 1000 1500 2000 2500 3000 3500 4000 4500-0.6

-0.4

-0.2

0

0.2

INL

(LS

B)

input code (base 10)

Integral Nonlinearity (INL), Full Scale V = 1.0V

Condition 2

May 25-28th, 2003

DNL and INL for Balanced Load Condition 1 - Vout 1.5V

May 25-28th, 2003

DNL and INL for Balanced Load Condition 3 - Vout 1.5V

0 20 40 60 80 100 120 1400

0.002

0.004

0.006

0.008

0.01

0.012D

NL

(L

SB

)

Differential Nonlinearity (DNL), Full Scale V = 1.5V

Condition 3

0 20 40 60 80 100 120 140-4

-2

0

2

4x 10

-3

INL

(L

SB

)

input code (base 10)

Integral Nonlinearity (INL), Full Scale V = 1.5V

Condition 3

May 25-28th, 2003

Single tone output spectrum matched latch load

May 25-28th, 2003

Single tone output spectrum: Closer Look

May 25-28th, 2003

Terayon Load Analysis (HPADS)

10 MHz signal

10nA (left)

10mA (right)

May 25-28th, 2003

Output of Terayon post-D/A Filter

•Differential Output

May 25-28th, 2003

Output of Terayon post-D/A Filter

•Cutoff around 80 MHz

•Limited Resolution

May 25-28th, 2003

DC Offset Simulation

May 25-28th, 2003

Power Supply Rejection - AC Analysis

AHVDD

out

V

VPSRR 10log20

ThAHVDDRAHVDDout

ThAHVDDRThgsout

VVVVI

and

VVVVVI

2

22

AHVDD

outThAHVDDRAHVDD

AHVDD

outout

V

RVVVV

V

RIPSRR

2log20

log20

10

10

May 25-28th, 2003

Power Supply Rejection - AC Analysis

ThAHVDDR

out

outThAHVDDR

VVV

V

RVVVPSRR

2log20

2log20

10

10

Finally the PSRR depends only on the design voltages

Using the design values

dBPSRR 7.1058.0

2log20 10

Which agrees with the simulation results

May 25-28th, 2003

•Digital inputs along top

•Analog inputs/outputs along bottom

•1716.5µm x 1700.0 µm

•Area = 2.918mm2

•Analog circuitry separated from noisy digital environment•Two guard rings

•40 µm n-well•100 µm p+

Full view of the D/A

Noisy digitalSemi-quiet digitalQuiet analog

May 25-28th, 2003

•Symmetries about orthogonal axes:

•Binary Current Sources

•Unary Current Sources

•Modular design in both digital and analog sections

•Digital inputs have at least 4.46 µm separation

•Reference circuit tightly integrated with sensitive analog circuitry

Full view of the D/A

May 25-28th, 2003

•8 Binary inputs DAC_D(4) ... DAC_D(11) encoded in thermometer code

•D Flip-flop organization

•8 rows x 32 columns

•DAC_D(4) ... DAC_D(6) select 1 of 8 rows

•DAC_D(7) ... DAC_D(11) select 1 of 32 columns

•Column select

•Distributed logic minimizes space

•Local clock drivers

Layout

May 25-28th, 2003

Layout•Distributed thermometer encoder

•D flip-flops above latches

•In black

•1 row select

•1 column select at C(i) and C(i+1)

May 25-28th, 2003

Layout

•1 Column (8 rows) of D flip-flops

•8 complementary signals carried on vertical green wires

•local clock driver, column decode logic

May 25-28th, 2003

Layout

•Clock distribution

•Inverted clk signal to digital input flip-flops

•clk signal split left/right from center

May 25-28th, 2003

Layout

•Vertical green wires:

•Routing from D flip-flops to latches

•Routing from latches to current source array

May 25-28th, 2003

Layout

•Wiring over current source array

•Comp. signals: S1, S2

•32 x 32 wires per quarter unary source

•Shield in met2, met 5

•Horizontal in met3

•Vertical in met4

•Wire width = 0.22 µm

•Wire spacing = 1.0 µm

May 25-28th, 2003

Salient DAC Specifications

•Resolution: 12 bits

•Conversion Rate: 180 MSPS

•Differential current outputs

•20mA at full scale

•Gain Error: ±10% of full scale

•DNL: ±1 LSB INL: ±2 LSB

•Wideband SFDR

•1MHz out: 70dBc, … 80MHz out: 50dBc

•Narrowband SFDR

•1MHz out (within ±100 kHz window): 80dBc

•Max Power: 200mW Power Down: 15uA

•Trise, Tfall (Cl<10pF, Rl=50): 1.6-2.5ns Trise-Tfall: 0.1-0.2 ns

•Glitch Energy Error: 2.0-5.0 pV-s