Cost Effective On-line Cleaning Strategies for Wafer SortCost Effective On-line Cleaning Strategies...
Transcript of Cost Effective On-line Cleaning Strategies for Wafer SortCost Effective On-line Cleaning Strategies...
International Test Solutions
Cost Effective On-line Cleaning Strategies for Wafer Sort
International Test SolutionsJerry Broz, Ph.D.
VP of WW Applications
Reno, NV USA
Probing Process Workshop
October 13 and 14, 2014Ieper, Belgium
J. BrozOct-2014
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Overview
• International Test Solutions Profile
• Short Discussion on the “Need to Clean”
• Cost Effective Materials of Probe Cleaning
• ITS Customer Success Stories
• Summary / Discussion
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International Test Solutions
International Test Solutions Corporate Profile
• Global supplier of high quality yield and utilization improvement products for wafer sort and package test since 1997
– Cost-effective cleaning solutions and industry leading technical services.– Strong IP position for front-end, wafer-sort, and back-end test.
• Managed by highly experienced semiconductor industry personnel with a combined experience of +100 years.
– ITS Branch Offices in Taiwan, Japan, Korea, China, and Singapore.– World-wide sales support network of authorized agents.
• Manufacturing Center for advanced polymer materials research and development– Controlled Compliance Manufacturing methods. – Materials characterization, development, and testing laboratories.
• Award winning Test Analysis Center for electrical test and process characterization– Analytical laboratory focused on probe technology and contactor performance testing.– Cleaning recipe assessment and optimization
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ITS – Increasing Yields and Reducing Costs
Maximized wafer yield
– Controlled and stable CRES
– Reduced site-to-site failure
Increased throughput
– Minimize off-line cleaning
– Extend probe card lifetime
Improved tool uptime
– Reduce operator intervention
– Reduce spare inventories
Increased litho tool output
– Clear “hot spots” w/o downtime
– Perform regular PM cycles
Higher etch tool output
– Clean ESC with closed chamber
– Accelerate wet clean recovery
Lower operating costs
– Extend time between wet cleans
– Lower process kit part usage
Improved first-pass yields
– Improved contact
– Reduced rescreen
Greater throughput
– Minimize off-line cleaning
– Maintaining high UPH
Reduced Cost of Test
– ACC for low downtime
– Tri-temperature capable
Probe Card Clean Test Socket Clean Chuck Cleaning Wafer
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Stable Yield is the TOP GOAL for Wafer Test
• To control wafer test is to control the mechanical contact and the electrical contact between the probes and the DUT.
• Process Monitors• Probe Yield• Binout Metric• Contact Resistance• Probe Mark• Re-Probe / Re-Test• I/O Damage
Apply the least mechanical contact that ensures a reliable electrical contact.
• Control Variables• Probe Force• Overtravel• Probe Placement (XYZ)• Current / Duration• Temperature• Cleaning Execution
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Probe Card Technology Types
Copyright © 2014 by VLSI RESEARCH INC. All rights reserved. Reprinted by SWTW with permission from VLSI RESEARCH INC.
Thanks to John West and Risto Puhakka!
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Why Are There So Many Probe Cards Types ?
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Ap
pro
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)
150 100 80 60 40 20
Approximate Nominal Pitch (um)
MPULogic
(Area Array)
NANDFLASH
Memory
DRAMNOR FLASH
Memory
SoCLogic
TSV
LCDDisplay
No SINGLE solution fits ALL device testing requirements!
PR
OB
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CA
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$
Parametric
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All Solutions MUST be Cleaned during Test!
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Why is CRES Important for Wafer Test ?
• Stable CRES determined by two basic parameters
– METALLIC CONTACT = “Metal-on-Metal Contact” between a probe and device
– FILM RESISTANCE = Non-conductive layers that interfere with METALLIC CONTACT
• pad, probe, film = resistivity values
• H = hardness of the pads, bumps, pillars, etc.
• P = contact pressure applied by probe
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P
H
P
HCRES
filmpadprobe
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Uncontrolled Film ResistanceCreates Critical Yield Fallout
Yield Throughput,Up-time, Re-Test, Probe Card Cost.
Cost of Test
METALLIC CONTACT
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Brandemuehl, et al., SWTW-1999 Cascade MicroTech 121-710-APP-0805
CRES is Affected by Contamination and Debris … It’s a Dirty World in Wafer Level Test …!
• Contamination creates CRES instability– Probes generate, accumulate, and pick up
debris
– Contamination affects data quality and yields
• Debris accumulation affects prober setup– Recognition of tips by the look-up optics is
affected
– Operator assist needed to for setup
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• I/O pad material adheres to the probe tip.
CRES is Affected by Material Transfer
TOE
HEEL
Al
P
O
W
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PAD MATERIAL
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CRES is Affected by Surface Oxides
• FAB processed I/O pads can have layers of oxide(s) or various contamination across the surface
• Build-up of non-conductive layers creates contact reliability issues
“Clean” I/O Pad Not so “Clean” I/O Pad
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Cleaning is Absolutely Needed to Maintain Yield
• Re-sort is needed to maintain production requirements and “recover” good devices.
• Logic testing costs can be 15% or more of the product cost.
• Memory testing costs can be 18% or more of the product cost.
Reduced first pass yield occurs with continuous probing
No Cleaning PerformedMemory Device Testing
Dramatically Reduced Wafer Yield by end of LOT
Wfr 1Yield > 95%
Wfr 25Yield < 30%
Wfr1
Wfr25
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When to Clean ?
• Answer = (no one wants to hear) … IT DEPENDS on the process !
• Better Answer = Clean only when necessary !– Real time data monitoring for a device specific recipe
– Probe-card life is extended due to less cleaning
– Problem = Each product requires a dynamic clean recipe
• Reality = Clean Often (whether it is needed or not) !– CRES sensitive devices with minor optimization
– Probe-card life is extended by other means
– Problem = Process yields acceptable, but it process not optimized
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How Much to Clean ?
• Probe Card Size and Probe Type does not matter ! – If one pin needs cleaning, then the entire probe card gets cleaned.
FREQUENCY OF CLEANING OPERATION
PR
OD
UC
TIO
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OST
STEST Y
IELD
Too little cleaning reduces yields and affects uptime.
Too much cleaning reduces throughput without yield benefits.
TOO MUCH CLEANING
TOO LITTLE CLEANING
OPTIMALCLEANING
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Cleaning Impacts on Cost of Test (CoT)
Throughput nUtilizatio Yield
OverheadCost VariableLifetime
Cost Capital
CoT
LaborMaintenance Spare parts
Cleaning Impact
Data “quality”Open / shorts rate
FPY/ retest rate
Cleaning Impact
UptimeOperator assistPC replacement
MTBR, MTTA, MTTR
Cleaning Impact
Test TimeIndex Time
Number of SitesEffective Throughput
Cleaning Impact
Useful lifetimeReplacement
Cleaning Impact
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Overview
• International Test Solutions Profile
• Short Discussion on the “Need to Clean”
• Cost Effective Materials of Probe Cleaning
• ITS Customer Success Stories
• Summary / Discussion
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What’s the Best Cleaning Process ?
Optimal Cleaning Process
PROBE CARD
• “Conventional” or “Advanced” • Probe Metal and Tip Shape• TD Lifetime Limits• Repair Costs
Operator• Probe to Pad Alignment• Optical recognition• Touch sensor profiling• Manual setup
Test Cell• Prober Make / Model• Cleaning Functions • Cleaning Overdrive• Number of Touchdowns
WAFER PROBER
Metallization• Pad Metal Type• Bump Metal Type• Aluminum, Copper, etc.
Electrical• High Current• CRES • Function Requirements
Temperature• -55C • +25C• +200c
DEVICE UNDER TEST
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1st Function of Prober = PTPA (Probe to Pad Alignment)
• Low and high magnification optical recognition is used to align probe tips (probe card) to probe pads (wafer).
Courtesy of Accretech
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Cleaning for Debris Free Probes and PTPA
• Recognition of the Probe Tip by Prober Look-up Camera– Clean probe tips for accurate Probe-to-Pad Alignment (PTPA).
– Clean probes reduce operator assist during setup.
After Touchdowns on Bond Pads(Mag: 150X)
Image captured from Accretech Prober
After Cleaning Touchdowns(Mag: 150X)
Image captured from Accretech Prober
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2nd Function of Prober = Online Probe Card Cleaning
• Online utilization methods
– Cleaning units that reside within the wafer prober.
– Cleaning wafers 150, 200, and 300-mm for large arrays.
• Advances in cleaning execution performance
– Profiling for surface recognition and consistent cleaning overtravel
– Multi-zonal cleaning for recipe optimization
– Efficient stepping patterns and translation during execution
Cleaning WaferCompatible
Large Area Cleaning UnitMultiple Zone Capable
Multiple Cleaning Plates
Courtesy of Accretech
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ITS Materials for Optimized Cleaning… If it’s dirty ….Let’s Clean It !
• ITS Probe Lap abrasive (lapping) films
– Low wear abrasive cleaning material
– Engineered for flat tip cantilevered, vertical, and MEMS probes
– Cleaning performance across -50C and up to 150C
• ITS Probe Polish polymer materials
– Polishing efficiency with debris collection
– Applicable for MEMS, crown-tip, radius, and vertical probes
– Wide temperature range -50C to +200C
• ITS Probe Form polymer materials
– Aggressive polishing for tip shaping and maintenance
– Used offline to recover tip shape and extend probe card life
– Used online to control CRES and maintain probe tip
ON-LINECLEANING
OFF-LINEFORMING
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Poor Cleaning = High Probe Card Costs !
• FACT = Probe Card companies focus on selling probe cards (not cleaning solutions).
• Most cleaning materials can have wear out rates more than 5X greater than optimized materials engineered for on-line cleaning by ITS.
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Touchdown for Probe Card Lifetime
Customer DesignRequirement
Reduced Costs(reduced spares)
Total Card Expense3X Cards Needed(spares required)
Card 1Optimal Cleaning
Probe Card Life Maximized(ITS Optimized)
Aggressive CleaningReduces Probe Card Life(Not Optimal Material)
Probe Card Actual Lifetime
Card 1 Card 2 Card 3
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• Designed for abrasive probe cleaning.
– Generally used for cantilevered probes.
– Flat-tipped vertical probes.
– Applicable for MEMS / Advanced probes.
• Consistent surface and controlled thickness
– Reduced wear-out during cleaning
– Low debris generation
– Probe tip contact surface finish
• -50C to 150C operating temperatures.
– Proprietary processing
2010 30μ
Green = 3-um grit lapping film
Purple = 1-um grit lapping film
Yellow = 0.5-um grit lapping film
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ITS Probe LapEffective on-line abrasive clean with low wear-out
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ITS Probe PolishEffective and efficient on-line polish and debris removal
• ITS optimized materials for cleaning performance and debris collection for demanding applications.
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Probe Polish 300Probe Polish 70 Probe Polish 150
Polishing Action / Abrasive Cleaning Efficiency
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ITS Probe FormCleaning Materials to Extend Probe Card Lifetime
• ITS off-line cleaning materials have performance for effective and efficient tip shaping, recovery, and maintenance.
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Probe Form 300-15Probe Form 300-03 Probe Form 300-10
Forming Action / Abrasive Efficiency
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International Test Solutions
Overview
• International Test Solutions Profile
• Short Discussion on the “Need to Clean”
• Cost Effective Materials of Probe Cleaning
• ITS Customer Success Stories
• Summary / Discussion
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ITS Customer Success Stories
1.) 300mm Test Structure Probe Process Improvement– Process Improvement for Increased CPW
2.) Process Stability and Yield Improvement– High Volume, Testing House Customer
3.) High Volume Manufacturing (HVM) Improvement – NXP Semiconductor for high volume automotive devices
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Case 1 – Test Structure Probe Process Improvement
• Overview– Contact problems for scribeline test structures
– Frequent operator intervention
– High probe card repair costs
• Objectives for Process Improvement– Reduce operator intervention
– Improve contact during parametric testing
– Reduce repair costs and extend probe card lifetime
– Implement Probe Lap online and Probe Form offline
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Eliminate Debris from Cleaning MaterialProbe Lap implemented for on-line cleaning
Cantilevered Probe TipsDebris Build-up due to Poor Cleaning
ITS Materials ImplementedOn-line Cleaning to Control Debris
Debris from 3M Lapping Film
Debris from Device
Clean Contact Surface
No Debris on Tip Length
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PTPA for Controlled Probing
Y
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Y
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Probe-to-Pad Misalignment Good Alignment For Probing
Probe Mark InspectionShows Poor Alignment
Probe Mark InspectionShows Good Alignment
Probe Mark Inspection is used to determine pad damage and probe mark alignment.
Large marks indicatehigh overtravel
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Sanitized User Application
Improved Test Structure Resistance DataR
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tan
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easu
rem
ents
fro
mSt
rap
ped
Scr
ibe
line
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ctu
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Scribeline Test Structure Touchdowns
SpecificationLimit
Resistance Variance Attributedto Probe-to-Pad Alignment Issues
Improved Probe-to-Pad Alignment Process
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ITS Probe Lap Clean for CRES Recovery
0.0
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Customer Process Dependent
Cleaning ExecutionEnabled on Prober
On-Cleaning ExecutionInitiated for CRES Recovery
1.0
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5.0
6.0
0.0
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Probe Card Life Extension (TIPS Refresher)
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Adherent Bond Pad Debris
16-um 25-um
Presented in collaboration with Dr. Rainer Gaggl (TIPS) at EMTC-2006
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Improvement Summary
• Sort Process Metrics– 2X increase in tester uptime
– Improved probe alignment for less operator assist
– Stable resistance for test structure qualification
• Probe Card Metrics– Probe card repair and replacement costs reduced
– Probe card life increased by ~2.5X through offline repair
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Case 2 – Cost of Test Reduction
• Overview– Probe card lifetime was below requirements
– High repair costs and spares were needed
• Objectives for Sort Process Improvement– Meet (and exceed) probe card touchdown lifetime targets
– Stabilize 1st pass yield and reduce lot-to-lot yield variations
– Reduce mean time between assist (MTBA)
– Implement Probe Lap to reduce probe card costs
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Probe Lap: Precision Abrasive Film
Engineered Surface Maximizes Cleaning Efficiency
ITS Probe Lap (purple)precision 1-um grit film
3M, 3-um grit “pink”266X, Lapping Film
Abrasive Particles
EpoxyBinder
ALL TDs during cleaning cycle on Probe Lapwill make contact with the abrasive surface
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TDs during cleaning cycle will make frequent contact within the regions of epoxy binder
Uniform working surface Non-uniform Bernard Structures
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Customer Benchmark of Cleaning Performance:
Efficient Tip Cleaning and Texturing Verification
Before CleanSolder Residuals on Tip
After “Vertical Option” CleanUsing Probe Lap
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Residual RemovedTip Area Textured
Solder residuals tend to accumulateOn contact area between probe / bump
XY movement at reduced overtravel is highly effective for tip cleaning / texturing
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ITS Cleaning Recipe Suggestions:
Maximize Probe Card Lifetime / Performance
• ITS Vertical Clean Recipe 1 = Square
– Clean Material = 1um Probe Lap (purple)
– Cleaning OD = 15 to 30um
– Square Pattern = 200um side lengths
– Cleaning Rotations per Cycle = 2 to 3 times
– Total Scrub = (200um*4)*2= 1600um
• ITS Vertical Clean Recipe 2 = Octagonal
– Clean Material = 1um Probe Lap (purple)
– Cleaning OD = 15 to 30um
– Octagonal Pattern = 150um side lengths
– Cleaning Rotations per Cycle = 1 to 2 times
– Total Scrub = (150um*8)*1= 1200um
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Reduced CL_ODIs Critical
150um
150um
150um
150um
150um
150um
150um
150um
Each customer process has unique requirements and these recipes are initial guidelines.Consult probe card supplier, as needed, regarding specific process settings.
Reduced CL_ODIs Critical
200um
200um
200um200um
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Device Touchdowns (Thousands)
Clean with Sandpaper Clean with 3M 266X (pink) Clean with ITS Probe Lap
Customer Benchmark for Probe Card Repair Cost Savings:
Vertical Probe Card End of Life Assessment
• ITS Probe Lap = 3M Devices tested before probe card rebuild / end of life
• 3M, 266X pink = 2.3M Devices tested before probe card rebuild / end of life– Probe Lap cleaning provides a 25% increase in probecard lifetime
• Abrasive “Paper” (PC supplier recommended) = 1.3M Devices tested before probe card rebuild– Probe Lap cleaning provides a + 2X increase in probecard lifetime
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Initial Tip Length
End-of-Life Tip Length
“Vertical Clean Option Enabled”Orbital movement or XY translation
during each cleaning cycle execution.
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Customer Benchmark for Process Improvement:
Wafer Yield Gain / Increased OEE for Cost Savings
• Split LOT Comparison for high volume device– 8 test cells with 3M, 266X cleaning recipe provided by PC maker
• Cleaning material cost = $1.8K• Note – probe cards had to rebuilt before completion of experiment
– 8 test cells with ITS, 1um Probe Lap cleaning recipe optimized with ITS• Cleaning material cost = $9.3K• ITS Probe Lap materials can withstand more cleaning rotations than the other “papers”.
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Process Metric Improvements for Test Cells Using Probe Lap On-line Cleaning
Wafer Yield 2 to 3% yield increase
Probe Card End of Life 25% gained for TD lifetime
Estimated Probe Card Savings ~$15K saved per test cell
Uptime 23.6 days gained
Probe Card Rebuild Not Needed
Max. Temperature Performance +150C
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Case 3 – HVM Process Improvement
• NXP Semiconductor – Hamburg– Unstable wafer yields for high value automotive devices
– Cleaning and repair time-consuming
– Probe card repair costs were excessive
• Objectives for Sort Process Improvement– Implement hardware and software upgrades
– Optimize Probe Polish process to maximize yield and uptime
– Reduce probe card repair costs and spares
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NXP Semiconductor, IS Test 2008
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Probe Polish Implemented for On-line Cleaning
• Vertical style cards with pointed tip– Multi-site application
– High current for automotive products
– Test temperatures = -50C to 175C
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Probe Polish 70 Implementation
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Increased First Pass Yield
01 10 11 12 01 02 03 04 05 06 07 08 0902 03 04 0605 07 08 09
92%
86%
84%
82%
80%
78%
76%
74%
72%
88%
Month
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Probe Polish Cleaning
Month
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High Volume DeviceSelected for Process
Improvement
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NXP Semiconductor, IS Test 2008
Poor Cleaning Process
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Reduced Probe Card Repair Events
01 10 11 12 01 02 03 04 05 06 07 08 0902 03 04 0605 07 08 09
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Contact issuesContact issues UnknownUnknown
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Probe Polish Cleaning
Month
Large Inventory ofProbe Cards Reduced
NXP Semiconductor, IS Test 2008
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Poor Cleaning Process
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• Sort Process Metrics– ~2% increase in 1st pass yield
– Test floor capacity increase by ~1.2%
– ~30% reduction in downtime
• Probe Card Metrics– Longer probe card life
– ~5 probe card repairs/day saved
– Overall 50% saving for probe card related costs
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Improvement Summary
J. BrozOct-2014
International Test Solutions
Overview
• International Test Solutions Profile
• Short Discussion on the “Need to Clean”
• Cost Effective Materials of Probe Cleaning
• ITS Customer Success Stories
• Summary / Discussion
46J. BrozOct-2014
International Test Solutions
Summary / Discussion
• Customers demand cleaning processes that maximize Overall Equipment Effectiveness (OEE) and reduce overall cost of test.
• Optimized on-line and off-line cleaning materials and associated processes are a critical part of wafer sort process.
• On-line and off-line cleaning has a direct and measurable impact on the yield, probe card performance, and operating costs.
• Non-optimized cleaning processes affect test results, reduce test hardware life, lower throughput, and decrease up-time.
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“I'm smart enough to know that I'm dumb as the next guy.”
- Richard FeynmanNobel Winner in Physics, 1965
Thanks for Attending !
Questions ???
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IEEE SW Test Workshop – www.swtest.orgJune 7 - 10, 2015, in San Diego, CA, USA
• Want to Learn More !
– All aspects of wafer level testing– Three Day Technical Program – EXPO that showcases key suppliers
• EXPO does not compete with technical program
• Topics include but are not limited to:
– New probe card and contractor technologies– Challenges of 300-mm wafer probing– Monitor and reduction of chip I/O pad damage– Productivity improvements for production– Probe data collection, analysis, and management– Cleaning and cost of ownership – e-Test, Parametric, and Test Structure Testing
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25 Years of Probe Technology
J. BrozOct-2014
International Test Solutions
About the Author
Jerry Broz, Ph.D., has been the Applications Engineering Team Leader and VP of Applications at International Test Solutions since 2003.
Responsible for the ITS branch office teams located in Taiwan, Korea, Japan, China, and Singapore for wafer sort and package test cleaning solutions.
Former Member of Technical Staff with the Worldwide Probe Development Team at Texas Instruments, Inc.
Earned a Ph.D. in Mechanical Engineering from the University of Colorado at Boulder and has over 20 years of experience in various high volume manufacturing and applied research environments.
General Chair for IEEE SW Test Workshop, Sr. Member of the IEEE, and IEEE Golden Core member.
Check out the SW Test web site http://www.swtest.org.
Jerry Broz, Ph.D.VP World Wide ApplicationsInternational Test SolutionsReno, NV 89502
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IEEE SW Test Workshop – www.swtest.orgJune 7 - 10, 2015, in San Diego, CA, USA