CoreRMII v2.0 Handbook - · PDF fileCoreRMII v2.0 Handbook 5 Introduction General Description...

CoreRMII v2.0

Handbook

CoreRMII v2.0 Handbook

CoreRMII v2.0 Handbook 3

Table of Contents

Introduction ..................................................................................................................................5

General Description .................................................................................................................................................... 5

Core Version ................................................................................................................................................................ 5

Supported Families ..................................................................................................................................................... 5

Utilization and Performance ...................................................................................................................................... 5

Functional Block Description ..................................................................................................7

Features ....................................................................................................................................................................... 7

Transmit Block ............................................................................................................................................................. 8

Receive Block .............................................................................................................................................................. 8

Ethernet Frame Format .............................................................................................................................................. 9

Timing Diagrams ......................................................................................................................................................... 9

Tool Flows ...................................................................................................................................11

Licensing .................................................................................................................................................................... 11

SmartDesign .............................................................................................................................................................. 11

Simulation Flows ....................................................................................................................................................... 12

Synthesis in Libero SoC .......................................................................................................................................... 12

Place-and-Route in Libero SoC .............................................................................................................................. 12

Core Interfaces ..........................................................................................................................13

Core Parameters ....................................................................................................................................................... 14

Register Map and Descriptions .............................................................................................15

Ordering Information................................................................................................................17

Ordering Codes ......................................................................................................................................................... 17

List of Changes..........................................................................................................................19

Product Support ........................................................................................................................21

Customer Service ..................................................................................................................................................... 21

Customer Technical Support Center...................................................................................................................... 21

Technical Support ..................................................................................................................................................... 21

Website ...................................................................................................................................................................... 21

Contacting the Customer Technical Support Center ........................................................................................... 21

ITAR Technical Support ........................................................................................................................................... 22


Introduction

General Description Reduced media independent interface (RMII) is a standard interface which helps in reducing the number of

signals required to connect a PHY to a MAC. CoreRMII is responsible for providing the interface between a

standard media independent interface (MII) to RMII conversion. The sixteen-signal MII interface is converted

into six-signal RMII interface.

The IP core adheres to RMII specification v1.2 that has been designed to support the SmartFusion®2 device

family. The SmartFusion2 Ethernet MAC (EMAC) supports IEEE 802.3 10/100/1000 Mbps Ethernet

operation.

Various configuration parameters or generics are applied to CoreRMII core.

Core Version This Handbook applies to CoreRMII version 2.0.

Supported Families SmartFusion2

Utilization and Performance Utilization and performance data is given in Table 1 for the SmartFusion2 (M2S050T) device family. The data given in this table is indicative only. The overall device utilization and performance of the core is system dependent.

Table 1 Device Utilization and Performance

Fa

mil

y

TR

AN

SF

ER

_S

PE

ED

LO

OP

BA

CK

Logic Elements Performance (MHz)

Se

qu

en

tia

l

Co

mb

ina

tori

al

To

tal

%

SmartFusion2

(M2S050T)

100 0 41 39 80 0.08 REFCLK = 308

SmartFusion2 10 0 54 63 117 0.2 REFCLK = 320



Note: The data in this table was achieved using typical synthesis and layout settings. Frequency (in MHz) was set to 100 and speed grade of -1.The parameters TRANSFER_SPEED and LOOPBACK are configured as shown in the table above. The parameter TRANSFER_TYPE is set to full-duplex mode.


Functional Block Description

As shown in Figure 1, CoreRMII consists of two major functional blocks: TX block and the RX block. The IP

core selects either 100 Mbps or 10 Mbps mode based on the configurable parameter ‗TRANSFER_SPEED‘.

RXCLK_M TXCLK_M REFCLK RSTN

MII_TXD[3:0]

MII_TXEN

MII_RXDV

MII_RXERR

MII_COL

MII_CRS

RMII_RXERR

RMII_CRSDV

RMII_RXD[1:0]

RMII_TXEN

RMII_TXD[1:0]TX Block

MII_

Inte

rfa

ce

MII_RXD[3:0]

RM

II_In

terf

ace

RX Block

Figure 1 CoreRMII Block Diagram

Features CoreRMII has the following features:

Provides reduced pin-count interface for Ethernet PHYs

Provides MII interface towards the microcontroller subsystem (MSS)-side and RMII interface on the

PHY-side

Supports 25 MHz clock operation on the MII-side and 50 MHz on the RMII-side for 10/100 Mbps mode

operation

Configurable parameter to select the data rate – 10/100 Mbps

Configurable parameter to enable/disable loopback feature

Supports full-duplex and half-duplex operations


8 CoreRMII v2.0 Handbook

Transmit Block During data transmission, the transmit enable signal (MII_TXEN) is asserted active to indicate the start of an

Ethernet frame, and is held active until the frame's transmission is completed. The EthernetMAC generates

4-bit MII nibble data (MII_TXD[3:0]) at 25 MHz. CoreRMII takes this nibble data and generates 2-bit data at

50 MHz on the RMII interface as output.

In 10 Mbps mode, the MAC provides 4-bit data on the MII interface on every 10th

clock of the 25 MHz MII

clock (effectively modulating to 2.5 MHz for 10 Mbps). CoreRMII takes this nibble data and generates the

2-bit data on every 10th clock of the 50 MHz RMII reference clock (effectively modulating to 5 MHz for

10 Mbps) as output.

Receive Block During reception, the receive data valid signal (RMII_CRSDV) goes active when the frame starts, and is held

active throughout the frame duration. For each clock period in which RMII_CRSDV is asserted,

RMII_RXD[1:0] transfers two bits of recovered data from the PHY. In Receive mode, the PHY sends 2-bit

data (RMII_RXD[1:0]) synchronous to the reference clock on the RMII interface. The RMII module detects

the start-of-frame delimiter to achieve proper synchronization with the start of the frame and then forwards

the 4-bit nibble wide data (MII_RXD[3:0]) to the MII interface and further to the MAC.

In 10 Mbps mode, the PHY generates the 2-bit data (RMII_RXD[1:0]) every 10th

clock of the reference clock

on the RMII interface as output. The RMII module detects the start-of-frame delimiter to achieve proper

synchronization with the start of the frame and then forwards the 4-bit nibble wide data (MII_RXD[3:0]) to the

MII interface and further to the MAC.

Start Frame Detection (SFD)

In order to align the received data from the RMII interface with respect to the REFCLK, the core detects a

pattern of alternating zeroes and ones ending with ones (D5). It uses an 8-bit shift register to capture the

receive data. It then decodes the SFD pattern. Output nibbles on the MII receive interface is output on the

SFD detection.

False Carrier

In addition, CoreRMII IP detects the false carrier condition as signaled by PHY. If the RMII PHY detects a

false carrier (BAD SSD), then it generates a unique pattern of ―10‖ rather than the normal ―01‖ preamble

pattern as output until the end of the receive end. The false carrier can occur only in the beginning of a

packet where the preamble is decoded (that is, RMII_RXD[1:0] = 01). The core detects this condition and

generates false carrier as output by asserting MII_RXER = ‘1‘, MII_RXDV = ‗0‘ and MII_RXD[3:0] = ‘E‘ at the

end of the receive cycle.

Error Detection

CoreRMII also provides RMII_RXERR input. The core on detection of this input asserts the MII_RXERR

output in order to propagate the error.

Collision Detection

The core detects the collision by anding MII_TXEN and MII_CRS and outputs MII_COL signal.

Carrier Sense/Data Valid

The RXDV and CRS signals are multiplexed to one signal on the RMII interface on RMII_CRSDV. The PHY

asserts this signal when the receive medium is non-idle. It is asserted asynchronously on detection of carrier

as per the criterion relevant to Operating mode, that is, 10/100 Mbps.

On loss of the carrier, the de-assertion is synchronous to the cycle of the REFCLK on which the first di-bit of

the nibble data is presented on RMII_RXD[1:0]. If the PHY is left with few more additional bits to present on

the RMII_RXD[1:0] after the de-assertion of the RMII_CRSDV signal, it then asserts the RMII_CRSDV

signal on cycles of REFCLK which presents the second di-bit of the nibble data and de-asserts on the first

di-bit of the nibble data. In this way, MAC can recover MII_RXDV and MII_CRS accurately.

Timing Diagrams


Loopback

In Loopback mode, the RMII_TXD[1:0] and RMII_TXEN are connected to the RMII_RXD[1:0] and

RMII_CRSDV signals respectively. The loopback feature can be used for diagnostic purposes to check the

sanity of the MII and RMII interfaces. This is done by enabling the ‗LOOPBACK‘ parameter.

Ethernet Frame Format An 802.3 Ethernet Frame format is shown in Figure 2.

Figure 2 Ethernet 802.3 Frame Format

Timing Diagrams Figure 3 represents the packet transmitted at 100 Mbps. CoreRMII takes the 4-bit nibble data at 25 MHz on

the MII interface and generates the 2-bit data at 50 MHz on the RMII interface as output.

TXCLK 25 MHz 0

MII_TXEN 1

MII_TXD[3:0] 0

REFCLK 50 MHz 1

RMII_TXEN 0

RMII_TXD[1:0] 0

0ps 100ns 200ns 300ns 400ns

Figure 3 Packet Transmitted on RMII TXD

Figure 4 represents the packet received at 100 Mbps. CoreRMII takes the 2-bit nibble data at 50 MHz on the

RMII interface and generates the 4-bit nibble data at 25 MHz on the MII interface as output.

RXCLK 25 MHz 1

MII_RXDV 0

MII_RXD[3:0] 0

REFCLK 50 MHz 1

RMII_CRSDV 1

RMII_RXD[1:0] 0

MII_CRS 1

0ps 100ns 300ns 400ns 500ns-100ps

Figure 4 Packet Received on MII RXD



Figure 5 represents the false carrier condition on the RMII RXD signal. CoreRMII generates the false carrier

code of MII_RXDV = 0, MII_RXD[3:0] = E, and MII_RXERR = 1 as output at the end of the false carrier

activity.

RXCLK 25 MHz 1

MII_RXDV 0

MII_RXD[3:0] 0

REFCLK 50 MHz 1

RMII_CRSDV 1

RMII_RXD[1:0] 1

MII_CRS 0

0ps 100ns 300ns 400ns 500ns-100ps 200ns

Figure 5 False Carrier Condition

Figure 6 represents the packet received at 100 Mbps. 2 elastic nibbles can be noticed at the end of the

frame received on the RMII interface. The MII_CRS is de-asserted before the elastic nibbles are sent.

RXCLK 25 MHz 1

MII_RXDV 0

MII_RXD[3:0] 0

REFCLK 50 MHz 1

RMII_CRSDV 1

RMII_RXD[1:0] 0

MII_CRS 1

0ps 100ns 300ns 400ns 500ns-100ps

Figure 6 Packet Received on MII RXD with Elastic Nibbles


Tool Flows

Licensing CoreRMII is licensed as register transfer level (RTL). Depending on the license tool flow, functionality may

be limited.

RTL

Complete RTL source code is provided for the core and testbenches.

SmartDesign CoreRMII is preinstalled in the SmartDesign IP Deployment design environment. An example instantiated

view is shown in Figure 7. The core can be configured using the configuration GUI within SmartDesign, as

shown in Figure 8 on page 11.

For more information on using SmartDesign to instantiate and generate cores, refer to the Using DirectCore

in Libero SoC User's Guide.

Figure 7 SmartDesign CoreRMII Instance View

Figure 8 SmartDesign CoreRMII Configuration Window

http://www.actel.com/documents/directcore_in_libero_tutorial_ug.pdf

http://www.actel.com/documents/directcore_in_libero_tutorial_ug.pdf

Tool Flows


Simulation Flows The user testbench for CoreRMII is included in all releases.

To run simulations, the User Testbench flow within SmartDesign should be selected before clicking Save

and Generate on the Generate pane. The User Testbench is selected through the Core Testbench

Configuration GUI.

When SmartDesign generates the Libero SoC project, it installs the user testbench files.

To run the user testbench, the design root must be set to the CoreRMII instantiation in the Libero SoC

design hierarchy pane. ModelSim® can be invoked by clicking Simulation in the Libero Soc Design Flow

window. This runs the simulation automatically.

User Testbench

An example user testbench is included in CoreRMII.

Testcases Testcases

EMAC

Driver

RMII PHY

Driver

CoreRMII

Monitor

Figure 9 User Testbench

As shown in Figure 9, the user testbench instantiates a Microsemi® DirectCore CoreRMII design under test

(DUT). The EMAC driver tasks drives transmit transactions to the MII interface of the DUT. The DUT in turn

converts the transmit transaction into corresponding transmit signals on the RMII interface. The monitor

tasks check Microsemi and determine whether or not the transaction is successful, and display the result.

Similarly, the PHY driver tasks drive the data on the receive signals of the RMII interface of the DUT. The

DUT in turn converts the transaction into corresponding receive signals on the MII interface. The monitor

tasks check and determine whether or not the transaction is successful, and display the result.

Synthesis in Libero SoC By clicking Synthesis in Libero SoC, the Synthesis window appears, displaying the Synplicity

® project.

Synplicity should be set for using the Verilog 2001 standard if Verilog is being used. Run should be selected

to run Synthesis.

Place-and-Route in Libero SoC To invoke Designer, Layout should be clicked in the Libero SoC software. CoreRMII does not require any

special place-and-route settings.


Core Interfaces

Signal descriptions for CoreRMII are defined in Table 2.

Table 2 CoreRMII I/O Signals

Name Direction Description

Clock and Reset Signals

TXCLKM Input MII Transmit Clock

25 MHz

RXCLKM Input MII Receive Clock

25 MHz

REFCLK Input RMII Reference Clock

50 MHz

RSTN Input System reset. Active low asynchronous reset

MII Signals

MII_TXD[3:0] Input MII transmit data

MII_TXEN Input Transmit enable

When HIGH, clock data on TXDF to transmitter (MAC to PHY)

MII_RXD[3:0] Output MII Receive data

MII_RXDV Output Receive data valid

MII_RXERR Output Receive error

MII_COL Output Collision, considered asynchronous

MII_CRS Output Carrier Sense, considered asynchronous

RMII Signals

RMII_TXD[1:0] Output TXD [1:0] contains two bit RMII data to PHY when TX_EN is HIGH. The data rate is

double than that of MAC data rate for nibble data transmit

RMII_TXEN Output Transmit enable output to PHY

When HIGH, clock data on TXDF to transmitter (MAC to PHY)

RMII_RXD[1:0] Input RXD [1:0] contains two bit RMII data from PHY when RX_CRSDV_CTL is HIGH.

The data rate is double compared to the MAC data rate for nibble data receive.

RMII_CRSDV Input Carrier sense Or Data valid (shared signal) from PHY

RMII_RXERR Input Receive Error

Core Interfaces


Core Parameters

CoreRMII Configurable Options

There are a number of configurable options which are applied to CoreRMII as shown in Table 3. If a

configuration other than the default is required, the configuration dialog box in SmartDesign should be used

to select appropriate values for the configurable options.

Table 3 CoreRMII Configuration Options

Name Valid

Range

Default Description

FAMILY 19 - Must be set to the required FPGA family:

19: SmartFusion2

TRANSFER_SPEED 0 or 1 1 0: Select 10 Mbps mode

1: Select 100 Mbps mode

TRANSFER_TYPE 0 or 1 1 0: Select half-duplex mode

1: Select full-duplex mode

LOOPBACK 0 or 1 0 RMII_TXD[1:0] and RMII_TXEN are

loopbacked to RMII_RXD[1:0] and

RMII_CRSDV respectively. This is useful for

diagnostic purpose only.

0: Loopback disabled

1: Loopback enabled


Register Map and Descriptions

CoreRMII does not contain any registers.


Ordering Information

Ordering Codes CoreRMII can be ordered through the local Sales Representative. It should be ordered using the following

number scheme: CoreRMII-XX, where XX is listed in Table 4.

Table 4 Ordering Codes

XX Description

RM RTL for RTL source—multiple use license


List of Changes

The following table lists critical changes that were made in each revision of the document.

Date Change Page

July 2013 Initial Handbook version N/A


Product Support

Microsemi SoC Products Group backs its products with various support services, including Customer

Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This

appendix contains information about contacting Microsemi SoC Products Group and using these support

services.

Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades,

update information, order status, and authorization.

From North America, call 800.262.1060 From the rest of the world, call 650.318.4460 Fax, from anywhere in the world 650. 318.8044

Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers

who can help answer your hardware, software, and design questions about Microsemi SoC Products. The

Customer Technical Support Center spends a great deal of time creating application notes, answers to

common design cycle questions, documentation of known issues and various FAQs. So, before you contact

us, please visit our online resources. It is very likely we have already answered your questions.

Technical Support Visit the Microsemi SoC Products Group Customer Support website for more information and support

(http://www.microsemi.com/soc/support/search/default.aspx). Many answers available on the searchable

web resource include diagrams, illustrations, and links to other resources on website.

Website You can browse a variety of technical and non-technical information on the Microsemi SoC Products Group

home page, at http://www.microsemi.com/soc/.

Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted

by email or through the Microsemi SoC Products Group website.

Email

You can communicate your technical questions to our email address and receive answers back by email,

fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We

constantly monitor the email account throughout the day. When sending your request to us, please be sure

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request.

The technical support email address is [email protected].

My Cases

Microsemi SoC Products Group customers may submit and track technical cases online by going to My

Cases.

http://www.microsemi.com/soc/support/search/default.aspx

http://www.microsemi.com/soc

http://www.microsemi.com/soc/

http://www.microsemi.com/soc/mycases/

http://www.microsemi.com/soc/mycases/

Product Support


Outside the U.S.

Customers needing assistance outside the US time zones can either contact technical support via email

([email protected]) or contact a local sales office. Sales office listings can be found at

www.microsemi.com/soc/company/contact/default.aspx.

ITAR Technical Support For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations

(ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes in the ITAR

drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.

mailto:[email protected]

http://www.microsemi.com/soc/company/contact/default.aspx



http://www.microsemi.com/soc/company/contact/default.aspx#itartechsupport

mailto:[email protected]

http://www.microsemi.com/mycases/

http://www.microsemi.com/soc/ITAR/

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50200439-0/05.13

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