Copper Interconnect Technology - Springer978-1-4419-0076-0/1.pdf · per interconnect are presented....

Copper Interconnect Technology

Tapan Gupta

Copper InterconnectTechnology

123

Tapan GuptaRadiation Monitoring Devices, Inc.Watertown, [email protected]

ISBN 978-1-4419-0075-3 ISBN 978-1-4419-0076-0DOI 10.1007/978-1-4419-0076-0Springer Dordrecht Heidelberg London New York

Library of Congress Control Number: 2009928021

© Springer Science+Business Media, LLC 2009All rights reserved. This work may not be translated or copied in whole or in part without the writtenpermission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York,NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use inconnection with any form of information storage and retrieval, electronic adaptation, computer software,or by similar or dissimilar methodology now known or hereafter developed is forbidden.The use in this publication of trade names, trademarks, service marks, and similar terms, even if they arenot identified as such, is not to be taken as an expression of opinion as to whether or not they are subjectto proprietary rights.

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Dedicated to the memoryof my father, Dr. Gopeswar Gupta,and mother, Dr. Kanak Lata Gupta

&To The Godfather of Modern Electronics,

Dr. John F. Bardeen

Preface

The frontiers of knowledge are advancing at an ever-increasing rate. Today’s discov-eries will tomorrow be part of the toolbox of every researcher. By analogy, the pro-cess of advancing the line of settlements, and cultivating and civilizing new territory,takes place in stages, and the semiconductor industry, which has brought a revolu-tion in modern civilization, is a vivid example. The intellectual foment that markedits beginnings has changed the way we view the physical world forever. Since thecreation of the integrated circuit in 1960 there has been a continuous reduction inthe size of circuits and thus the feature size of devices.

Following Moore’s famous prediction, the number of devices manufactured ona single chip has exceeded the expectation of very large-scale integrated (VLSI)circuits. As a result, new materials are being introduced to meet the challenge of 21stcentury IC technology. The increasing device count accompanied by a shrinkingminimum feature size, which was expected to be smaller than 1 μm before 1990, hasreached 0.1 μm at the beginning of the 21st century. Progress in the developmentof new materials is marching in tandem and with much the same speed as circuitdensity (number of devices per unit square area).

The entire field of VLSI circuits depends upon circuit design, layout of elec-tronic circuitry, process development, and synthesis of new materials. As a result,traditional materials (e.g. copper) are sometimes renewed in a fashion necessary toaccommodate them to modern technology. Mankind has known about copper andits processing for different uses since the prehistoric age. Now, at the beginning ofthe 21st century, the use of copper has opened a new era in the IC manufacturingindustry.

The 1990s were the decade in which copper as an interconnecting material cameto the forefront and gained much attention from microelectronics engineers and sci-entists. The metallic conductivity and resistance to electromigration of bulk copper(Cu) are better than aluminum (Al). But as the feature size of the Cu-lines forminginterconnects is scaled, the resistivity of the lines is seen to increase. At the sametime, the electromigration and stress induced voids due to increased current den-sity become reliability issues. Innovative ideas like the use of a cobalt-tungsten caplayer and alloying of copper have worked well, but both come with an increased RCproduct line.

vii

viii Preface

The use of Cu-interconnect has introduced the additional burden of integrationof the barrier layer in Cu-damascene architecture. The barrier layer affects the resis-tance of the Cu-lines too. The PVD-Cu/PVD-Ta interface is “magical” and the useof precursors in the ALD/CVD (Atomic Layer Deposition/Chemical Vapor Deposi-tion) system has raised several questions, although the advantages of ALD in com-parison to the PVD system in producing perfect step coverage with very thin layersis clear.

In the field of low-K, time-dependent dielectric breakdown (TDDB) and inter-layer dielectrics (ILDs), reliability is becoming more important. As the dimensionsshrink, the stress gradients increase because the same amount of stress is confinedwithin a reduced geometry. Moreover, these low-K materials are softer than SiO2and susceptible to failure.

There are many challenges and difficulties with copper interconnect but not with-out any gain. Most of the challenges are overcome partially by using advancedinstrumentation and photolithography materials. Photolithography has come a longway from 365 nm exposure technology to 157 nm exposure technology. Use ofadvanced laser systems with lower radiation wavelengths, additional hardware, andenhancement techniques, have all contributed to these improvements.

In 1997 IBM and Motorola introduced new approaches to Cu-interconnectingtechnology and in September 1997 IBM demonstrated their complementary metaloxide semiconductor (CMOS) device with six layers of copper lines. At the endof the decade, copper damascene processes were introduced and the century-oldchemical mechanical polishing (CMP) procedure was renewed to integrate copperin deep sub-micron level circuitry.

This book was developed from a series of lecture notes prepared for graduate stu-dents of different universities. The notes are based on the research and publicationsof countless scientists and engineers engaged in this field. I express my sincerestthanks and gratitude for their indirect help.

Copper Interconnect Technology is the first book on the subject to treat materi-als, technology, and applications comprehensively, and is a product of my 25 yearsof research and teaching experience in different universities and research organiza-tions. It is written for professionals as well as graduate students, and belongs on thebookshelf of workers in several microelectronics disciplines.

The chapters of the book are arranged sequentially following the sequence ofthe damascene process. In Chapter 1 basic properties of the materials used in cop-per interconnect are presented. Chapter 2 deals with the low- and high-K dielectricmaterials (dealing with the physical, chemical, and structural properties) that areof potential interest for scaled-down, high-speed devices. The diffusion of Cu insilicon is well known, so Chapter 3 is devoted to the search for new barrier materi-als and metal complexes to minimize diffusion of Cu from Cu interconnects. Someof the promising barrier materials, their physical and chemical properties, and theinterpretation of binary and ternary phase diagrams, are also discussed.

Chapter 4 addresses different resist materials (DUV and EUV) and lithographytechniques that are being used or are in the development stage. Pattern generation

Preface ix

technologies together with different etching systems applied in the modern IC indus-try are also considered.

As the state of the art of modern integrated circuit technology has changed fromthe subtractive aluminum metallization process to via and trench filling additive Cu,the deposition technology has also evolved. Chapter 5 covers different depositiontechnologies that are frequently used in the modern Cu-damascene process. Chapter6 deals with the damascene procedure and the chemical mechanical planarization(CMP) process.

Cu-interconnect replaced Al-interconnect because of its higher bulk-conductivityand electromigration resistance. But as the feature size of the conducting lines isshrinking, the thin metal lines can no longer retain the bulk properties of the metal.In Chapter 7 the conductivity and electromigration properties of Cu-interconnectinglines are discussed. Chapter 8 deals with the routing design of the Cu-interconnectstogether with the reliability issues of the scaled Cu-lines forming interconnects.

Watertown, Massachusetts Tapan K. Gupta

Acknowledgments

A book of such diversity would not have been possible without the indirect helpof many research workers, engineers, and teachers. Virtually all of the informationpresented here is based on my lectures to graduate students of different universities.The notes were prepared from the research work of countless scientists and engi-neers engaged in this field. Their contributions are recognized to a small degree byciting some of their work in references at the end of the chapters. I also wish toacknowledge the work of the people who are not cited directly but who have con-tributed indirectly to the development of the book. My sincerest thanks go to them.

The entire manuscript has been read by Dr. Rafael Reif, Provost, and for-mer Professor and Head, Electrical Engineering Department, MIT, Cambridge,Massachusetts and Dr. K.N. Tu, Professor of The Henry Samueli School of Engi-neering and Applied Science, and former Head of the Department of MaterialsScience and Engineering, University of California, Los Angeles, California(UCLA). The author is grateful to them for their help.

The author also expresses his gratitude for the encouragement receivedfrom Professor Carl Thompson, Rickey/Nelson Professor, MIT, Cambridge,Massachusetts, Professor Krishna Saraswat, ECE Department and Professor Rein-hold Dauskardt, Materials Science, Stanford University, CA, and Professor P.S. Ho,Professor, University of Texas, Austin, TX. I am grateful to the anonymous review-ers for their comments and criticism that have helped in shaping the book.

I have taken many illustrations and materials from different journals and maga-zines. I want to express my sincerest thanks to all the authors and the staff membersfor their permission to reproduce these in my book.

Most of all I want to thank my wife Arundhati, my daughter Atreyee, and myson-in-law Jesse, for the love, understanding, patience, and impatience that madethe preparation of this book possible.

Tapan K. Gupta

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Trends and Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Physical Limits and Search for New Materials . . . . . . . . . . . . . . . . . . . 51.3 Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.4 Choice of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4.1 Why Copper (Cu) Interconnects? . . . . . . . . . . . . . . . . . . . . . . . 71.5 New Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.5.1 Multilayer Metal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 151.5.2 Substrate Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.6 An Alternate Technology for Interconnects . . . . . . . . . . . . . . . . . . . . . . 191.7 Materials Used in Modern Integrated Circuits . . . . . . . . . . . . . . . . . . . . 21

1.7.1 Properties of Copper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231.7.2 Grain Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241.7.3 Melting Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.8 Barrier Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271.9 Low-K Dielectric Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281.10 Polymers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301.11 Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.11.1 Silicon (Si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331.12 Challenges and Accomplishments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.12.1 Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351.12.2 Accomplishments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.13 Technologies of the 21st Century, and the Plan to Meetthe Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.14 Ultra-Shallow Junction (USJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401.15 Circuit Design and Architecture Improvements . . . . . . . . . . . . . . . . . . 411.16 Performance and Leakage in Low Standby Power (LSTP) Systems . . 421.17 Introduction of New Materials and Integration Processes . . . . . . . . . . 43

1.17.1 Nano-Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441.17.2 Superconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451.17.3 Integration Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1.18 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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2 Dielectric Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672.2 Interlayer Dielectric (ILD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712.2.2 Mathematical Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742.2.3 Selection Criteria for an Ideal Low-K Material . . . . . . . . . . . . 762.2.4 Search for an Ideal Low-K Material . . . . . . . . . . . . . . . . . . . . . 782.2.5 Achievement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832.2.6 Impact of Low-K ILD Materials on the Cu-Damascene

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922.2.7 Deposition Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

2.3 High-K Dielectric Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972.3.2 Impact on Scaling and Requirements . . . . . . . . . . . . . . . . . . . . 982.3.3 Search for a Suitable High-K Dielectric Material . . . . . . . . . . 992.3.4 Deposition Technology for High-K Materials . . . . . . . . . . . . . 1022.3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

3 Diffusion and Barrier Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113.1 Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113.1.2 Transitional Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133.1.3 Mathematical Modeling of Diffusion in Cu-Interconnects . . . 1143.1.4 Grain Boundary (GB) Diffusion . . . . . . . . . . . . . . . . . . . . . . . . 1183.1.5 Vacancy Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203.1.6 Drift Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213.1.7 Interdiffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223.1.8 Diffusion of Copper and Its Consequences . . . . . . . . . . . . . . . 1223.1.9 Precipitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

3.2 Barrier Layer for Cu-Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253.2.1 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253.2.2 Ideal Barrier Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263.2.3 Barrier Layer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263.2.4 Interlayer Reactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283.2.5 Influence of the Barrier Layer Properties on the Reliability

of Cu-Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323.2.6 Low-K Dielectric-Barrier Layer . . . . . . . . . . . . . . . . . . . . . . . . 1353.2.7 Reaction Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353.2.8 Influence of the Barrier Layer on the Electrical

Conductivity of Cu-Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393.2.9 Influence of Barrier Layer Thermal Conductivity

on Cu-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413.2.10 Classification of Barrier Layer . . . . . . . . . . . . . . . . . . . . . . . . . 144

Contents xv

3.2.11 Properties of Different Barrier Layer Materials . . . . . . . . . . . . 1453.2.12 Cap-Layer, Its Properties and Functions . . . . . . . . . . . . . . . . . . 148


4 Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614.1 Photolithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614.1.2 Resolution Limits of Optical Lithography . . . . . . . . . . . . . . . . 1644.1.3 Deep Ultraviolet (DUV) Lithography . . . . . . . . . . . . . . . . . . . . 1684.1.4 Reticles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734.1.5 Enhancement Techniques for Resolution . . . . . . . . . . . . . . . . . 1754.1.6 157 nm Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794.1.7 Chemically Amplified Resist (CA) . . . . . . . . . . . . . . . . . . . . . . 1834.1.8 Extreme Ultraviolet (EUV) Lithography . . . . . . . . . . . . . . . . . 1854.1.9 e-Beam Lithography (EBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894.1.10 Electron-Beam Resist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1924.1.11 e-Beam Reticle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1954.1.12 Step and Flash Imprint Lithography (SFIL) . . . . . . . . . . . . . . . 195

4.2 Etching and Cleaning of Damascene Structures . . . . . . . . . . . . . . . . . . 1974.2.1 Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974.2.2 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210


5 Deposition Technologies of Materials for Cu-Interconnects . . . . . . . . . . . . 2235.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235.2 Emerging Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

5.2.1 Cu-Damascene Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2245.2.2 Barrier Layer Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

5.3 Deposition Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2255.4 Thin Film Growth and Theory of Nucleation . . . . . . . . . . . . . . . . . . . . 226

5.4.1 Nucleation Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2275.5 Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

5.5.1 Physical Vapor Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305.5.2 Sputtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2315.5.3 Ionized Physical Vapor Deposition (IPVD) . . . . . . . . . . . . . . . 234

5.6 Chemical Vapor Deposition (CVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365.6.1 Plasma Enhanced CVD (PECVD) System . . . . . . . . . . . . . . . . 2365.6.2 Metal-Organic Vapor Deposition (MOCVD) . . . . . . . . . . . . . . 238

5.7 Low Temperature Thermal CVD (LTTCVD) System . . . . . . . . . . . . . . 2405.8 Atomic Layer Deposition (ALD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2415.9 Plating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

5.9.1 History of Electroplating and Printed CircuitBoards (PCBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

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5.9.2 DC Bath Chemistry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2445.9.3 Electroplating of Copper Inside Damascene Architecture . . . 245

5.10 Process Chemistry for Superconformal Electrodepositionof Copper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

5.11 Electrochemical Mechanical Deposition (ECMD) . . . . . . . . . . . . . . . . 2485.12 Influence of the Seed Layer on Electroplating . . . . . . . . . . . . . . . . . . . . 2495.13 Electroless Deposition of Copper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2505.14 Stress in Cu-Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2515.15 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

6 The Copper Damascene Process and Chemical Mechanical Polishing . . 2676.1 The Copper Damascene Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

6.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2676.1.2 Conventional Metallization Technology . . . . . . . . . . . . . . . . . . 2706.1.3 Cu-Damascene Metallization Technology . . . . . . . . . . . . . . . . 2716.1.4 General Objectives and Challenges . . . . . . . . . . . . . . . . . . . . . . 276

6.2 Chemical Mechanical Polishing (CMP) and Planarization . . . . . . . . . 2786.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2786.2.2 Chemical Mechanical Polishing (CMP)Technology . . . . . . . . 2796.2.3 Copper Dishing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2856.2.4 Slurry Chemistry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2866.2.5 Particle Size Inside the Slurry . . . . . . . . . . . . . . . . . . . . . . . . . . 2876.2.6 Relative Velocity of the Pad and Wafer . . . . . . . . . . . . . . . . . . 2896.2.7 Pad Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2896.2.8 Pad-Elasticity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2896.2.9 Pad Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2896.2.10 Shallow Trench Isolation (STI) . . . . . . . . . . . . . . . . . . . . . . . . . 2906.2.11 Abrasive Free Polishing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2916.2.12 End-Point Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2916.2.13 Dry In Dry Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2926.2.14 Multi-Step Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2936.2.15 Post-CMP Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2936.2.16 CMP Pattern Density Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . 295


7 Conduction and Electromigration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3017.1 Conduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

7.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3017.1.2 Conduction Mechanism and Restrictions . . . . . . . . . . . . . . . . . 3037.1.3 Effect of Grain Boundary (GB) Resistance on the

Conductivity of Cu-Interconnects . . . . . . . . . . . . . . . . . . . . . . . 3117.1.4 Effect of Grain Size and Morphology of the Substrate . . . . . . 311

Contents xvii

7.1.5 Morphology of the Cu-Film and Its Influence on theConduction (Electrical) Mechanism of Cu-Interconnects . . . 312

7.1.6 Effect of Film Thickness on the Conductivityof Cu-Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

7.1.7 Diffusion Related Impacts on the Conductivityof a Cu-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

7.1.8 Cu-Line Stress and Its Consequences . . . . . . . . . . . . . . . . . . . . 3197.1.9 Conduction of Heat Through Cu-Interconnects . . . . . . . . . . . . 3217.1.10 Thermal Cycling (Annealing) Related Phenomena . . . . . . . . . 322

7.2 Electromigration (EM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3247.2.1 Electromigration (EM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3247.2.2 Mechanism of Electromigration (EM) and Its Effects . . . . . . 3257.2.3 Void Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3297.2.4 Analytical Model on Stress Related EM . . . . . . . . . . . . . . . . . 3307.2.5 Effect of Microstructure of the Film on Mass Migration . . . . 3337.2.6 Effect of Solute on Electromigration . . . . . . . . . . . . . . . . . . . . 3357.2.7 Melting Temperature of a Metal and Its Effect on Grain

Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3357.2.8 Effect of Temperature on EM . . . . . . . . . . . . . . . . . . . . . . . . . . 3367.2.9 Current Density and Its Effect on EM . . . . . . . . . . . . . . . . . . . 336


8 Routing and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3478.1 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

8.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3478.1.2 Methods of Improving Interconnect Routings . . . . . . . . . . . . . 3498.1.3 Interconnect Routing Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 3518.1.4 Challenges with High Density Routing . . . . . . . . . . . . . . . . . . 3598.1.5 Cascaded Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3618.1.6 Transmission Line Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . 3618.1.7 Clocking of High-Speed System . . . . . . . . . . . . . . . . . . . . . . . . 361

8.2 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3628.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3628.2.2 Reliability Issues Related to Cu-Interconnects . . . . . . . . . . . . 3658.2.3 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388


Glossary (Copper Interconnects) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Author Biography

Tapan K. Gupta received his Master of Science degree in Physics from the IndianInstitute Technology, a PhD degree in Physics from Boston College, and was a Post-Doctoral Fellow in the Electrical Engineering and Communication Department atLehigh University, Pennsylvania. A former Analog Devices Career DevelopmentProfessor in the Electrical Engineering and Computer Science Department at TuftsUniversity, an International Rotary Foundation Scholar, and recipient of a TeachingExcellency Award, Dr. Gupta is currently a Chief Materials Scientist performingresearch in the field of Nuclear Medicine in collaboration with different universitiesand industries at Radiation Monitoring Devices, Massachusetts. Dr. Gupta has 25years of teaching and research experience at different universities and industries inthe USA and 75 peer reviewed articles in the fields of physics, materials science,semiconductor physics, and nuclear medicine. Dr. Gupta is the author of the bookHandbook of Thick and Thin Film Hybrid Microelectronics published by John Wileyand has authored a book chapter on solar cells and materials for Allied Publication,New Delhi.

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