COPious-PXIe - FPGA & Data Acquisition Systems … · Isometric view of COPious-PXIe front bezel,...

COPious-PXIe

DESCRIPTIONCOPious-PXIe is a user-customizable, PXIe plug-in card thatincludes two A9 CPU cores. Linux runs in core 0 to provideEthernet, USB and disk connectivity while core 1 runs real-timestand-alone applications. COPious-PXIe is compatible withInnovative's wide assortment of ultimate-performance FMCmodules. With its modular IO, scalable performance and easy touse CPU core architecture, the COPious-PXIe reduces time-to-market while providing the performance you need.

Distributed Data Acquisition – Put the COPious-PXIe at the datasource and reduce system errors and complexity. Available IEEE-1588 network or GPS-synchronized timing, triggering and samplecontrol is available for remote IO. Limitless expansion via multiplenodes.

Uniquely customizable – An HPC FMC site for IO, user-programmable FPGA for IO interfaces, on-board GbE and USB.Stand-alone, autonomous operation with precision-timed samplingon FMC data.

Autonomous – Boots Petalinux and user application code from flashwhen installed in a standard 8HP PXIe chassis slot. Ready forembedded operation.

12V +/- 5% DC-Only Operation - Perfect for offloading real-timeapplications and functionality within a larger PXIe test environment.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Innovative Integration products and

disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Innovative Integration standard warranty. Production processing does not necessarilyinclude testing of all parameters.

©2016 Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com01/18/17

FEATURES• Combines an Zynq Z7045 SoC with FMC IO

module in a compact, stand alone design• Powerful, dual, floating-point ARM A9 CPU

performance• 8HP PXIe form factor• Self-bootable, stand-alone operation• Able to operate diskless and headless• Runs Linux applications• Configurable IO uses standard HPC FMC IO

module. Add anything from RF receivers to industrial control modules.

• IO site (VITA 57) deliver up to 6 GB/s to PL memory, 2 GB/s to PS memory

• IEEE-1588 or GPS-disciplined clock from backplane routed to FMC module PLL matrix

• Supports Innovative FMC IO module features for private data channels, triggering and timing features

• USB 2.0, 1 Gb Ethernet, eMMC, SPI, RS232 ports

• Boots Linux from on-board eMMC device• 12V +/- 5% DC operation

APPLICATIONS• Embedded instrumentation • Remote, autonomous IO• Lab/Factory automation • Distributed data acquisition

SOFTWARE• Linux/Windows -host compatible• Runs Petalinux on Core 0• Runs standard desktop applications• Eclipse C++ Developers Kit supporting IO

integration and customization• Device drivers, example software and support

applets supplied for all peripherals

Single Board Computer with HPC FMC IO Site

V0.2 01/17/17

http://www.innovative-dsp.com/

COPious-PXIe

This electronics assembly can be damaged by ESD. Innovative Integration recommends that all electronic assemblies and components circuits be handled with appropriate precautions. Failure to observeproper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not tomeet its published specifications.

ORDERING INFORMATIONNote: Please consult the Carsharp Production Selection Flowchart here to best understand the configuration options for thisproduct.

Product Part Number Description

COPious-PXIe 80358-0-L0 COPious-PXIe - with Zynq Z7Z045 SoC with dual A9 CPU, active heat sink and fan, 2.5 GB DDR2, 32MB Flash, 32 GB eMMC, 2x USB 2.0, 10/100/1000 GbE, 1x RS232. Approx 12W consumption.

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http://www.innovative-dsp.com/myii/dl_Docs.php?file=Cardsharp_Configuration_Guide1.pdf&product=Cardsharp&ref=/cgi-bin/dlDocs.cgi?product=Cardsharp

COPious-PXIe


Figure 1. COPious-PXIe Block Diagram


COPious-PXIe


Figure 2. Zync SoC block diagram


COPious-PXIe

Isometric view of COPious-PXIe front bezel, HPC FMC-site and fan-cooled Zynq Z7045 SoC FPGA.

Front view of COPious-PXIe front bezel.

Rear view of COPious-PXIe PXIe backplane connector.

Top viewof COPious-PXIe showing FMC site and fan assemblyatop Zynq Z7045 SoC FPGA.



COPious-PXIe

Standard FeaturesZ7045 SoC

CPU Dual ARM® Cortex-A9 MPCore. NEON™& Single / Double Precision Floating Point for each processor

Cache L1: 512KB, L2: 256KB

DDR2 Memory

2x 512 MBx16 for PS (CPU)3x 512 Mbx16 for for PL (Logic)

Logic Cells 444K

Block Ram 3.020 KB

DSP Slices 2020

Tranceivers 16

IO Ports

USB 1x, USB 2.0, Type A rear panel port

UART 1x RS232

GPIO 8 bits, direction is bit-programmable

QSFP 1x Aurora, 40 Gbps (bidirectional)

Ethernet 1x 10/100/1000 Mbps

FMC Sites

Module Sites 1

Standards VITA 57.1 FMC VITA 20 Conduction cooling

Size 69 x 76.5 mm, 10mm mezzanine height

CPU Connections

FMC Site 0: HPC

eMMC FLASH Drive

Capacity 32 GB

Type Embedded Flash

Use Boot drive or data storage

Timing and Triggering Support Features

Sample Clock Sources

PXIe Backplane, FMC site

Trigger Modes Software, PXIe backplane-synchronized,external input

Trigger Outputs FMC site (FMC module type dependent)

Trigger Inputs 1 SSMC on FMC site

Clock input Use as sample clock or FMC Reference; SSMC on FMC site.

Module Synchronization

Simultaneously across mesh via PPS/matched reference clocks



COPious-PXIeCustomization Features

FPGA Xilinx Zynq 7045 SoC FPGAControls triggering and has 34 pin connections to FMC MezzanineMemory-mapped Interface to A9 CPU coresFrameWork Logic available for FPGA in VHDL

Power Requirements

Input 12V +/- 5% DC

Consumption Varies according to FMC module requirements8W: COPious-PXIe with no FMC

Power Management

Power States Low power states supported including wake features from CPU and LAN

Temperature Monitors

2 total : Zync SoC and COPious-PXIe assembly each have a temperature sensor

Alarms Software programmable warning and failure levels

Over-temp Monitor Disables power supplies

Conductive Cooling Conduction cooling supported for COPious-PXIe assembly includes heat conduction bars on each edge and VITA57 pattern for FMC module

Fans Single integrated fan controller

Physicals

Form Factor PXIe 3U x 8 HP

Weight 1500g (est.)

Hazardous Materials Lead-free and RoHS compliant

MTBF ~42,000 Hours



COPious-PXIeABSOLUTE MAXIMUM RATINGS!Exposure to conditions exceeding these ratings may cause damage!

Parameter Min Max Units Conditions

Supply Voltage 11.4 12.6 V

Operating Temperature 0 60 C Non-condensing, forced air cooling required

Storage Temperature -65 +150 C

ESD Rating - 1k V Human Body Model

Vibration - 5 g 9-200 Hz, Class 3.3 per ETSI EN 300 019-1-3 V2.1.2(2003-04)

Shock - 40 g peak Class 3.3 per ETSI EN 300 019-1-3 V2.1.2 (2003-04)



COPious-PXIeArchitecture and FeaturesThe COPious-PXIe combines dual ARM A9 CPU cores with an HPC FMC IO module and high-speed connectivityperipherals to create a autonomous signal processing board for a variety of applications.

Embedded CPU cores

The Zynq Z045 SoC is a dual A9 CPU core combined with user extensible FPGA fabric that provides a real-time computingengine, suitable for high-speed signal processing while consuming minimal footprint and power.

Embedded CPU #0 boots into Linux, which provides sophisticated, mature drivers to high performance connectivityperipherals such as the 1 GbE ethernet port, QSFP port, eMMC flash memory and USB port. USB storage devices aresupported, to support data logging at rates to 480 Mb/s to each device. Embedded CPU core #1 boots a user-written stand-alone application to perform real-time I/O via the FMC module. This provides optimal, minimal latency interaction with theFMC peripherals and resources, without inducing OS or stack latencies of any kind. The best of both worlds: high-performance connectivity via CPU 0, determinicity and speed via CPU 1.

Each A9 CPU core is mapped directly to the FMC module. The CPU bus tightly couples the CPU to the FMC modules andthe SoC DMA engines may be used to accelerate I/O, outperforming Innovative's previous generation SBC systems by 2 to 4times. Bidirectional data transfer rates between logic memory and FMC resources occur at full memory bus rates: 6000MB/s.

The COPious-PXIe provides familiar core interfaces for expansion and connectivity: Gigabit Ethernet, USB ports, andeMMC disk, as well as numerous connectivity interfaces such as RS232 and SPI.



COPious-PXIe

XP3 Connectors

XP3/XJ3 are the XMC PCI Express connectors to the host.

Column

Row A B C D E F

1 XMC_P15_TX0_P XMC_P15_TX0_N NC XMC_P15_TX1_P XMC_P15_TX1_N 12P0V_XMC

2 DGND DGND XMC_JTRST_N DGND DGND XMC_MRSTI_N


4 DGND DGND XMC_JTCK DGND DGND NC


6 DGND DGND XMC_JTMS DGND DGND NC


8 DGND DGND XMC_JTDI DGND DGND NC

9 NC NC NC NC NC 12P0V_XMC

10 DGND DGND XMC_JTDO DGND DGND NC

11 P15_RX_0_P P15_RX_0_N NC P15_RX_1_P P15_RX_1_N 12P0V_XMC

12 DGND DGND NC DGND DGND DGND


14 DGND DGND NC DGND DGND NC



17 P15_RX_6_P P15_RX_6_N NC P15_RX_7_P P15_RX_7_N XMC_RFU12


19 PEX_REFCLK0_P PEX_REFCLK0_N NC NC NC NC

Table 1: P15 Signals



COPious-PXIeSignal Name Description

1 NC No Connect. Do not connect any signals (including ground) to these pins

2 DGND Board Ground

3 12P0V_XMC Carrier +12V power input. If this power is present, COPious-PXIe on-board power input (J5) must be left unconnected; otherwise the board might be damaged.

4 XMC_P15_TX0_P/XMC_P15_TX0_Nto XMC_P15_TX7_P/XMC_P15_TX7_N

High-speed transmitter differential pairs. Typically used for PCIe bus (up to 8 lanes) connection, carrier being the host. Signal direction is from the module (module drives these signals). Can be also used in a QSFP high-speed port.

5 XMC_P15_RX0_P/XMC_P15_RX0_Nto XMC_P15_RX7_P/XMC_P15_RX7_N

High-speed receiver differential pairs. Typically used for PCIe bus (upto 8 lanes) connection, carrier being the host. Signal direction is to the module (module receives these signals). Can be also used in a QSFP high-speed port.

6 PEX_REFCLK0_P/PEX_REFCLK0_N PCIe Reference Clock (differential) from the carrier board.

7 XMC_MRSTI_N PCIe reset signal.

8 XMC_JTRST_N JTAG Reset signal from the carrier. Used as a board master reset on COPious-PXIe.

9 XMC_JTCK JTAG Clock signal from the carrier.

10 XMC_JTMS JTAG Mode Select signal from the carrier.

11 XMC_JTDI JTAG Data Input signal from the carrier (module input).

12 XMC_JTDO JTAG Data Output signal from the module (module output).

13 XMC_RFU12 Not used, reserved for future use.

Table 2: P15 Signal Description

Notes:

1. JTAG signals are also available on connector J3, exposed via the front panel bezel.

2. JTAG signals are 3.3V LVCMOS.



COPious-PXIe

FMC IO Site

A single HPC FMC IO module site enables the COPious-PXIe to be configured with a wide variety of IO personalities. TheFMC site is for FPGA mezzanine cards conforming to VITA 57.1 standard, which are 69 x 75 mm modules. The module siteis designed to support cooling via convective airflow provided by the PXIe chassis.

Innovative offers FMC IO offering a range ofanalog performance mated to the high performanceFPGA computing cores within the Zynq SoC.Innovative's Velocia architecture data packetsystem allows these modules to stream datacontinuously to Zynq system memory at rates limited only by the memory subsystem – making the COPious-PXIe well suited for real-time control, digital signal processing and applications requiring deterministic, low-latency.

Special features supporting all Innovative FMC module are provided in the COPious-PXIe for simultaneously sampling, triggering and controls. System triggers and matched clocks from an externally-supplied clock or reference provide simultaneously sampling for the two modules. The FMC module site has 66 differential connections plus eight 12.5 Gbps SERDES links to the on-board FPGA, providing ample bandwidth for even the fastest FMC modules.

Triggering and Sample Clocks

The COPious-PXIe has unique clocking and triggering features for the FMC module. The site receives two triggers from theapplication FPGA and two clock inputs through its connector. Innovative modules can use these to support simultaneoussampling and unique trigger scenarios using the application FPGA.

Sample clocks for the FMC site can be synchronized using an optional GPS or IEEE-1588 reference or from an externalclock input. FMC module PLLs can use either the external clock input or the disciplined clock as a reference. The disciplinedclock allows multiple, remote instruments to sample simultaneously and act cooperatively. Position and time data is alsoavailable from the GPS when installed.

Remote Operation

COPious-PXIe can be operated using Ethernet as a remote computer or embedded instrument. For pure embedded operation,the COPious-PXIe can operate “headless” without monitor, keyboard or mouse. The system boots from an onboard QSPIand eMMC FLASH, providing reliable operation even in a rugged environment. This provides independence from the PXIesystem controller providing greater determinicity, lower latency and application reliability.

Application FPGA

The Zynq Z7045 provides a large, user-programmable on-chip FPGA which allows the COPious-PXIe to be customized formany IO functions, such as triggering and control features. This FPGA is memory-mapped peripheral to the Zync SoC CPUs.New functions can added to the system by adding them to the FPGA design. FPGA logic is provided in the FrameWorkLogic tools, which includes the standard functionality that can be modified or used as an example.

Software ToolsSoftware development tools for the COPious-PXIe provide comprehensive support application development including devicedrivers, peripheral configuration and control, and utilities that allow developers to be productive from the start. Softwareclasses provide C++ developers a powerful, high-level interface to the system devices that makes system integration andachieving real-time, high speed data acquisition easier.


FMC Modules for IO

- Flexible, modular IO- Industry-standard VITA 57.1- Up to 6000 MB/s transfer rates - Industry-standard, multi-vendor


COPious-PXIeSoftware for data logging and analysis are provided with every Innovative FMC module. Data can be logged to systemmemory at full rate or to disk drives at rates supported by the drive and controller. Triggering and sample rate controls areprovided to support data acquisition applications without writing code. Innovative software applets include Binview whichprovides data viewing, analysis and import to MATLAB for large data files.

Support for Eclipse C++ is provided. The PetaLinux OS is supported. For more information, the software tools User Guideand on-line help may be downloaded.

Logic ToolsCustomized IO interfaces, triggering and other unique features may be added to the COPious-PXIe by modifying the FPGAlogic. The FrameWork Logic tools provide support for VHDL/Verilog developments. Application logic can be modified bybuilding upon the Innovative components for hardware interfaces and system functions. Each design is provided as a XilinxVivado project with VHDL source for top level logic with a modeling test-bench illustrating logic functionality.

FMC ModulesPlug FMC modules into the COPious-PXIe to build your custom, PXIe plug-in card. Innovative Integration offers an array ofultra-performance, CPU FMC modules to create your solution.

Innovative FMC module families feature analog and digital IO with FPGA computing cores on high performance CPU modules. The FrameWork Logic development tools allow you to design in MATLAB and VHDL and rapidly implement highspeed signal processing on the FMC.

See the full list of Innovative FMC modules here.



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COPious-PXIeIMPORTANT NOTICESInnovative Integration Incorporated reserves the right to make corrections, modifications, enhancements, improvements, andother changes to its products and services at any time and to discontinue any product or service without notice. Customersshould obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All products are sold subject to Innovative Integration’s terms and conditions of sale supplied at the time of orderacknowledgment.

Innovative Integration warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with Innovative Integration’s standard warranty. Testing and other quality control techniques are used to theextent Innovative Integration deems necessary to support this warranty. Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.

Innovative Integration assumes no liability for applications assistance or customer product design. Customers are responsiblefor their products and applications using Innovative Integration products. To minimize the risks associated with customerproducts and applications, customers should provide adequate design and operating safeguards.

Innovative Integration does not warrant or represent that any license, either express or implied, is granted under anyInnovative Integration patent right, copyright, mask work right, or other Innovative Integration intellectual property rightrelating to any combination, machine, or process in which Innovative Integration products or services are used. Informationpublished by Innovative Integration regarding third-party products or services does not constitute a license from InnovativeIntegration to use such products or services or a warranty or endorsement thereof. Use of such information may require alicense from a third party under the patents or other intellectual property of the third party, or a license from InnovativeIntegration under the patents or other intellectual property of Innovative Integration.

Reproduction of information in Innovative Integration data sheets is permissible only if reproduction is without alteration andis accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information withalteration is an unfair and deceptive business practice.

Innovative Integration is not responsible or liable for such altered documentation. Resale of Innovative Integration productsor services with statements different from or beyond the parameters stated by Innovative Integration for that product orservice voids all express and any implied warranties for the associated Innovative Integration product or service and is anunfair and deceptive business practice. Innovative Integration is not responsible or liable for any such statements.

For further information on Innovative Integration products and support see our web site:

www.innovative-dsp.com

Mailing Address: Innovative Integration, Inc.

741 Flynn Road, Camarillo, California 93012

Copyright ©2016, Innovative Integration, Incorporated




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