Controlling Linewidth Roughness in Step and Flash Imprint Lithography

Gerard M. Schmida, Niyaz Khusnatdinova, Cynthia B. Brooksa, Dwayne LaBrakea, Ecron

Thompsona, Douglas J. Resnicka*, Jordan Owens b, Arnie Fordb, Shiho Sasakic, Nobuhito Toyamac, Masaaki Kuriharac, and Naoya Hayashic, Hideo Kobayashid, Takashi Satod, Osamu Nagarekawad,

Mark W. Harte, Kailash Gopalakrishnane, Rohit Shenoye, Ron Jihe, Ying Zhangf, Edmund Sikorskif, Mary Beth Rothwellf, Shusuke Yoshitakeg, Hitoshi Sunaoshig, Kenichi Yasuig aMolecular Imprints, Inc., 1807C West Braker Lane, Austin TX 78758, USA bSematech ATDF, 2706 Montopolis Drive, Austin, Texas 78741-6499, USA

cElectronic Device Laboratory, Dai Nippon Printing Co., Ltd., 2-2-1, Fukuoka, Fujimino-shi, Saitama 356-8507, Japan

dHOYA Corporation R&D Center 3-3-1 Musashino,Akishima-shi,Tokyo 196-8510 Japan eIBM Almaden Research Center, 650 Harry Road San Jose, CA 95120-6099, USA

fIBM Thomas J. Watson Research Center, 1101 Kitchawan Road, Route 134Yorktown Heights, NY 10598-0218, USA

gNuFlare Technology, Inc., 8, Shinsugita-cho, Isogo-ku, Yokohama 235-0032, Japan

ABSTRACT

Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits.

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (imprint mask). As a high fidelity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions. Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size. Keywords: S-FIL, template, imprint lithography, replication, linewidth roughness

*dresnick@militho.com; phone: 512 339-7760; fax: 512 339-3799; www.molecularimprints.com

1. INTRODUCTION Despite the remarkable progress made in the past decade in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. LWR guidelines for the industry are very aggressive. Table 1 depicts the ITRS 2006 roadmap for LWR as a function of both year and DRAM half pitch. Table 1. ITRS roadmap for linewidth roughness (LWR), starting at the 65nm half pitch and extending out to 16nm. Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography (S-FIL®) operates in a step-and-repeat fashion: the processes of deposition of imprint material, imprint, alignment, photocuring and release all occur sequentially as each die on a wafer is patterned.1,2 S-FIL utilizes UV-curable liquids that are dispensed in a drop-wise fashion to meet the local pattern density requirements of the template structures, thus enabling imprint patterning with a uniform residual layer. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template mold. As a high fidelity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions. Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing any linewidth roughness falls to the template fabrication process. Increasing the sensitivity of chemically amplified resists has been shown to cause increased LWR in both EUV and electron beam exposure processes. Non chemically amplified resists, such as ZEP520A, have excellent resolution but are not nearly as sensitive and can produce features with very low LWR. Non chemically amplified resists are therefore much better candidates for high resolution imprint templates. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final patterned substrate.

2. EXPERIMENTAL DETAILS

Templates used for analysis in this work were supplied by both Dai Nippon Printing (DNP) and Hoya. The bas ic process used to fabricate the templates is briefly described. Exposures were performed with either 50 kV variable shaped beam (VSB) pattern generators or 100 kV Gaussian beam (GB) pattern generators. Both a positive tone fast chemically amplified resist and a slower non-chemically amplified resist were employed on the VSB writers. ZEP520A was used in all cases when writing on GB systems. After exposure and development of the resists, the chromium and fused silica were etched using Cl2/O2 and fluorine-based chemistry, respectively. The details of the process are discussed in References 3 and 4. Mesa lithography and a mesa etch process, followed by a dice and polish step were employed to create a finished 65 mm x 65 mm template.5

Imprinting of the template pattern was performed by using a Molecular Imprints Imprio 250 imprint tool. A Drop-On-Demand method was employed to dispense the photo-polymerizable acrylate based imprint solution in field locations across a 200 mm silicon wafer. The template was then lowered into liquid-contact with the substrate, displacing the

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solution and filling the imprint field. UV irradiation through the backside of the template cured the acrylate monomer. The process was then repeated to completely populate the substrate. Details of the imprint process have previously been reported.6 SOI wafers were etched using an Applied Materials capacitively-coupled etch chamber. Oxide wafers were etched in a Trion reactive ion etch chamber. LWR measurements were performed two different ways. In the first case, high resolution SEM images were taken with a JEOL JSM-6340F field emission cold cathode SEM equipped with a tungsten emitter. The accelerating voltage can be varied from 0.5 to 30 kV. The system has intrinsic 1.2 nm resolution capability at 15 kV accelerating voltage, and 2.5nm at 1 kV. Critical dimension (CD), linewidth roughness, and line edge roughness (LER) data were then extracted offline using the SIMAGIS® automated image metrology software suite from Smart Imaging Technologies. For the analysis of some of the etch work, an AMAT NanoSEM was used to collect information on CD. LWR and LER. The beam accelerating voltage was 500V. 1200 pixels were used per scan line and 256 lines were scanned for each feature.

3. RESULTS

LWR was analyzed using eight different templates. Five different studies were performed: a) LWR from imprints obtained with a template fabricated using a VSB pattern generator and a fast CA resist, b) CD and LWR for 30nm and 40 nm semi-dense structures, evaluated after imprint, and after SOI etch, c) CD and LWR analysis for dense 42nm lines, starting at imprint, and ending after a clean process following an oxide etch, and d) an analysis of CD and LWR of the template and the imprinted images for features sizes ranging from half pitches of 32nm to 44nm. A 100 KV Gaussian beam pattern generator was used for cases b, c, and d. e) LWR from templates and imprints fabricated using a VSB pattern generator and a slower high resolution resist a. Imprints from a VSB Template Fast chemically amplified resists are typically used in the fabrication of 4X photomasks and have also been employed when writing full field 1X templates. Previous publications have noted that resolution is typically limited to 60nm with this type of processing.7,8 LWR is also impacted, and Figure 1 shows an example of the LWR obtained from 90nm dense lines using a template fabricated with a fast CA resist. SIMAGIS software was used to analyze CD, LWR and LER. Four lines were measured, with a sampling step of 3.79nm. The mean LWR was 11.27nm, with a 3σ variation of 1.37nm. The large LWR is primarily attributed to shot noise limitations during the exposure process.9,10 Other templates created with somewhat slower CA resists have yielded somewhat better LWR results (< 8nm, 3σ), but nothing approaching the values suggested by the ITRS roadmap. Figure 1. Linewidth roughness (LWR) for 90nm half pitch imprinted lines. The template used to imprint these features was fabricated using a fast chemically amplified resist.

90nm HP90nm HP

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b. 30nm and 40nm Semi-dense Features The templates evaluated in the next three sections were all written using ZEP520A, a high resolution positive electron beam resist from Nippon Zeon. Depending on the amount of biasing employed and developer used, the dose required at 100 kV can vary from 100 µC/cm2 to over 300 µC/cm2.4 Given the improved electron statistics, it is expected that the LWR would be significantly reduced. The first samples that were analyzed consisted of 30nm and 40nm semi-dense patterns that are being used to test addressing schemes for ultra -high density memory.11,12 Portions of a typical test structure are shown in Figure 2. Figure 2a shows a SEM image of the template for the 30nm test structures. Figure 2b shows the corresponding imprint of the test structure. The etched SOI fins, with apparently very smooth sidewalls, are shown in Figure 2c, and Figure 2d shows a cross section TEM image of the SOI fins after additional processing.

Figure 2. 30nm semi -dense structure: a) Template, b) imprinted features, c) etched SOI fins, and d) cross-section of etched fins after additional processing.

Figure 3. LWR and LER measurements of the 30nm and 40nm semi-dense features after etch.

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SIMAGIS measurements of the imprinted 30nm lines revealed an LWR of 2.43nm, 3σ. After imprinting, wafers were etched. Wafers 1 and 25 were analyzed via CD-SEM, to obtain a more complete statistical view of the variations within a field, from field to field, and from wafer to wafer. Figure 3 shows the LWR and LER results for a single set of 30nm and 40nm lines. LWR was comparable to the starting imprinted LWR, and LER was much less than 2.0nm. Fifteen lines across five fields were also measured on wafers 1 and 25, and the results are shown in Figure 4. It is interesting to note that not only does the CD track from line to line, but so does the LWR. At 30nm, the correlation between wafer 1 and 25 is 0.928 for CD and 0.528 for LWR. At 40nm, the correlation between wafer 1 and 25 is 0.907 for CD and 0.954 for LWR. These results lead us to believe that the imprint process yields both highly reproducible CD and LWR from field-to-field.

Figure 4. Critical dimension (CD) and LWR for the 30nm and 40nm features after etch for two different wafers. Note the good correlation for both CD and LWR.

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c. 42nm Dense lines A 42nm design template (supplied by DNP) provided a first opportunity to track CD and LWR for dense features through etch. Process steps examined included imprint, descum, oxide etch and wet clean. The results of this study are shown in Figure 5. The center eight lines of a ten line pattern were analyzed with respect to CD, LWR and LER. The outer lines were not included to avoid possible asymmetric etch effects. After imprint, the mean LWR measured 2.8nm. The statistics for the imprinted features are shown in the bottom right hand corner of the image. It is interesting to observe that lines 1 and 2 have a difference in LWR of approximately 1nm, yet the scanned image (bottom left) gives no indication of any obvious difference in line roughness. The conclusion drawn is that for these values of LWR, it is not possible to distinguish differences between 2nm and 3nm of LWR, and that better methodologies will be necessary to characterize LWR values less than 2nm, 3σ. As the wafer was processed, LWR remained low, and to within measurement error, no discernable difference in LWR could be detected. Figure 5. CD and LWR for 42nm dense lines starting with the imprint process and ending with a clean process after etch. LWR is less than 3nm, and is nearly constant throughout the process. d. 32nm Dense Lines A template containing both dense and semi-dense features ranging in size from 32nm to 44nm provided an opportunity to compare LWR between the starting template and the imprinted images. SEM images of the template, provided by DNP, are shown in Figure 6. The graph, to the right of the images, plots CD and LWR as a function of coded CD. CD remained linear (to within 5%) across all feature sizes, and LWR measured 3.1nm and was nominally independent of feature size. Imprint results with this template are shown in Figure 7a. Three imprints of the 32nm patterns had a mean LWR of 2.73nm, closely tracking what was observed in the template. The mean CD for all fifteen lines was 34.72nm, with a 3σ variation of only 1.62nm.

Imprint Descum Oxide Etch CleanCD 41.3.nm 39.3nm 40.7nm 38.4nmLWR 2.8nm 2.5nm 2.7nm 2.9nm

2.172.542.042.082.402.462.412.04LER Right <3s > nm

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87654321Results / Line

Imprint StatisticsImprint Statistics1 2 3 4 5 6 7 8

Figure 6. a) Template SEMs for CDs ranging from 32nm to 44nm. b) CD and LWR as a function of coded CD. CD response is linear, while LWR is independent of feature size. Two additional templates with minimum CDs of 28nm and 26nm were also imprinted to observe if low values of LWR were maintained. One example is shown in shown in Figure 7b. LWR from the 28nm and 26nm features measured 3.60nm and 3.15nm, respectively. Figure 7. a) 32nm imprints from the template shown in Figure 6. LWR of the imprint is comparable to that seen in the template. b) An imprint at 26nm (right image. Image courtesy of Toshiba.). LWR remains low.

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e. Analysis of all GB data Figure 8 shows a plot of LWR versus CD from all of the high resolution features in this study and includes all of the data from templates, imprints, and etched wafers. The data set consisted of one hundred and thirty measurements, and the mean LWR was 2.87nm. The lowest observed LWR was 1.70nm, which is the target value for LWR 32nm DRAM half pitch in 2013. To first order, LWR is independent of both feature size and process step, for the processes employed in this study. Figure 8. LWR as a function of feature size for all lines measured. To first order, LWR is independent of feature size and process step. f. VSB Pattern Generation using ZEP520A The resist processes developed for sections b, c and d were then applied to VSB writers, in order to understand the effect on LWR. For these experiments, an EBM-5000 and the EBM-6000 variable shape beam pattern generators from NuFlare Technology were used to pattern the images on the substrates. Several key specifications of the EBM-6000, resulting in improved performance over the EBM-5000 include higher current density (70 A/cm2), astigmatism correction in the subfields, optimized variable stage speed control, and improved data handling to increase the maximum shot count limitation. Figure 9. Dense lines on a template fabricated with a NuFlare EBM-5000 and ZEP520A resist.

4 Total # lines measured: 1304 LWRmean = 2.87nm4 LWRmin = 1.70nm4 LWRmax = 4.39nm4 3σ = 1.71nm

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Figure 10. 33nm and 39nm dense lines imaged using an EBM-6000 and ZEP520A resist. The resist thickness was 50nm. A negative bias of -12nm was also applied in order to improve resolution and reduce LWR. Figure 11. LWR for all templates exposed using ZEP520A. The LWR obtained from exposures on VSB systems is improved relative to the results obtained on VSB systems using a chemically amplified resist. The LWR from lines defined in Figures 9 and 10 was measured and included with the data shown in Figure 8. The result is shown in Figure 11. For the case when the EBM-5000 was used, the LWR varied between 4 and 7nm, which is a significant reduction relative to the LWR obtained using a chemically amplified resist (see Figure 1). It was noted that

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LWR did increase as feature size approached 32nm. When the improved resis t process was applied on the EBM-6000, an additional improvement (of about 2nm) in LWR was obtained for the smallest features measured. The LWR is still higher than what was obtained on Gaussian beam writers, and the process continues to be refined in order to further reduce LWR.

4. CONCLUSION

LWR, a critical parameter for determining device performance, has been characterized for the S-FIL process. Advantages of using low sensitivity electron beam resists , such as ZEP520A, and Gaussian beam pattern generators were observed. LWR was characterized on the template, after imprint, and after etch into two different substrates. In the case where Gaussian beam pattern generators were used, LWR was independent of feature size (measured down to 20nm) and process step. Extremely low values were noted: 2.87nm on average, with a minimum of 1.70nm. Improvements in LWR were also noted when using ZEP520A on NuFlare VSB systems. Future work will determine if these low values can be achieved when writing full field templates with high resolution resists on VSB pattern generators.

ACKNOWLEDGMENTS

The authors appreciate the support of S. V. Sreenivasan and Mark Melliar-Smith. This work was partially funded by DARPA (AP2C Grant H$001-06-1-0005) and NIST-ATP.

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