CONTROL CODE DEVICE FUNCTION CONNECTOR ......HW TYPE : Customer Evaluation Z 1:1 02_041351 D2 Neil L...
10
JUN-2017 AS PER ECR-069788 D-2 AS PER ECR-067076 N. WILSON FEB-2017 D N. WILSON AS PER ECR-067075 N. WILSON N. WILSON N. WILSON INITIAL RELEASE A B C AS PER ECR-061220 25-JAN-2017 1 10 <User Define> <User Define> <User Define> : Pitch-pitch StyleVendor Style PACKAGE : 400-lead N/A BGA-family : Power Product(s): AD9364 HW TYPE : Customer Evaluation Z no_template D2 CodeID 1:1 02_041351 TBD - - - W. Burton - Neil L Wilson - - - - REV 2 REVISIONS 1 OWNED OR CONTROLLED BY ANALOG DEVICES. THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP# USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER 8 CONNECTOR FUNCTION CODE DEVICE 2 2 6 JUMPER TABLE 4 7 5 A 3 DATE APPROVED D B DESCRIPTION 3 4 OFF ON 5 5 7 OEM PART# HANDLER 6 C B 8 SOCKET OEM BK/BD SPEC. P.O SPEC. A 1 RELAY CONTROL CHART 3 1 4 C NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS CHECKER DESIGNER PTD ENGINEER TEST ENGINEER DECIMALS X.XXX +-0.005 X.XX +-0.010 MASTER PROJECT TEMPLATE TOLERANCES +-1/32 FRACTIONS +-2 SIZE D D SCHEMATIC DRAWING NO. SCALE CODE ID NO. SHEET OF REV. D A A E N VC LG S E O DATE ANGLES UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES TESTER TEMPLATE TEMPLATE ENGINEER HARDWARE SERVICES HARDWARE SYSTEMS COMPONENT ENGINEER TEST PROCESS HARDWARE RELEASE * SEE ASSEMBLY INSTRUCTIONS CONTROL D
Transcript of CONTROL CODE DEVICE FUNCTION CONNECTOR ......HW TYPE : Customer Evaluation Z 1:1 02_041351 D2 Neil L...
JUN-2017AS PER ECR-069788D-2
AS PER ECR-067076 N. WILSONFEB-2017D
N. WILSON
AS PER ECR-067075
N. WILSON
N. WILSON
N. WILSON
INITIAL RELEASEA
B
C
AS PER ECR-061220
25-JAN-2017
1 10
<User Define><User Define><User Define>
: Pitch-pitch StyleVendor StylePACKAGE : 400-lead N/A BGA-family
: PowerProduct(s): AD9364HW TYPE : Customer Evaluation Z
no_template
D2CodeID1:1
02_041351TBD
-
-
-
W. Burton
-
Neil L Wilson
-
-
-
-
REV
2REVISIONS
1
OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP#USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER
8
CONNECTORFUNCTIONCODE DEVICE
2
2
6JUMPER TABLE
4
7
5
A
3
DATE APPROVED
D
B
DESCRIPTION
34
OFFON
5
57
OEM PART# HANDLER
6
C
B
8
SOCKET OEMBK/BD SPEC.P.O SPEC.
A
1
RELAY CONTROL CHART
3 14
C
NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS
CHECKER
DESIGNER
PTD ENGINEER
TEST ENGINEER
DECIMALS
X.XXX +-0.005X.XX +-0.010
MASTER PROJECT TEMPLATE
TOLERANCES
+-1/32FRACTIONS
+-2SIZE
DDDD
SCHEMATIC
DRAWING NO.
SCALE CODE ID NO.
SHEET OF
REV.
DA A
ENV C
L GSE
ODATE
ANGLES
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES
TESTER TEMPLATE
TEMPLATE ENGINEER
HARDWARE SERVICES
HARDWARE SYSTEMS
COMPONENT ENGINEER
TEST PROCESS
HARDWARE RELEASE
* SEE ASSEMBLY INSTRUCTIONS
CONTROL
D
MODULE (DAUGHTER BD)
BANK_501
REVERSE CURRENT PROTECTION
PHY1
2 10
<DESIGN_VIEW>
: PowerProduct(s): AD9364HW TYPE : Customer Evaluation Z
1:1
D202_041351
Neil L Wilson
BSS138TA
1K
4.7UF
1K
1K
1K
4.99K
4.99K
10KDNI
10K10K
1K
10KDNI
0.1UF
0.1UF
4
0.1UF
2
0.1UF
3
0.1UF 0.1UF
0.1UF 0.1UF 0.1UF
31
4.7UF
10UF 4.7UF 1UF
0.1UF0.1UF 0.1UF 4.7UF
0.1UF
43
10K
0.1UF
42
4.7UF
51
1UF
1UF
52
10K
1UF 1UF 1UF 1UF
1K
100OHM
L0805
L0805
100OHM
41
L0805
100OHM
24MEGHZ
CDSOT23-SR208
0.1UF
220
220
BSS138TA
BSS138TA
0
39
BSS138TA
8.06K
88E1512-56QFN
27PF 27PF
XC7Z020-1CLG400I
USB3320C-EZK
BSS138LT1G
0.1UF
25MEGHZ
0
C50
R15
R14
R16
R11
R50
R26
R8R7
R13
R37
C242
C224 C225 C226
C217 C214
C201 C211 C203
C49
C210 C218 C219
C208C75 C73 C63
C212
R27
C206 C74
C58
C78
R178
C184 C181 C182 C183
R191
R194
R3
C32
C126
C60C59
Y2
U1
R176
Y3
Q5
Q1
R17
Q2
Q4
R18
Q3
R12
U10
E14
E15
E16
R175
U16
U15
PS_MIO21_501_ETH0_TX_CTL
VCCPCOM-1P8V
USB_OTG_P
USB_OTG_N
PS_MIO30_501_USB0_STP
PS_MIO07_500_USB_RESET_BVCCPCOM-1P8V
CARRIER_RESET
VCCPCOM-1P8V
PS_MIO17_501_ETH0_TX_D0
VCCPCOM-1P8V
VCC-3P3V-IO
PHY1_1V8
VCC-3P3V
PHY1_AVDD_1V8_OUT
S_IN_P
S_IN_N
PHY1_AVDD_1V8
PHY1_AVDD_1V8_OUT
PS_MIO16_501_ETH0_TX_CLK
PS_MIO20_501_ETH0_TX_D3
PS_MIO19_501_ETH0_TX_D2
S_OUT_N
S_OUT_P
PHY1_1V8
PHY1_AVDD_3V3
PS_MIO08_500_ETH0_RESETN
ETH_MD4_N
ETH_MD4_P
ETH_MD3_N
ETH_MD3_P
PHY1_LED_0
PHY1_LED_1
ETH_MD1_N
ETH_MD2_P
PHY1_VDD_3V3PHY1_1V8
PHY1_AVDD_1V8
PHY1_VDD_3V3
PS_MIO27_501_ETH0_RX_CTL
PS_MIO22_501_ETH0_RX_CLK
PS_MIO23_501_ETH0_RX_D0
PS_MIO24_501_ETH0_RX_D1
PS_MIO25_501_ETH0_RX_D2
PS_MIO26_501_ETH0_RX_D3
PHY1_1V8
PHY1_AVDD_1V8
PHY1_AVDD_1V8
VCCPCOM-1P8V
PS_MIO29_501_USB0_DIR
PS_MIO36_501_USB0_CLK
ETH_PHY_LED1
PHY1_VDD_3V3
PS_MIO17_501_ETH0_TX_D0
VCCPCOM-1P8V
PHY1_DVDD_1V0
USB_OTG_P
3.3V
PS_MIO32_501_USB0_D0
USB_OTG_CPEN
USB_VBUS_OTG
USB_ID
ETH_MD2_N
VCC-3P3V-IO
USB_OTG_N
PS_MIO37_501_USB0_D5
PS_MIO31_501_USB0_NXT
PS_MIO39_501_USB0_D7
PS_MIO28_501_USB0_D4
PS_MIO35_501_USB0_D3
PS_MIO34_501_USB0_D2
PS_MIO33_501_USB0_D1
ETH_MD1_P
ETH_PHY_LED0
PHY1_VDD_3V3
PHY1_AVDD_3V3
PHY1_VDD_3V3
1.8V
PS_MIO29_501_USB0_DIR
PS_MIO31_501_USB0_NXT
PS_MIO33_501_USB0_D1
PS_MIO35_501_USB0_D3
PS_MIO38_501_USB0_D6
PS_MIO40_501_SD0_CLK
PS_MIO42_501_SD0_DATA0
PS_MIO46_501_JX4
PS_MIO48_501_JX4
PS_MIO50_501_SD0_CD
PS_MIO52_501_ETH0_MDC
PS-SRST#
PS_MIO28_501_USB0_D4
PS_MIO30_501_USB0_STP
PS_MIO32_501_USB0_D0
PS_MIO34_501_USB0_D2
PS_MIO39_501_USB0_D7
PS_MIO41_501_SD0_CMD
PS_MIO47_501_JX4
PS_MIO49_501_JX4
PS_MIO51_501_JX4
PS_MIO53_501_ETH0_MDIOVCC-3P3V-IO
PHY1_LED_1
PS_MIO43_501_SD0_DATA1
PS_MIO44_501_SD0_DATA2
PS_MIO45_501_SD0_DATA3
PS-SRST#
PS_MIO16_501_ETH0_TX_CLK
PS_MIO19_501_ETH0_TX_D2
PS_MIO18_501_ETH0_TX_D1
PS_MIO20_501_ETH0_TX_D3
PS_MIO21_501_ETH0_TX_CTL
PS_MIO22_501_ETH0_RX_CLK
PS_MIO23_501_ETH0_RX_D0
PS_MIO24_501_ETH0_RX_D1
PS_MIO25_501_ETH0_RX_D2
PS_MIO26_501_ETH0_RX_D3
PS_MIO27_501_ETH0_RX_CTL
PS_MIO36_501_USB0_CLK
PHY1_LED_0
PS_MIO18_501_ETH0_TX_D1
PS_MIO09_500_USB_CLK_PD
PS_MIO38_501_USB0_D6
PS_MIO37_501_USB0_D5
VCCPCOM-1P8V
PHY1_DVDD_1V0 PHY1_AVDD_3V3
PHY1_DVDD_1V0
PS_MIO53_501_ETH0_MDIO
PS_MIO52_501_ETH0_MDC
2
E11E14D10
F14
D11
F15
D13
C13
E16
D15
F12
E13
D14
E12
F13
D16
B12
B13
C10
B10A19
B18A17
B17
A16
A15
C16
C15
A14
A12A11A10
C18
C17
A9
B15
B14
C12
B9
C11
A13
B16
D12
E15
31
42
4
1 3
2
2
1
3
2
1
3
1
32
1
3
2
1
3
3334
10
52 49
11
55 54 51 5056 53
29
45
12
48 47 45 44 4346
30
16
41
3736
PAD
18 22 24 28
8
17 21 23 27
7
121314
3231
40
42
6
15
935
2520
3938
2619
3
21
21
21
52
6
43
1
25
3220 3028
2221
29
1615
27
14118
26
24
2
12
23
PAD
1819
31
1310976543
17
1
PINSPARE
GND
PINSPARE
PINSPARE
PINSPARE
GND
GND GND
PAD
TX_C
TRL
TXD(
3)TX
D(2)
TX_C
LKVD
DOTX
D(1)
TXD(
0)VD
DORX
D(3)
RXD(
2)RX
_CLK
RXD(
1)RX
D(0)
RX_C
TRL
DVDDREGCAP2
DVDD_OUTAVDD18_OUT
AVDD18REGCAP1
REG_INAVDDC18XTAL_IN
XTAL_OUTHSDACPHSDACN
RSETTSTPT
MDI
P(0)
MDI
N(0)
AVDD
18AV
DD33
MDI
P(1)
MDI
N(1)
MDI
P(2)
MDI
N(2)
AVDD
33AV
DD18
MDI
P(3)
MDI
N(3)
RESE
TNCO
NFIG
LED(0)LED(1)LED(2)/INTNVDDOVDDO_SELCLK125MDIOMDCDVDDS_OUTNS_OUTPAVDD18S_INNS_INP
GND
GND
GND
GND
GND
PINSPARE
PINSPARE
GND_FLAG
VDDI
O
DIR
VDD1
8
STP
VDD1
8
RESETB
REFCLK
XO
RBIAS
IDVBUSVBAT
VDD3
3
DMDP
CPEN
SPK_RSPK_L
REFSEL2
DATA7
N/C
REFSEL1
DATA6DATA5
REFSEL0
DATA4DATA3DATA2DATA1DATA0
NXT
CLKOUT
PINSPARE
PINSPARE
PINSPARE
PINSPARE
GND
GND
GND
VCCO
_MIO
1_50
1VC
CO_M
IO1_
501
VCCO
_MIO
1_50
1VC
CO_M
IO1_
501
PS_MIO53_501
PS_MIO51_501
PS_MIO49_501
PS_MIO47_501
PS_MIO45_501
PS_MIO43_501
PS_MIO41_501
PS_MIO39_501
PS_MIO37_501PS_MIO36_501
PS_MIO34_501
PS_MIO32_501
PS_MIO30_501
PS_MIO28_501
PS_MIO26_501
PS_MIO24_501
PS_MIO22_501
PS_MIO20_501PS_MIO18_501
PS_MIO16_501PS_SRST_B_501
PS_MIO52_501
PS_MIO50_501
PS_MIO48_501
PS_MIO46_501
PS_MIO44_501
PS_MIO42_501
PS_MIO40_501
PS_MIO38_501
PS_MIO35_501
PS_MIO33_501
PS_MIO31_501
PS_MIO29_501
PS_MIO27_501
PS_MIO25_501
PS_MIO23_501
PS_MIO21_501
PS_MIO19_501PS_MIO17_501
PS_MIO_VREF_501
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDSTANDBY
GNDOUTPUT
GND
G
S
D
GND
G
S
D
GND
GND
G
S
D
G
S
D
GND
PINSPARE
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
QSPI FLASH
BANK_500
DAT2
CD/DAT3
CMD
VDD
DAT1
DAT0
VSS
SD CARD
NAND (NA)
BOOT MODE
CASCADED JTAG
QSPI
S4(MIO5)
1
1
0
0
S3(MIO4)
1
0
1
0
MODULE (DAUGHTER BD)
QSPI & MICROSD
CLK
MIO
3 10
<DESIGN_VIEW>
: PowerProduct(s): AD9364HW TYPE : Customer Evaluation Z
1:1
D202_041351
Neil L Wilson
XC7Z020-1CLG400I
39
240
10KDNI
10K
0.1UF
0
20K20K
20K
20K 20K
0.1UF
0.1UF
0.1UF
20K20K
20K
4.99K0.1UF
0.1UF
4.99K0.1UF
TXS02612RTWR
N25Q256A11E1240
CAS-120TB
CAS-120TB
DM3CS-SF
CAS-120TB
7914J-1-000E
R0603
33.333MEGHZ
0.1UF
R41
R40
C39
R19
R31R32
R36
R120 R119
C40
C55
C41
R122R121
R116
R109 C57
C54
R4 C42
C34
Y1
R114
U1
U13R28
J3
S4
S3
S1
U11
SW1
VCCPCOM-1P8V
PS_MIO01_500_QSPI0_SS_B
VCCPCOM-1P8V
PS-SRST#
PS_MIO06_500_QSPI0_SCLKPS_MIO01_500_QSPI0_SS_B
PS_MIO09_500_USB_CLK_PD
PS_MIO11_500_JX4
PS_MIO13_500_JX4
PS_MIO15_500_JX4
VCCPCOM-1P8V
PS_MIO08_500_ETH0_RESETNPS_MIO07_500_USB_RESET_BPS_MIO06_500_QSPI0_SCLKPS_MIO05_500_QSPI0_IO3
VCCPCOM-1P8VVCCPCOM-1P8V
PS_MIO02_500_QSPI0_IO0PS_MIO03_500_QSPI0_IO1PS_MIO04_500_QSPI0_IO2
PS_MIO43_501_SD0_DATA1PS_MIO44_501_SD0_DATA2PS_MIO45_501_SD0_DATA3
PS_MIO41_501_SD0_CMD
PS_MIO00_500_JX4
SDIO_CLKB0
SDIO_CMDB0SDIO_DAT3B0
SDIO_CMDB1SDIO_CLKB0SDIO_CLKB1
PS_MIO10_500_JX4
PS_MIO12_500_JX4
PS_MIO14_500_JX4
PWR_GD_1.35V
J3-9SDIO_DAT1B0SDIO_DAT0B0
SDIO_DAT2B0VCC-3P3V-IO
SD_SEL
SDIO_DAT3B1SDIO_DAT3B0SDIO_DAT2B1SDIO_DAT2B0SDIO_DAT1B1SDIO_DAT1B0SDIO_DAT0B1SDIO_DAT0B0
PS_MIO40_501_SD0_CLK
VCCPCOM-1P8V VCC-3P3V-IO
VCC-3P3V-IO
VCCPCOM-1P8V
SDIO_CMDB0
PS_MIO02_500_QSPI0_IO0PS_MIO03_500_QSPI0_IO1
PS_MIO05_500_QSPI0_IO3PS_MIO04_500_QSPI0_IO2
VCCPCOM-1P8V
VCC-3P3V-IO
PS_MIO42_501_SD0_DATA0
VCCPCOM-1P8V
D2
3
2
1
4
E7C7C8C5E8D9C6E9B5
D5D8A5A6B7D6B8A7E6
B6 D7
C4
B3
B4
C2A4
E5E4E3E2E1D5D1C5C3C1B5B1A5A3A2
D4
D3B2
987654321
GND4GND3GND2GND1
13 2
13 2
13 2
17215
24
PAD112
1022
3 8231 1516714186
12204
13199
2B2A
1B1A
VCCB1VCCB0VCCA
CLKB1CLKB0
CMDB1CMDB0
DAT3B1DAT3B0DAT2B1DAT2B0DAT1B1DAT1B0DAT0B1DAT0B0
PADGNDGNDSEL
CLKA
CMDA
DAT3A
DAT2A
DAT1A
DAT0A
GND
GND
VDDSTANDBY
GNDOUTPUT
GND
GND
VCCO
_MIO
0_50
0VC
CO_M
IO0_
500
PS_MIO0_500PS_MIO1_500PS_MIO2_500PS_MIO3_500PS_MIO4_500PS_MIO5_500PS_MIO6_500PS_MIO7_500PS_MIO8_500
PS_MIO9_500PS_MIO10_500PS_MIO11_500PS_MIO12_500PS_MIO13_500PS_MIO14_500PS_MIO15_500PS_POR_B_500PS_CLK_500
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
RESET/NC
CDQ0
VSS
W#/VPP/DQ2DQ1
S#
VCC
HOLD#/DQ3
GND
GND
GND
GND
GNDGND
GND
GNDGND
GND
GNDGND
GND
GND
GND
PINSGND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
MODULE (DAUGHTER BD)
4 10
<DESIGN_VIEW>
: PowerProduct(s): AD9364HW TYPE : Customer Evaluation Z
1:1
D202_041351
Neil L Wilson
10K
1K
10K
3PIN_SOLDER_JUMPER
3PIN_SOLDER_JUMPER 3PIN_SOLDER_JUMPER
3PIN_SOLDER_JUMPER
61082-101400LF
61082-101400LF
61082-101400LF
61082-101400LF 61082-101400LF61082-101400LF
61082-101400LF61082-101400LF
R43
R53
R56
JP4
JP3
JP2
JP1
JX4 JX4
JX4 JX4
JX3 JX3
JX3 JX3
JX2 JX2
JX2 JX2
JX1 JX1
JX1JX1
3.3VJX_VIN
JX_VCCO_34
S_IN_N
ETH_MD3_N
S_IN_P
ETH_MD3_P
IO_L16_13_JX2_N
ETH_MD2_P
S_OUT_P
S_OUT_N
ETH_MD4_N
ETH_MD4_P
IO_L13_MRCC_34_JX4_N
IO_L13_MRCC_34_JX4_P
ETH_MD2_N
USB_OTG_CPEN
USB_VBUS_OTG
ETH_PHY_LED1
IO_L15_34_JX4_N
IO_L15_34_JX4_P
ETH_PHY_LED0
JX_VCCO_13
INIT_B_0_JX2_09
IO_L11_SRCC_13_JX2_N
JX_VIN
FPGA_DONE
IO_L11_SRCC_13_JX2_P
IO_L13_MRCC_13_JX2_N
PG_MODULE
IO_L05_34_JX4_P
IO_L05_34_JX4_N
IO_L03_34_JX4_N
DX_0_P
JX_VIN
JTAG_TMS
DX_0_N
JX_VIN
JTAG_TCK
JTAG_TDO
FPGA_VBATT
JX_VCCO_34
IO_L19_13_JX2_N
IO_L21_13_JX2_N
IO_L21_13_JX2_P
IO_L17_13_JX2_N
IO_L19_13_JX2_P
SDA
IO_L17_13_JX2_P
SCL
IO_L20_34_JX4_P
IO_L12_MRCC_34_JX4_P
IO_L14_SRCC_34_JX4_N
IO_L22_34_JX4_N
IO_L22_34_JX4_P
PS_MIO48_501_JX4
PS_MIO14_500_JX4 PS_MIO47_501_JX4
IO_L14_SRCC_34_JX4_P
IO_L10_34_JX4_P
IO_L08_34_JX4_N
GPO3
IO_L18_34_JX4_N
IO_25_34_JX4
IO_L16_34_JX4_N
IO_L08_34_JX4_P
IO_L17_34_JX4_N
PS_MIO12_500_JX4
PS_MIO46_501_JX4PS_MIO13_500_JX4
IO_L19_34_JX4_N
IO_L21_34_JX4_P
IO_L16_34_JX4_P
IO_L04_34_JX4_N
IO_L12_MRCC_34_JX4_NIO_L11_SRCC_34_JX4_N
IO_L06_34_JX4_N
IO_L18_34_JX4_P
SDIO_CMDB1
JX_VCCO_13
IO_L10_34_JX4_N
IO_L06_34_JX4_P
PS_MIO00_500_JX4 PS_MIO49_501_JX4
PS_MIO51_501_JX4
IO_L14_SRCC_13_JX2_N
IO_L14_SRCC_13_JX2_P
SDIO_DAT2B1
V_0_P
SDIO_CLKB1
IO_L12_MRCC_13_JX2_N
JX3_SD1_CDN
SDIO_DAT3B1
PS_MIO15_500_JX4
GPO0
GPO2
VDDA_GPO_PWR
AUXADC
IO_L09_34_JX4_P
IO_L07_34_JX4_P
IO_L21_34_JX4_N
IO_L20_34_JX4_N
PS_MIO11_500_JX4
AUXDAC1
GPO1
AUXDAC2
IO_L02_34_JX4_P
IO_L02_34_JX4_N
IO_L04_34_JX4_PIO_L03_34_JX4_P
IO_L01_34_JX4_N
IO_L01_34_JX4_P
IO_L09_34_JX4_N
AD9364_CLK
SDIO_DAT1B1
IO_L13_MRCC_13_JX2_P
IO_L15_13_JX2_P
IO_L20_13_JX2_N
IO_L20_13_JX2_P
IO_L18_13_JX2_N
IO_L12_MRCC_13_JX2_P
JX_VIN
PG_1P8V
PS_MIO10_500_JX4
IO_L19_34_JX4_P
IO_L17_34_JX4_P
IO_L11_SRCC_34_JX4_P
IO_L07_34_JX4_NSDIO_DAT0B1
JX_VCCO_13
V_0_N
IO_L06_13_JX2_P
IO_L15_13_JX2_N
IO_L16_13_JX2_P
IO_L18_13_JX2_P
JX_VIN
ETH_MD1_P
ETH_MD1_N
USB_ID
USB_OTG_P
USB_OTG_N
PWR_ENABLE CARRIER_RESET
JTAG_TDI
23
1
23
1
23
1
23
1
99979593918987858381797775737169676563615957555351
100989694929088868482807876747270686664626058565452
494745434139373533312927252321191715131197531
5048464442403836343230282624222018161412108642
99979593918987858381797775737169676563615957555351
100989694929088868482807876747270686664626058565452
494745434139373533312927252321191715131197531
5048464442403836343230282624222018161412108642
99979593918987858381797775737169676563615957555351
100989694929088868482807876747270686664626058565452
494745434139373533312927252321191715131197531
5048464442403836343230282624222018161412108642
99979593918987858381797775737169676563615957555351
100989694929088868482807876747270686664626058565452
5048464442403836343230282624222018161412108642
494745434139373533312927252321191715131197531
GNDGNDGND
BCOMA
BCOMA
BCOM
A
BCOM
A
GND
GNDGNDGND GNDGND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
MODULE (DAUGHTER BD)
VTTREF
DDR3
PLACE NEAR DDR #2
S0
STATE S3
HI
S5
HI ON ON
VTT
PLACE NEAR DDR3 #1
BANK_502
5 10
<DESIGN_VIEW>
: PowerProduct(s): AD9364HW TYPE : Customer Evaluation Z
1:1
D202_041351
Neil L Wilson
10UF
MT41K256M16TW-107 IT:P
MT41K256M16TW-107 IT:P
10UF
0.01UF
4.7UF0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10K
10K
1K
0.01UF 0.01UF
0.01UF0.01UF
0.015UF
0.47UF0.47UF 0.47UF0.47UF4.7UF100UF 4.7UF 4.7UF
0.01UF
0.01UF
0.01UF
4.7UF
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
XC7Z020-1CLG400I
240
240
10UF
80.6
240
240
0.22UF
TPS51206DSQR
0
0
U3
C83
C122
C120C91 C92 C94 C95 C96 C97 C109 C112 C115 C116 C117 C118
R222
R221
R133
C77 C76
C123C103
C80
C89C88 C108C107C86C100 C87 C106
C102
C84
C43
C101
R134
R135
U1
R142
R166
U2
R161
U14
R165
C81
C79
C82
R6
R163
R160R162
R156R159
R154R155
R152R153
R150R151
R148R149
R146R147
R144R145
R141R143
R139R140
R137R138
R136
DDR3_BA1
DDR3_BA2
DDR3_BA1
DDR3_BA0
DDR3_A6
DDR3_A3
DDR3_A0
DDR3_DM2
DDR3_DM3
VCC-1P35
DDR3_A8
DDR3_A14
DDR3_A13
DDR3_RST#
DDR3_A11
DDR3_A9
DDR3_A7
DDR3_A4
DDR3_A1
DDR3_A2
DDR3_A5
DDR3_A12
DDR3_BA0
DDR3_A10
DDR3_WE#
DDR3_CS#
DDR3_CKE
DDR3_CK_N
DDR3_CAS#
DDR3_ODT
DDR3_CK_P
DDR3_RAS#
DDR3_DQ21
DDR3_DQ23
DDR3_DQ20
DDR3_DQS2_N
DDR3_DQ22
DDR3_DQ19
DDR3_DQ17
DDR3_DQS2_P
DDR3_DQ18
DDR3_DQ16
DDR3_DQ24
DDR3_DQ26
DDR3_DQS3_P
DDR3_DQ25
DDR3_DQ27
DDR3_DQ30
DDR3_DQS3_N
DDR3_DQ28
DDR3_DQ31
DDR3_DQ29
DDR3_DQS1_N
DDR3_DM3
DDR3_DM2
DDR3_BA2
DDR3_WE#
DDR3_A6
DDR3_A3
DDR3_A4
DDR3_A1
DDR3_A13
DDR3_A14
DDR3_A11
DDR3_A12
DDR3_A9
DDR3_A10
DDR3_A7
DDR3_A8
DDR3_A5
DDR3_A2
DDR3_A0
DDR3_CS#
DDR3_CKE
DDR3_ODT
DDR3_RAS#
DDR3_CAS#
DDR3_A12
VCC-1P35VCC-1P35
DDR3_A5
DDR3_A3
VCCPCOM-1P8V
DDR3_CAS#
DDR3_DQS0_N
DDR3_A0
DDR3_WE#
DDR3_DQ9
DDR3_A8
DDR3_DQ31
DDR3_DQ30
DDR3_DQ29
DDR3_DQ28
DDR3_DQS3_N
DDR3_DQS3_P
DDR3_DQ27
DDR3_DQ26
DDR3_DQ25
DDR3_DQ24
DDR3_DQ23
DDR3_DQ22
DDR3_DQ21
DDR3_DQ20
DDR3_DQS2_N
DDR3_DQS2_P
DDR3_DQ19
DDR3_DQ18
DDR3_DQ17
DDR3_DQ16
DDR3_RAS#
DDR3_CKE
DDR3_CS#
DDR3_ODT
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_A0
DDR3_A1
DDR3_A2
DDR3_CK_N
DDR3_CK_P
DDR3_A4
DDR3_A6
DDR3_A7
DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A13
DDR3_A14
DDR3_DQ15
DDR3_DQ14
DDR3_DQ13
DDR3_DQ12
DDR3_DQS1_P
DDR3_DM1
DDR3_DQ11
DDR3_DQ10
DDR3_DQ8
DDR3_DQ7
DDR3_DQ6
DDR3_DQ5
DDR3_DQ4
DDR3_DQS0_P
DDR3_DM0
DDR3_DQ3
DDR3_DQ2
DDR3_DQ1
DDR3_DQ0
DDR3_RST#
DDR3_A8
DDR3_A14
DDR3_A13
DDR3_RST#
DDR3_A6
DDR3_A11
DDR3_A9
DDR3_A7
DDR3_A4
DDR3_A1
DDR3_A2
DDR3_A5
DDR3_BA1
DDR3_A12
DDR3_A3
DDR3_BA2
DDR3_BA0
DDR3_A10
DDR3_WE#
DDR3_CS#
DDR3_CKE
DDR3_CK_N
DDR3_CAS#
DDR3_ODT
DDR3_CK_P
DDR3_RAS#
DDR3_DQ5
DDR3_DQ7
DDR3_DQ4
DDR3_DQS0_N
DDR3_DQ6
DDR3_DQ3
DDR3_DQ1
DDR3_DQS0_P
DDR3_DQ2
DDR3_DM0
DDR3_DQ0
DDR3_DQ8
DDR3_DM1
DDR3_DQ10
DDR3_DQS1_P
DDR3_DQ9
DDR3_DQ11
DDR3_DQ14
DDR3_DQS1_N
DDR3_DQ12
DDR3_DQ15
DDR3_DQ13
VCCO-DDR
VCC-1P35
VTT_0P75
VTT_0P75
VCC-3P3V
DDR3_CK_P
DDR3_CK_N
VTT_0P75
VCC-1P35 VTTVREF
VTTVREF
VTTVREF VTTVREF
VCC-3P3V
VCC-1P35
VTTVREF
D7
T7
A1
A2
A3
A7
A8
A9B1
B2
B3
B7
B8
B9C1
C2
C3
C7
C8
C9D1
D2
D3
D8
D9
E1E2
E3
E7
E8
E9 F1
F2
F3
F7
F8
F9 G1
G2
G3
G7
G8
G9
H1H2
H3
H7
H8
H9
J1 J2
J3
J7
J8J9
K1
K2
K3
K7
K8
K9
L1
L2
L3
L7
L8
L9 M1
M2
M3
M7
M8
M9
N1
N2
N3
N7
N8
N9
P1
P2
P3P7
P8
P9
R1
R2
R3
R7
R8
R9
T1
T2
T3
T8
T9
A1
A2
A3
A7
A8
A9B1
B2
B3
B7
B8
B9C1
C2
C3
C7
C8
C9D1
D2
D3
D7
D8
D9
E1E2
E3
E7
E8
E9 F1
F2
F3
F7
F8
F9 G1
G2
G3
G7
G8
G9
H1H2
H3
H7
H8
H9
J1 J2
J3
J7
J8J9
K1
K2
K3
K7
K8
K9
L1
L2
L3
L7
L8
L9 M1
M2
M3
M7
M8
M9
N1
N2
N3
N7
N8
N9
P1
P2
P3P7
P8
P9
R1
R2
R3
R7
R8
R9
T1
T2
T3T7
T8
T9
B4
C3B3A2A4
A1
C2B2
D3D1C1E1E2E3
G3H3
F1
G2F2
J3H2H1J1
F4D4E4G4F5J4K1K4L4L1M4K3
G5H5L2M2
M3K2N2
J5R4L5
N5N1N3M5P5P4
P1P3R3R1
T1
R2T2
T4U4U2U3V1Y3W1Y4
Y1
W5W4
Y2W3V2V3
G1
H4 L3 P2 R5 U1 V4
H6P6
E5D2A3
5
6
3
2
1
10
97
4
PAD8
GNDGNDGND GND
VCCO
_DDR
_502
VCCO
_DDR
_502
VCCO
_DDR
_502
PS_DDR_VREF1_502PS_DDR_VREF0_502
VCCO
_DDR
_502
VCCO
_DDR
_502
VCCO
_DDR
_502
VCCO
_DDR
_502
VCCO
_DDR
_502
VCCO
_DDR
_502
VCCO
_DDR
_502
PS_DDR_DQ31_502PS_DDR_DQ30_502PS_DDR_DQ29_502PS_DDR_DQ28_502
PS_DDR_DQS_N3_502PS_DDR_DQS_P3_502
PS_DDR_DM3_502
PS_DDR_DQ27_502PS_DDR_DQ26_502PS_DDR_DQ25_502PS_DDR_DQ24_502PS_DDR_DQ23_502PS_DDR_DQ22_502PS_DDR_DQ21_502PS_DDR_DQ20_502
PS_DDR_DQS_N2_502PS_DDR_DQS_P2_502
PS_DDR_DM2_502
PS_DDR_DQ19_502PS_DDR_DQ18_502PS_DDR_DQ17_502PS_DDR_DQ16_502
PS_DDR_RAS_B_502PS_DDR_CAS_B_502PS_DDR_WE_B_502
PS_DDR_CKE_502PS_DDR_CS_B_502PS_DDR_ODT_502
PS_DDR_BA0_502PS_DDR_BA1_502PS_DDR_BA2_502
PS_DDR_A0_502PS_DDR_A1_502PS_DDR_A2_502
PS_DDR_CKN_502PS_DDR_CKP_502PS_DDR_VRP_502PS_DDR_VRN_502
PS_DDR_A3_502PS_DDR_A4_502PS_DDR_A5_502PS_DDR_A6_502PS_DDR_A7_502PS_DDR_A8_502PS_DDR_A9_502
PS_DDR_A10_502PS_DDR_A11_502PS_DDR_A12_502PS_DDR_A13_502PS_DDR_A14_502
PS_DDR_DQ15_502PS_DDR_DQ14_502PS_DDR_DQ13_502PS_DDR_DQ12_502
PS_DDR_DQS_N1_502PS_DDR_DQS_P1_502
PS_DDR_DM1_502
PS_DDR_DQ11_502PS_DDR_DQ10_502
PS_DDR_DQ9_502PS_DDR_DQ8_502PS_DDR_DQ7_502PS_DDR_DQ6_502PS_DDR_DQ5_502PS_DDR_DQ4_502
PS_DDR_DQS_N0_502PS_DDR_DQS_P0_502
PS_DDR_DM0_502
PS_DDR_DQ3_502PS_DDR_DQ2_502PS_DDR_DQ1_502PS_DDR_DQ0_502
PS_DDR_DRST_B_502GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND GND
GND
GNDGND
PIN
SP
AR
E
PIN
SP
AR
E
PIN
SP
AR
E
PIN
SP
AR
E
PIN
SP
AR
E
VSS
A8
A14A13
RESET#
VSS
VDD
A6
A11
A9
A7
VDD
VSS
A4
A1A2
A5
VSS
VDD
BA1
A12/BC#
A0
A3
VDD
VSS
VREF
CA
NC
BA2
BA0
VSS
NC
ZQ
A10/AP
WE#
CS#
NC
CKE
VDD
CK#
CAS#
VDD
ODT
NC VSS
CK
RAS#
VSS
NC
VDDQ
DQ5
DQ7
DQ4
VDDQ
VREF
DQ
VSSQ
VSS
VDD
LDQS#
DQ6
VSSQ
VSSQ
DQ3
DQ1
LDQS
DQ2
VDDQ
VDDQ
VSSQ
LDM
DQ0
VSSQ
VSS
VDD
VSSQ
DQ8
UDM
VDDQ
VSSQ
VDDQ
DQ10
UDQS
DQ9
DQ11
VDDQ
VSSQ
DQ14
UDQS#
VSS
VDD
VSSQ
VSS
VDDQ
DQ12
DQ15
DQ13
VDDQ
PIN
SP
AR
E
PIN
SP
AR
E
PIN
SP
AR
E
PIN
SP
AR
E
PIN
SP
AR
E
VSS
A8
A14A13
RESET#
VSS
VDD
A6
A11
A9
A7
VDD
VSS
A4
A1A2
A5
VSS
VDD
BA1
A12/BC#
A0
A3
VDD
VSS
VREF
CA
NC
BA2
BA0
VSS
NC
ZQ
A10/AP
WE#
CS#
NC
CKE
VDD
CK#
CAS#
VDD
ODT
NC VSS
CK
RAS#
VSS
NC
VDDQ
DQ5
DQ7
DQ4
VDDQ
VREF
DQ
VSSQ
VSS
VDD
LDQS#
DQ6
VSSQ
VSSQ
DQ3
DQ1
LDQS
DQ2
VDDQ
VDDQ
VSSQ
LDM
DQ0
VSSQ
VSS
VDD
VSSQ
DQ8
UDM
VDDQ
VSSQ
VDDQ
DQ10
UDQS
DQ9
DQ11
VDDQ
VSSQ
DQ14
UDQS#
VSS
VDD
VSSQ
VSS
VDDQ
DQ12
DQ15
DQ13
VDDQ
PAD
VDD
S5
GND
S3 VTTREF
VTTSNS
PGND
VTT
VLDO
IN
VDDQSNS
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PLACE NEAR XC7Z020 (VCCO-DDR)
VCCAUX & VCCPAUX
BANK_0
PLACE NEAR XC7020PLACE NEAR XC7Z020 (VCCPINT)
MODULE (DAUGHTER BD)
GND/VCC
XILINX
PLACE NEAR XC7Z020 (VCC-BRAM)
ZYNQ
PLACE NEAR XC7Z020 (VCCO-35 BANK)PLACE NEAR XC7Z020 (VCCO-34 BANK)
PLACE NEAR XC7Z020 (VCCO-13 BANK)PLACE NEAR XC7Z020 (VCCINT-0P95V)
6 10
<DESIGN_VIEW>
: PowerProduct(s): AD9364HW TYPE : Customer Evaluation Z
1:1
D202_041351
Neil L Wilson
100UF100UF
22UF
22UF
22UF22UF100UF
4.7UF4.7UF 0.47UF 0.47UF 0.47UF 0.47UF
4.7UF 4.7UF 0.47UF 0.47UF
0.47UF0.47UF0.47UF
0.47UF4.7UF100UF0.47UF0.47UF
0.47UF
100UF100UF 4.7UF 4.7UF 0.47UF 0.47UF 0.47UF 0.47UF
100UF 0.47UF0.47UF
0.47UF
0.47UF 0.47UF4.7UF
4.7K
4.7K
130
4.7K
47UF
0.1UF0.47UF
4.7UF
0.47UF4.7UF100UF
0.47UF100UF 4.7UF 0.47UF
4.7UF
0.47UF0.47UF4.7UF4.7UF
0
220OHM
220OHM
XC7Z020-1CLG400I
QTLP600C4TR
XC7Z020-1CLG400I
600OHMS
C151C1
C71
C30
C145C24C29
C140 C141 C143 C16 C19 C23
C175 C52 C53 C179
C20C17C11
C72C70C56C51C47
C178
C28C2 C3 C4 C7 C15 C18 C22
C27 C48C46
C10
C170 C171C169
R169
R168
R172
R167
C251
C190C189
C167
C125C121C138
C163C173 C159 C162
C174
C44C35C33C31
D4
U1
U1
E12
E1
R9
L12
JTAG_TCKJTAG_TMS
VCC-3P3V-IO
INIT_B_0_JX2_09
VCC-3P3V-IO
VCCINT-1P0V JX_VCCO_13
VDD_INTERFACEVCC-BRAM
VCCINT-1P0V
VCCPCOM-1P8V
VCCPINT-1P0V
VCCPCOM-1P8VVCC-BRAM
VCCINT-1P0V
FPGA_DONE
VCCPCOM-1P8V
VCCPCOM-1P8V
VCCO-DDR
JX_VCCO_34
V_0_PV_0_N
JTAG_TDI JTAG_TDO
VCCPINT-1P0V
DX_0_NDX_0_P
VCCPCOM-1P8V
VCC-3P3V-IO
FPGA_VBATT
A8A18B1
B11C4
C14K11D17E10E20
F3F7
G10G12G16
H7H9
H11H13H19
J2J8
J12 K5 K7 C9 K13
K15 L8 L12
L18
M1
M7
M11
M13 N4 N8 N10
N12
N14 P7 P9 P11
P13
P17R8R12R20T3T7T13U6U16V9V19W2W12Y5Y15G13H12J13K12L13M12N13
P12
R13
J11
L11
N9P10
R9N11
G11
H10
G8
G9
F8H8K8M8
G7
J7L7N7P8R7
R11
M9
J10
J9
L9L10
F11
F9
M10
K10
K9
F10
N6R6
R10
G6 F6
T6
M6
L6
J6
K6
A
C
21
21
GND
GND
GND
GND
VCCP
INT
VCCP
INT
VCCP
INT
VCCP
INT
VCCP
INT
VCCP
INT
VCCP
AUX
VCCP
AUX
VCCP
AUX
VCCP
AUX
VCCP
AUX
VCCP
LVC
CBRA
MVC
CBRA
MVC
CAUX
VCCA
UXVC
CAUX
VCCA
UXVC
CAUX
VCCA
UXVC
CINT
VCCI
NT
VCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINT
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
VCCO
_0
TMS_0
PROGRAM_B_0
CFGBVS_0
RSVD
VCC1
TDO_0TDI_0
INIT_B_0
RSVD
VCC2
RSVD
VCC3
RSVD
GND
VP_0
VREFN_0
DXN_0
TCK_0
VCCB
ATT_
0
VN_0VREFP_0
VCCA
DC_0
GND
ADC_
0
DXP_0
DONE_0
GND
GND
GND
GNDGND
GND
GNDGND
GNDGND
GND
GNDGND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
HR
HRBANK_13
XILINX
BANK_35 BANK_34
HR
MODULE (DAUGHTER BD)
7 10
<DESIGN_VIEW>
: PowerProduct(s): AD9364HW TYPE : Customer Evaluation Z
1:1
D202_041351
Neil L Wilson
XC7Z020-1CLG400I
XC7Z020-1CLG400I
XC7Z020-1CLG400I
U1
U1
U1
IO_L10_35_ENABLE
IO_L11_35_EN_AGC
IO_L10_35_SYNC_IN
IO_L11_35_TXNRX
IO_L08_35_FB_CLK_N
IO_L09_35_TX_FRAME_P
IO_L09_35_TX_FRAME_N
IO_L12_MRCC_35_DATA_CLK_P
IO_L12_MRCC_35_DATA_CLK_N
IO_L07_35_RX_FRAME_N
IO_L07_35_RX_FRAME_PIO_L07_34_JX4_P
IO_L06_34_JX4_N
IO_L15_35_TX_D2_N
IO_L15_35_TX_D2_P
IO_L14_35_TX_D1_NIO_L14_35_TX_D1_P
IO_L04_35_RX_D3_N
IO_L04_35_RX_D3_P
IO_L03_35_RX_D2_N
IO_L03_35_RX_D2_P
IO_L08_35_FB_CLK_P
IO_L06_35_RX_D5_N
IO_L06_35_RX_D5_P
IO_L02_35_RX_D1_N
IO_L02_35_RX_D1_P
IO_L01_35_RX_D0_P
IO_L13_35_TX_D0_P
IO_00_34_AD9364_CLKSEL
IO_L01_34_JX4_N
IO_L05_35_RX_D4_P
VDD_INTERFACE
IO_L17_13_JX2_P
IO_L17_13_JX2_N
IO_L18_13_JX2_P
IO_L18_13_JX2_N
IO_L19_13_JX2_P
SCL
SDA
IO_L21_13_JX2_N
IO_L21_13_JX2_P
IO_L20_13_JX2_N
IO_L20_13_JX2_P
IO_L19_13_JX2_N
IO_L16_13_JX2_N
IO_L16_13_JX2_P
IO_L15_13_JX2_N
IO_L15_13_JX2_P
IO_L14_SRCC_13_JX2_N
IO_L14_SRCC_13_JX2_P
IO_L13_MRCC_13_JX2_N
IO_L13_MRCC_13_JX2_P
IO_L12_MRCC_13_JX2_N
IO_L12_MRCC_13_JX2_P
IO_L11_SRCC_13_JX2_N
IO_L11_SRCC_13_JX2_P
IO_L06_13_JX2_P
IO_25_34_JX4
IO_L24_34_CTRL_IN3
IO_L24_34_CTRL_IN2
IO_L23_34_CTRL_IN1
IO_L23_34_CTRL_IN0
IO_L22_34_JX4_N
IO_L22_34_JX4_P
IO_L21_34_JX4_N
IO_L21_34_JX4_P
IO_L20_34_JX4_N
IO_L20_34_JX4_P
IO_L19_34_JX4_N
IO_L19_34_JX4_P
IO_L18_34_JX4_N
IO_L18_34_JX4_P
IO_L17_34_JX4_N
IO_L17_34_JX4_P
IO_L16_34_JX4_N
IO_L16_34_JX4_P
IO_L15_34_JX4_N
IO_L15_34_JX4_P
IO_L14_SRCC_34_JX4_N
IO_L14_SRCC_34_JX4_P
IO_L13_MRCC_34_JX4_N
IO_L13_MRCC_34_JX4_PIO_L12_MRCC_34_JX4_N
IO_L12_MRCC_34_JX4_P
IO_L11_SRCC_34_JX4_N
IO_L11_SRCC_34_JX4_P
IO_L10_34_JX4_N
IO_L10_34_JX4_P
IO_L09_34_JX4_N
IO_L09_34_JX4_P
IO_L08_34_JX4_N
IO_L08_34_JX4_P
IO_L07_34_JX4_N
IO_L06_34_JX4_P
IO_L05_34_JX4_N
IO_L05_34_JX4_P
IO_L04_34_JX4_N
IO_L04_34_JX4_P
IO_L03_34_JX4_N
IO_L03_34_JX4_P
IO_L02_34_JX4_N
IO_L02_34_JX4_P
IO_L01_34_JX4_PIO_25_35_AD9364_CLKOUT
IO_L24_35_SPI_DO
IO_L24_35_SPI_DI
IO_L23_35_SPI_CLK
IO_L23_35_SPI_ENB
IO_L22_35_CTRL_OUT7
IO_L22_35_CTRL_OUT6
IO_L21_35_CTRL_OUT5
IO_L21_35_CTRL_OUT4
IO_L20_35_CTRL_OUT3
IO_L20_35_CTRL_OUT2
IO_L19_35_CTRL_OUT1
IO_L19_35_CTRL_OUT0
IO_L18_35_TX_D5_N
IO_L18_35_TX_D5_P
IO_L17_35_TX_D4_N
IO_L17_35_TX_D4_P
IO_L16_35_TX_D3_N
IO_L16_35_TX_D3_P
IO_L13_35_TX_D0_N
IO_L05_35_RX_D4_N
IO_L01_35_RX_D0_N
IO_00_35_AD9364_RST
JX_VCCO_34
JX_VCCO_13
A20E17D18
G19
J18
K19
L19M18M17M20M19F17F16
D20
R19T11T10T12U12U13V13V12W13T14T15P14R14Y16Y17W14Y14T16U17V15W15U14U15U18U19 N18
P19N20P20T20U20V20W20Y18Y19V16W16R16R17T17R18V17V18W18W19N17P18P15P16T19
N19
R15
T18
V14
W17
Y20
V5U7V7T9
U10Y7Y6Y9Y8V8W8
W10W9 U9
U8W11Y11T5U5Y12Y13V11V10V6W6
T8 U11
W7
Y10
G14C20B20B19
D19
E18E19
L20
J19L16L17K17K18 H16
H17
H18F19F20G17G18J20H20
G20H15G15K14J14N15N16L14L15M14M15K16J16J15
C19
F18
H14
J17
K20
M16
VCCO
_35
VCCO
_35
VCCO
_35
VCCO
_35
VCCO
_35
VCCO
_35
IO_25_35IO_L24N_T3_AD15N_35IO_L24P_T3_AD15P_35
IO_L23N_T3_35IO_L23P_T3_35
IO_L22N_T3_AD7N_35IO_L22P_T3_AD7P_35
IO_L21N_T3_DQS_AD14N_35IO_L21P_T3_DQS_AD14P_35
IO_L20N_T3_AD6N_35IO_L20P_T3_AD6P_35IO_L19N_T3_VREF_35
IO_L19P_T3_35IO_L18N_T2_AD13N_35IO_L18P_T2_AD13P_35IO_L17N_T2_AD5N_35IO_L17P_T2_AD5P_35
IO_L16N_T2_35IO_L16P_T2_35
IO_L15N_T2_DQS_AD12N_35IO_L15P_T2_DQS_AD12P_35IO_L14N_T2_AD4N_SRCC_35IO_L14P_T2_AD4P_SRCC_35
IO_L13N_T2_MRCC_35IO_L13P_T2_MRCC_35IO_L12N_T1_MRCC_35
IO_L12P_T1_MRCC_35IO_L11N_T1_SRCC_35IO_L11P_T1_SRCC_35IO_L10N_T1_AD11N_35IO_L10P_T1_AD11P_35IO_L9N_T1_DQS_AD3N_35IO_L9P_T1_DQS_AD3P_35IO_L8N_T1_AD10N_35IO_L8P_T1_AD10P_35IO_L7N_T1_AD2N_35IO_L7P_T1_AD2P_35IO_L6N_T0_VREF_35IO_L6P_T0_35IO_L5N_T0_AD9N_35IO_L5P_T0_AD9P_35IO_L4N_T0_35IO_L4P_T0_35IO_L3N_T0_DQS_AD1N_35IO_L3P_T0_DQS_AD1P_35IO_L2N_T0_AD8N_35IO_L2P_T0_AD8P_35IO_L1N_T0_AD0N_35IO_L1P_T0_AD0P_35IO_0_35
VCCO
_13
VCCO
_13
VCCO
_13
VCCO
_13
IO_L22N_T3_13IO_L22P_T3_13
IO_L21N_T3_DQS_13IO_L21P_T3_DQS_13
IO_L20N_T3_13IO_L20P_T3_13
IO_L19N_T3_VREF_13IO_L19P_T3_13IO_L18N_T2_13IO_L18P_T2_13IO_L17N_T2_13IO_L17P_T2_13IO_L16N_T2_13
IO_L16P_T2_13IO_L15N_T2_DQS_13IO_L15P_T2_DQS_13IO_L14N_T2_SRCC_13IO_L14P_T2_SRCC_13IO_L13N_T2_MRCC_13IO_L13P_T2_MRCC_13IO_L12N_T1_MRCC_13IO_L12P_T1_MRCC_13IO_L11N_T1_SRCC_13IO_L11P_T1_SRCC_13IO_L6N_T0_VREF_13
VCCO
_34
VCCO
_34
VCCO
_34
VCCO
_34
VCCO
_34
VCCO
_34
IO_25_34IO_L24N_T3_34IO_L24P_T3_34IO_L23N_T3_34IO_L23P_T3_34IO_L22N_T3_34IO_L22P_T3_34
IO_L21N_T3_DQS_34IO_L21P_T3_DQS_34
IO_L20N_T3_34IO_L20P_T3_34
IO_L19N_T3_VREF_34IO_L19P_T3_34IO_L18N_T2_34IO_L18P_T2_34IO_L17N_T2_34IO_L17P_T2_34IO_L16N_T2_34IO_L16P_T2_34
IO_L15N_T2_DQS_34IO_L15P_T2_DQS_34
IO_L14N_T2_SRCC_34IO_L14P_T2_SRCC_34IO_L13N_T2_MRCC_34IO_L13P_T2_MRCC_34IO_L12N_T1_MRCC_34
IO_L12P_T1_MRCC_34IO_L11N_T1_SRCC_34IO_L11P_T1_SRCC_34IO_L10N_T1_34IO_L10P_T1_34IO_L9N_T1_DQS_34IO_L9P_T1_DQS_34IO_L8N_T1_34IO_L8P_T1_34IO_L7N_T1_34IO_L7P_T1_34IO_L6N_T0_VREF_34IO_L6P_T0_34IO_L5N_T0_34IO_L5P_T0_34IO_L4N_T0_34IO_L4P_T0_34IO_L3N_T0_DQS_34IO_L3P_T0_DQS_PUDC_B_34IO_L2N_T0_34IO_L2P_T0_34IO_L1N_T0_34IO_L1P_T0_34IO_0_34
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
TX MONITOR INPUT
RX SMA CONNECTOR
1%
TX OUTPUT SMA CONNECTOR
MODULE (DAUGHTER BD)
8 10
<DESIGN_VIEW>
: PowerProduct(s): AD9364HW TYPE : Customer Evaluation Z
1:1
D202_041351
Neil L Wilson
0.001UF 10UF
1UF0.001UF
10K
1UF0.001UF
49.91K
0.1UF0.1UF
0.001UF
0.001UF 10UF
14.3K
TCM1-63AX+U.FL-R-SMT-1(01)
18PF
330NH
330NH
18PF
18PFU.FL-R-SMT-1(01) 18PF
LT15CCC2243A
U.FL-R-SMT-1(01)
10
1
TCM1-63AX+ U.FL-R-SMT-1(01)TCM1-63AX+
TCM1-63AX+
FXL4T245BQX
1
AD9364BBCZ
18PF
U.FL-R-SMT-1(01)18PF
330NH
330NH
18PF
18PF
C93 C98
C105C104
R111
C12C13
R101 R59
C246C245
C6
C14 C21
R125
T3
U17
R1
C8
C9
T1 T2C25
U22
RXA TXA
TXM
R123
R2
M1
TXBT4C99
C110
C90
RXB
W1
L8
L1 L2
L9C26
C85
TX_MON
RXB_N
IO_L11_35_EN_AGC
IO_L10_35_ENABLE
XTAL_N
IO_L23_35_SPI_ENB
IO_L24_35_SPI_DI
IO_L23_35_SPI_CLK
IO_00_35_AD9364_RST
IO_L08_35_FB_CLK_N
IO_L08_35_FB_CLK_P
TX_VCO_1P1V_SUPPLY
IO_L09_35_TX_FRAME_N
IO_L09_35_TX_FRAME_P
IO_L13_35_TX_D0_P
IO_L14_35_TX_D1_N
RXB_N
RXB_P
RXA_P
TX_MON
IO_L11_35_TXNRX
IO_L10_35_SYNC_IN
CTRL_IN2
CTRL_IN0
TXB_P
TXB_N
1P3_TX
TXA_P
TXA_N
IO_L21_35_CTRL_OUT5
IO_L21_35_CTRL_OUT4
IO_L19_35_CTRL_OUT1
IO_L19_35_CTRL_OUT0
IO_L12_MRCC_35_DATA_CLK_P
IO_L03_35_RX_D2_N
IO_L02_35_RX_D1_N
IO_L01_35_RX_D0_N
GPO0
GPO1
GPO2
GPO3
AUXDAC1
TXB_N
TXB_P
TXA_N
TXA_P
AUXDAC2
IO_L13_35_TX_D0_N
IO_L06_35_RX_D5_P
IO_L05_35_RX_D4_N
IO_L15_35_TX_D2_P
IO_L16_35_TX_D3_N
IO_L16_35_TX_D3_P
IO_L17_35_TX_D4_N
IO_L17_35_TX_D4_P
IO_L18_35_TX_D5_N
IO_L18_35_TX_D5_P
1P3_TX
RXA_N
RXA_P
RXB_P
IO_L24_35_SPI_DO
IO_L22_35_CTRL_OUT7
IO_L22_35_CTRL_OUT6
IO_25_35_AD9364_CLKOUT
IO_L12_MRCC_35_DATA_CLK_N
IO_L07_35_RX_FRAME_P
IO_L07_35_RX_FRAME_N
VDDA_TX_LOVDDA_TX_SYNTH
VDDA_RX_LOVDDA_RX_SYNTH
VDDA_RX_TX
VDDA_BBVDDD_DIG
TX_VCO_1P1V_SUPPLY
VDD_INTERFACERX_VCO_LDO_OUT
VDDA_GPO
VDD_INTERFACE
CTRL_IN0
CTRL_IN1
CTRL_IN2
CTRL_IN3 IO_L24_34_CTRL_IN3
IO_L24_34_CTRL_IN2
IO_L23_34_CTRL_IN1
IO_L23_34_CTRL_IN0
IO_L20_35_CTRL_OUT2
IO_L20_35_CTRL_OUT3
IO_L14_35_TX_D1_P
IO_L15_35_TX_D2_N
CTRL_IN3
CTRL_IN1
JX_VCCO_34
IO_L06_35_RX_D5_N
IO_L05_35_RX_D4_P
IO_L04_35_RX_D3_P
IO_L03_35_RX_D2_P
IO_L02_35_RX_D1_P
IO_L01_35_RX_D0_P
IO_L04_35_RX_D3_N
AUXADC
RX_EXT_LO
RX_VCO_LDO_OUT
RXA_N
L5 B3C3
J6
C5C6
D6D5
D4E4E5E6F6F5F4G4
H11G11G5
G6
G10
B7B6B5B4
A3 M3
E12D11E11D10E10D9E9D8E8D7F8E7
K11
J12
K10
J11
K9
J10
K8
J9
K7
J8J7H8
L4K5
G1
G7G8
G2
M2M1
J1H1
L1K1
J5J4
L6
K6
H5C4
H9G9
M5
M8M7
M10M9
B8H12
G3
A11
K4E2D2J3 A7A8A9A10
D3F2B9 E3K3B10
F12
A1 A2 A4 A6 B1 B2 B12 C1 C2 C7 C8 C9 C10
C11
C12 D1 E1 F1 F3 H2 H3 H6 J2 K2 L2 L3 L7 L8 L9 L10
L11
L12
M4 A5 M6
D12 F7 F9 F11
G12 H7 H10
K12
M12M11
1 5
2
3
4
6
15
2
3
4
6
2345
13121110
7 8
9
PAD
6
1 14
1
2 3
1
23
1
2 3
GND4GND5GND6GND7GND8GND9
GND10GND11 GND12
GND13GND14GND15GND16GND17GND18GND19GND20GND21GND22
1
23
15
2
3
4
6
1 5
2
3
4
61
2 3
1
GND1GND2GND3
F10
A12
H4B11
GND
GND
GND GND NC
GND
GND
NC
GND
GND
GND
GND
GNDGND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND GND
GND GND
GNDGND
GND
GND
GNDGND
T/R_N
B0B1B2B3
VCCBVCCA
GND PADOE_N
GND
A3A2A1A0
GND
GNDGND
XTALNXTALP
TXB_NTXB_P
TXA_NTXA_P
VSSA
VSSA
VSSA
NC
RXA_NRXA_P
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
SPI_DO
AUXADC
RBIAS
VSSA
VSSA
RXC_N
VSSD
P1_D0/RX_D0_NP1_D2/RX_D1_NP1_D4/RX_D2_NP1_D6/RX_D3_NP1_D8/RX_D4_N
SPI_ENB
RESETB
VDDA
1P3_
BB
VDDA
1P3_
TX_S
YNTH
VSSA
RXC_P
P1_D1/RX_D0_PP1_D3/RX_D1_PP1_D5/RX_D2_PP1_D7/RX_D3_PP1_D9/RX_D4_P
P1_D10/RX_D5_N
CLK_OUT
SPI_CLKSPI_DI
VDDA
1P3_
RX_S
YNTH
VSSA
RXB_N
VDD_
INTE
RFAC
E
DATA_CLK_N
VSSD
TX_FRAME_N
P1_D11/RX_D5_P
VSSD
VSSA
SYNC_IN
TXNRX
VSSA
VSSA
RXB_P
VSSD
DATA_CLK_P
FB_CLK_N
TX_FRAME_P
RX_FRAME_PRX_FRAME_N
ENABLEEN_AGC
CTRL_OUT7
VDDA
1P1_
RX_V
CO
RX_VCO_LDO_OUTRX_EXT_LO_IN
VDDD
1P3_
DIG
VSSD
FB_CLK_P
VSSD
P0_D10/TX_D5_N
VSSD
CTRL_OUT4CTRL_OUT5CTRL_OUT6
VSSA
VDDA
1P3_
RX_V
CO_L
DO
VSSA
P0_D0/TX_D0_N
P0_D2/TX_D1_N
P0_D4/TX_D2_N
P0_D6/TX_D3_N
P0_D8/TX_D4_N
P0_D11/TX_D5_P
CTRL_OUT3CTRL_OUT2CTRL_OUT1
VDDA
1P3_
TX_L
O_B
UFFE
R
VDDA
1P3_
RX_L
O
VSSA
VSSD
P0_D1/TX_D0_P
P0_D3/TX_D1_P
P0_D5/TX_D2_P
P0_D7/TX_D3_P
P0_D9/TX_D4_P
CTRL_IN2CTRL_IN3
CTRL_OUT0
VDDA
1P3_
RX_T
X
VDDA
1P3_
RX_R
F
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
CTRL_IN1CTRL_IN0
TEST/ENABLE
AUXDAC2
VSSA
VSSA
VSSA
TX_VCO_LDO_OUT
VDDA
1P3_
TX_V
CO_L
DOVD
DA1P
3_TX
_LO
VDD_
GPO
GPO_0GPO_1GPO_2GPO_3
AUXDAC1
VSSA
VSSA
TX_ENT_LO_IN
VDDA
1P1_
TX_V
CO
VDDA
1P3_
RX_T
XVD
DA1P
3_RX
_TX
VDDA
1P3_
RX_T
XVD
DA1P
3_RX
_TX
VSSA
TX_MON
VSSA
NCVSSA
VSSA
NCNCGND
GND
GNDGND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
2A @ 1.35V
POWER MANAGEMENT SECTION
BALL B8
BALL H12
BALL B9 & B10
MODULE (DAUGHTER BD)
VIN = 5V MAX
BALL E2 & F2
BALL K3
BALL J3
BALL K4
BALLS E3, D3,A10, A9, A8, A7, D2
BALL F12
BALL T2
2A @ 1.8V
3A @ 1V
9 10
<DESIGN_VIEW>
: PowerProduct(s): AD9364HW TYPE : Customer Evaluation Z
1:1
D202_041351
Neil L Wilson
10K
10K
0.047UF
0.047UF
10K180PF
0.0056UF150PF
10UF10UF
10UF10UF
0.047UF
47UF47UF
47UF47UF
1UF
10UF
0.0033UF
10K
4.75K
22UF
47UF
56000PF
0.1UF
22UF
47UF47UF47UF47UF
1K
15K
18.7K
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF 0.1UF 1UF 0.01UF 1UF
130
0.01UF 1UF
1UF 0.01UF
10UF
10UF0.1UF
0.01UF 1UF
1UF
1UF
10UF
10K
0.01UF
10UF 10UF 0.1UF 0.1UF
0.01UF
10K
0.01UF1UF
0.01UF1UF
0.01UF1UF
0.1UF0.1UF
1UF0.01UF
1UF0.01UF
10UF10UF
1UF 0.01UF 0.01UF1UF
150NH
10
1UH
10UF
10UF
23.2K
46.4K
ADP7104ACPZ-3.3-R7
19.6K
ADP2164ACPZ
0.47UH
10
180NH
180NH
ADP2114ACPZ
27.4K
1.5UH
ADP1754ACPZ-1.3
BSS138LT1G
QTLP600C4TR
75OHM
ADP1754ACPZ-1.3
ADP7102ACPZ-2.5
1.5UH
44.2K
L0805100OHM
100OHML0805
L0805100OHM
L0805100OHM
100OHML0805
100OHML0805
100OHML0805
100OHML0805
100OHML0805
30K
R22
R25
C144
C142
R47C68
C69C67
C139C45
C137C37
C150
C135C129
C136C132
C146
C147
C114
R46
R20
C65
C66
C127
C61
C64
C131C130C128C119
R49
R34
R35
C198
C196
C197
C194
C195
C193
C191
C200 C319 C358 C360 C361
R113
C334 C335
C324 C325
C38
C365C364
C330 C331
C36
C199
C363
R304
C340
C341 C342 C343 C344
C311
R306
C321C320
C329C328
C333C332
C315C314
C323C322
C327C326
C313C312
C354 C355 C356 C357
E10
U18R301
L302
TP2
E3
E4
E5
E6
E9
E8
E7
E2
Q14
U6 E11
U9
U19
D3
U4
L5
L3
L4
R10
U20
R48
L10
L7
R23
R39
R45
C148
C149
R38
L6
R29
1.8V
JX_VIN
VDD_INTERFACE
PG_1P0V
PG_1P8V
FB_1P35V
COMP_1P35V
PWR_GD
1P3_TX
VDDD_DIG VDDA_RX_TX
VDDA_BB
VDDA_RX_SYNTH
VDDA_TX_LO
VDDA_TX_SYNTH
VDDA_RX_LO
FB_1P8V
VCC-1P35
PG_1P0VFB_1P8V
JX_VIN PG_1P8V
PWR_ENABLE
PG_1P8V
COMP_1P8V
COMP_1P35V
ADP2114_VIN
JX_VIN
JX_VIN
VCC-3P3V-IO
VCC-3P3V
PWR_GD
ADP2114_VIN
VCCINT-1P0V
VCCO-DDR
1.0V
1.35V
PG_MODULE
3.3V
PG_MODULE
3.3V
VDDA_GPO
VDDA_GPO_PWR
1P3_SUPPLY_B
1P3_SUPPLY_APWR_GD
VCCPCOM-1P8V
3.3V
VCCPINT-1P0V
VCC-BRAM
VDD_INTERFACE
SYNC
COMP_1P8V
FB_1P35V
ADP2114_VIN
PWR_GD_1.35V
1.8V
FB0
1 2
15
4
5 PAD6 7 8
16
12 13
2
91011
1
3
14
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
3
1
2
5
3 64
PAD
728 1 1 2
5
3 64
PAD
728 1
4
68 PAD
5
97
123
1516
1011121314
C
A
2
7
28
13
32
9
3
1
6
PAD22 21 20 19
29
12
4
30
11
2423
1817
5
31
10
8
272625
141516
4
68 PAD
5
97
123
1516
1011121314
GND GND GND
GND GND
GND GNDGND GND
GND GND
GND
GND
GND
SYNC
PADPGNDGND
SW
PGOOD
RT
FBTRKENVIN
PVIN
GNDGNDGNDGND
GND
GND
GNDGND
GNDGND GND GND
GND
GND
GND
GND
GND
GNDGND
GNDGND
GNDGND
GNDGNDGNDGND
GNDGND
GND
GND
GND GND
GNDGND
GND
GND
SENSE
VOUT
NC
SS
GND
PG
EN
VIN
PAD
GND GND
GND GND
GND
GND
GND
GND
GND
GND
VIN6VIN5VIN4
VIN3VIN2VIN1
VDD
PAD
PGND
4PG
ND3
PGND
2PG
ND1
GND
SS2FB2 V2SET
SW4SW3
COMP2
PGOOD2
SW2SW1
COMP1
PGOOD1
EN2
SS1FB1 V1SETEN1
OPCFG
SYNC_CLKOUTFREQSCFG
GND
SENSE
VOUT
NC
SS
GND
PG
EN
VIN
PAD
SENSE
PAD
VIN
PGENNC GND
VOUT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SENSE_ADJ
PAD
VIN
PGEN_UVLO
NC GND
VOUT
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
CLK MUST BE 1.3VP-P MAX
10 10
<DESIGN_VIEW>
: PowerProduct(s): AD9364HW TYPE : Customer Evaluation Z
1:1
D202_041351
Neil L Wilson
4.7UF4.7UF
0.1UF
0.1UF
10K
1K
DNI
49.9
4.7K4.7K
0.1UF
DNI
10K
10K 10K
DNI
10K
0.1UF
4.7K4.7K
4.7UF
10UF10UF 10UF
0
4.02K
DNI
ADM7160AUJZ-1.8
40MEGHZ301
BSS138LT1G
ADG772BCPZ
18PF 18PF
4.02K
4.02K
4.02K
AD7291BCPZ
0.1UF
TCA9517DGKR
C188
Y4C152 C5 C113
R33
R55
R5
R44R42
C244
R64
R63 R65
R66
C243
R58R57
C133
C158C124 C134
U24
R61
R62
R67
U21R68
C111
R54
Q6
U5
C216 C165
U7
C62
3.3V
AD9364_CLK
IO_00_34_AD9364_CLKSEL
3.3V
IO_00_34_AD9364_CLKSEL
PS_MIO50_501_SD0_CD
3.3V
XTAL_N
JX3_SD1_CDN
SD_SEL
J3-9
SDA_AD7291SCL_AD7291
PHY1_AVDD_1V8_OUT
VTTVREFVTT_0P75
FPGA_VBATT1P3_SUPPLY_B1P3_SUPPLY_A
3.3V
3.3V
3.3V
SCLSDA
JX_VCCO_13
SDA_AD7291SCL_AD7291
3.3V
3.3V
VDDA_GPO
12
1113
8
9 6PAD
17
15 14
10
16
18192012345
7
5
4
2 73 6
1 8
3
1
2
1
2
3
4
2
8
10
45
13
97
6
3
2 4
1 5VOUT
NC
EN
GND
VIN
GND GND
GND
GND
GND
D2
GND
S2A
S1A D1S1BIN1
S2B
IN2
VDD
GND
E/DGND
VDDOUT
GND
GNDGND
GND
GND
GND
GND
VCCB
SCLBSDAB
ENGND
SDAASCLA
VCCA
GND
GND
GND
GND
GNDGND
GNDGND
PAD GND1GND
VDD VREF
SDA
ALERT
DCAP
SCLAS1AS0
VIN7VIN6VIN5VIN4VIN3VIN2VIN1VIN0
VDRIVE
PD_N/RST_N
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
