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Customer Information from Tektronix, Inc.,Beaverton, Oregon 97077

Editor: Gordon Allison

Contents

2 A 16-channel logic analyzer for the 7000 SeriesA plug-in logic analyzer with built-in IG-bit word recog­nizer transforms your 7000 Series Oscilloscope into ahigh-performance logic analysis tool for working in thedigital domain.

8 A plug-in word recognizer with digital delayA companion plug-in for the LA 501 provides data ac­quisition with high-impedance active probes, IG-bit wordrecognition, and digital delay.The 'VR 501 can also operate as a stand-alone wordrecognizer or digital delay unit.

12 The FG 504-a new standard in functiongenerators.A 40-MHz function generator with (i-ns rise time, 3D-voltpeak-to-peak output, and phase lock on'ers a new levelof operating coll\'enience, \'ersatility, and signal gener­ation.

16 A new low-cost 500 MHz probeThe circuit-loading effect of a new FET probe is com­pared with that of high-impedance passive probes.Designed to work into :;0 0 or I Mo, the probe featuresdc offset and wide dynamic range.

19 New productsIncluded are a host of new products for TV and CATVbroadcasters & designers.

Servicescope, a regular feature, does not appear in thisissue because of space considerations. It will resume inthe next issue.

Cover: Some of the unique features of the 7001/7000Series logic analyzer system are presented in this artistictreatment. The digital readout abo\'e the traces showsthe number of clock pulses occurring between the triggerand cursor positions_ The readout below the traces is thebinary word present at the cursor position. (The triggerand cursor position are not shown in this display.)

Copyright © 1976, TektroniX, Inc. All rights reserved. U.S.A. andForeign Products of TektroniX, Inc. are covered by U.S.A. andForeign Patents and/or Patents Pending. TEKTRONIX, TEK,SCOPE-MOBILE, TELEQUIPMENT and @ are registered trade­marks of Tektronix, Inc. Printed in U.S.A.

Keith Taylor

A16-channellogicanalyzer for the7000 Series

M ore than just an oscilloscope. This is the phraseoften used to describe the 7000 Series. And for

good reason. Plug-in versatility transforms 7000 SeriesOscilloscopes into counters, digital multimeters, spec­trum analyzers, time-domain reflectometers, curve trac­ers, rapid-scan spectrometers, etc. Now, with the intro­duction of the 7DO 1 plug-in, 7000 Series Oscilloscopesbecome state-of-the-art logic analyzers,

The 7DO 1 is a l6~channel, logic timing analyzer thatpresents data in the familiar oscilloscope-type, time­related diagram pictured in figure 1. But, as you cansee, there's much more that meets the eye in figure 1than just the usual multi-trace, logic timing diagram.Several features have been added to aid you in analyz­ing the displayed data.

Note the two vertical rows of bright dots, The rowat the left indicates the triggering point. In this in­stance, we have selected the post-trigger position, whichmeans that 90% of the data displayed occurs after thetrigger. Pre-trigger and center-trigger positions areavailable at the flip of a switch, to give you a wide rangeof data to view.

The second row of bright dots in the display providesa reference point for making time comparisons betweendisplayed channels. This row of dots can be positionedanywhere on the horizontal axis by means of the cursor

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Fig. 1. A wealth of information is available from the display gen­erated by the 7DOI. The intensified dots at left show the triggerpoint. The dots about two divisions to the right are a movablecursor. The number of clock pulses occurring between the two

bright dots is displayed at the top of the screen. The l6-bit binaryword at the cursor po~ition is displayed at the bottom of thescreen. Right to left corresponds with top to bottom.

There are two paths through the Word Recognizer,synchronous and asynchronous, selectable by a front­panel switch. In the asynchronous mode, a variablefilter is inserted in the trigger path that preventsglitches and other anomalies from causing false trig­gering. Word recognition of bit combinations of short­er duration than the filter setting is inhibited. Maxi­mum filter width is at least 300 ns.

The trigger point indicated on the display is mostaccurate when operating the Word Recognizer in theasynchronous mode with the filter set at minimum, orwhen using an external sampling interval. The triggerposition indication is less accurate when triggeringfrom channel 0, or when the asynchronous filter is ad­vanced clockwise.

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The built-in Word Recognizer operates independentof the rest of the logic analyzer. When all of the condi­tions required for word recognition are met, the dataacquisition circuits are enabled and a HI signal is sup­plied to a fron t-panel connector, for triggering anoscilloscope or other associated equipment. A WordRecognizer output occurs each time the conditions aremet, whether the logic analyzer is operating in the storeor display mode.

For applications where it is desirable to page througha long sequence of events, a companion plug-in, the7DIO, provides digital delay by up to 107 events. Thedelayed trigger output of the 7DIO serves as an externalqualifier or trigger for the 7DO 1. The 7D 10 countsevents at rates up to 50 MHz.

Display Clock Store!

Display Clock Inhibit Display MemoryClock Selector

Store Clock Gate Latch

Store Clock Inhibit Clock -

Ch4

ChOCh8

Ch12

I~-~-

• Format I

2568ilRAM

2568ilRAM

t

2568itRAM

II---

Data f--

Latch 256 Bitf- RAM

DataSelector

ChOData

Ch8 SelectorFormatted

Ch4 tor 16Channels

Ch12

Ch4

Ch12

ChO o-f-­Ch8

r-·

• FOi~tl ._..,.,;

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0-- 4 Selector ~

0---+ FO~~ra:ed ~

Ch12 o-r Channels ~.....ChO

Ch8

Ch4FromProbe

Fig. 2. The 4-k memory in the 7DOI is formattable. One of four4 x 256-bit sections is shown. It can store 1024 bits from one chan­nel, 512 from two, or 256 from four channels. In 4-channel opera-

tion the Data Selector functions as a 4-bit shift register, in 8- and16-channel operation as 4-bit latches. '

Data inputsUp to 16 channels of parallel data can be acquiredsimultaneously by the 7DOl. Minimum loading (I MO,5 pF) on the circuit under test is achieved by two activeprobes with multiple inputs. Probe qualifier and exter­nal clock inputs are also provided for in the activeprobes.

You have a choice of threshold levels for the probeinputs-a preset +1.4 volts for TTL applications, orselection over a range of -+- 12 volts by a front-panelvariable control.

Data can be clocked into the 7DOI in either a syn­chronous or asynchronous mode. In asynchronous, theclock may be either internal or external at rates up to100 MHz depending upon the number of channels inuse. To match the resolution of the measurement toyour specific application, sample intervals derived fromthe internal clock may be selected over the range of5 ms to 10 ns, in a 1-2-5 sequence.

A formattable memoryOne of the most useful features of the 7DOI is the for­mattable memory. Consisting of sixteen 256-bit randomaccess memories (RAMs) ,the memory can be formattedby a front-panel switch to store four channels with 1024data bits per channel, eight channels with 512 bits perchannel, or sixteen channels with 256 bits per channel.

Let's take a look at how this is accomplished (seefigure 2). The 16 data inputs are arranged in groupsof four, each group coupled to a corresponding 4 x 256­Bit RAM. In the 4-channel mode of operation, the DataSelector functions as a 4-bit shift register, acquiringfour bits of data input from channel O. The Data Latchtransfers the data from the outputs of the Data Selectorto the inputs of the four, 256-Bit RAMs. Througha three-gate arrangement controlled by the DATACHANNELS switch, the outputs of the RAMs can beadded to give us a single 1024-bit memory, two 512-bitmemories, or four 256-bit memories. The function of theData Selector is also con trolled by the DATA CHAN­NELS switch to pass four bits of data from one channel,two bits from each of two channels, or one bit from eachof four channels, to the Data Latch.

Data acquisition and displayFigure 4 is a simplified block diagram of the 7DOl. Let'srefer to it and go through a cycle of acquiring and dis­playing data. A good point to start is when reset occurs.

When display time ends, a reset signal is generated bythe reset circuitry. This resets the trigger flip-flop, trig­ger and address counters, and the store/display flip-flop,switching the memory from the display mode to thestore mode. Data, which is clocked into the Data Latchat the high-frequency clock rate, is transferred to the

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Fig. 3. The 7DlO Digital Delay plug-in is an ideal companion forthe 7DOl. It will count up to 107 arbitrary trigger events, periodicor aperiodic, and deliver an output after the preselected count hasbeen reached.

setting of the DATA CHANNELS switch. A separate1-, 2-, or 4-times divider is used for the trigger low­frequency clock because of phasing considerations re­lated to the memory low-frequency clock.

The trigger counter counts 16, 128, or 240 counts(depending upon trigger position selected) and thengenerates the first flag. During this flag, the memoryclock is summed with a gate derived from the triggerclock, to generate a gate that switches the Store/DisplayFlip-Flop to the display mode. Transition from storeto display is thus made in phase with the memory low­frequency clock.

The display clock, which runs at 2 /-,s, now becomes thehigh-frequency clock. It, in turn, is divided by 1, 2, or 4to become the memory and trigger low-frequency clocks.During display time, the outputs of the sixteen, 256-BitRAMs are displayed in serial fashion, as determined bythe Output Steering and Multiplexer circuitry.

In the display mode, the trigger counter countsthrough 256 counts of the display clock (equivalent toone display line) and generates a second flag. This flagresets the sweep, blanks the crt, and selects the nextchannel to be displayed. This flag also goes to a divide­by-16 coun ter that sets a flag when sixteen channels havebeen displayed. When the display time ends, a resetpulse is generated and the store/display cycle startsagain.

To further enhance the flexibility of the 7DOI, achoice of two display modes - Full Display or FirstTrigger - can be selected by positioning an internaljumper. In the Full Display mode, the trigger to theTrigger Flip-Flop is inhibited until the Address Count­er has completely cycled. This assures that the memoryis filled with valid data.

In the First-Trigger mode, it is conceivable that atrigger may occur before the memory is completelyfilled. If this occurs~ the display is blanked during thetime that invalid data would be presented.

Data outputsData from the memory is available in both parallel andserial format from an internal 25-pin connector. Alsoavailable are the display/store, flag, frame, trigger in­tensify, and master reset outputs.

Two inputs are made via the connector: record en­able and external display clock input. An external dis­play clock is required if the data are to be output tocomputer for further analysis.

SummaryThe 7DOI is designed to offer high-performance, 16­channel logic analysis to 7000 Series users. Used withconventional oscilloscope plug-ins in a four-hole main­frame, you can have both an oscilloscope and a logicanalyzer in a single package. The formattable memoryoffers unparalleled flexibility, and the high-speed data

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memory at the memory low-frequency clock rate, start­ing with the end of reset. The high-frequency clock rateis determined by the SAMPLE INTERVAL switch set­ting, and is divided by I, 2, or 4 times to establish thelow-frequency clock. Data is clocked into the memoryuntil a trigger occurs, and for a period following thetrigger as determined by the DATA POSITION switchsetting. For example, in the CENTER position, half ofthe memory fills after the trigger occurs.

The input steering and latch circuitry determineshow data will be input to the memory. In the 4-channelmode, the data from channel 0 is clocked serially intoone 4 x 256 section of the memory, as previously dis­cussed. The data from channels 1, 2, and 3 are clockedinto their respective memories simultaneously, in asimilar manner.

Occurrence of the trigger, switches the trigger flip­flop, gating on the trigger low-frequency clock. Thelow-frequency clock is the store clock (high-frequencyclock) divided by 1, 2, or 4 times, depending upon the

EVENTS 51ARTCOO'lING $l}lJACt TRIGGER

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- ThresholdControl

Cursor

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Verti",,1Out

-2V =l Power \--+15V

~5 v Supply l---- -15 v---Output Serial

t---~. Steertng and I---=.:Dar:ta=---.1-----,/. Multiplexer

Memory

+1,2,4

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Latch andInput

Steering

Buffer andPolaritySelector

I

18-BitWord

Recognizer

Ch 0 to Trigger~e..sr- s,ource tSelector

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8 Lines

-r--

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Probe#2

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Interfaceto

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f-----+-Out

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I

100MHzOscillator

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Flag

21'SDisplayClock

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ClockSleering

ExternalClock Internalr----. Store

Clock

TriggerCounter

Datachannels I-­4,$.16

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Delay

1Trigger

TriggerSourceSelector

SyncFiller Trigger

F-F

CHO-

Reset

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Trigger

Intensify

Fig. 4. Simplified block diagram of the 7DOI.

acqulSltlOn and mmimum loading afforded by activeprobes makes the 7DOI ideal for working with higherspeed logic families.

AcknowledgmentsMurlan Kaufman as Project Manager provided overalldirection for the 7DOl. Project Leader was Keith Taylor,with Morris Green and Jeff Bradford doing electricaldesign, and Ed Wolf mechanical design, Dick Anderson,Group Technician, provided valuable assistance, as didBeverley Kateley and Dona Fricker on prototype as­sembly and circuit board details. Roy Kaufman, Evalua­tion Engineer, and Dave McCullough, Marketing Pro­gram Supervisor, also made valuable contributions. Ourthanks to Wendell Damm for his work on the activeprobe, and to the many others who contributed to thecompletion of the project. @

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