· Contents 6 Datasheet Revision History Date Revision Description 10/03 -001 Initial release....

Intel StrataFlash Wireless MemorySystem (LV18/LV30 SCSP)1024-Mbit LV Family

Datasheet

Product Features

The Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP) family offers a variety ofhigh performance code segment and large embedded data segment combination flash dies incommon package footprints and ballouts on 0.13 µm ETOX™ VIII flash technology. The codesegment flash features 1.8 V low-power operations with flexible multi-partitions, dual operationRead-While-Write/Erase, asynchronous and synchronous reads at 54 MHz. The data segment flashfeatures 1.8 V low-power operations optimized for cost sensitive large embedded asynchronousdata application. The LV device integrates up to two code segment flash dies and two data segmentflash dies compatible with other LQ/LVQ or LX/LVX SCSP family ballout packages.

Device Architecture—Flash die density: 128-, 256-Mbit—Top or Bottom flash parameter

configuration Device Voltage

—Core: VCC = 1.8 V (Typ)—I/O: VCCQ = 1.8 V or 3.0 V (Typ)

Device Common Performance—Buffered EFP: 5 µs / Byte (Typ) per die—Buffer Program: 7 µs / Byte (Typ) per

die

—Concurrent Buffered EFP: 6.4 Mbitsper second (4 dies)

Device Common Architecture—Asymmetrical blocking structure

—16-KWord parameter blocks (Top orBottom); 64-KWord main blocks

—Zero-latency block locking—Absolute write protection with block

lock down using F-WP# Device Packaging

—88 balls (8 x 10 active ball matrix) forLVQ device and 103 balls (9 x 12 ballmatrix) for LVX device

—Area: 8 x 11 mm to 11 x 11 mm—Height: 1.2 mm to 1.4 mm

Code Segment Flash Performance—85 ns initial access at 1.8 V I/O—25 ns async page read at 1.8 V I/O—14 ns sync read (tCHQV) at 1.8 V I/O

—54 MHz CLK at 1.8 V I/O Data Segment Flash Performance

—170 ns initial access at 1.8 V I/O—55 ns async page read at 1.8 V I/O

Code Segment Flash Architecture—Hardware Read-While-Write/Erase—Multiple 8-Mbit or 16-Mbit Partition Sizes—2-Kbit One-Time Programmable (OTP)

protection register Data Segment Flash Architecture

—Software Read-While-Write/Erase—Single Partition Size Die

Flash Software—Intel FDI, Intel PSM, and Intel VFM

—Common Flash Interface (CFI)—Basic/Extended Command Set

Quality and Reliability—Extended Temp: –25 °C to +85 °C—Minimum 100 K flash block erase cycle—0.13 µm ETOX VIII flash technology

253854-003February 2004

Notice: This document contains preliminary information on new products in production. Thespecifications are subject to change without notice. Verify with your local Intel sales office thatyou have the latest datasheet before finalizing a design.

2

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Datasheet

THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BYHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMSIMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIESESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHEROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

nges to specifications and product descriptions at any time, without notice.

rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these forshall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

ireless Memory System (LV18/LV30 SCSP), 1024-Mbit LV Family may contain design defects or errors known as errata whichuct to deviate from published specifications. Current characterized errata are available on request.

ntel sales office to obtain the latest specifications and before placing your product order.

ts which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-ing Intel's website at http://www.intel.com.

orporation, 2004.

rands may be claimed as the property of others.

Contents

Contents1.0 Introduction ...............................................................................................................................7

1.1 Nomenclature .......................................................................................................................71.2 Acronyms..............................................................................................................................81.3 Conventions..........................................................................................................................9

2.0 Functional Overview ............................................................................................................10

2.1 Product Description ............................................................................................................102.2 Product Segment Unique Features ....................................................................................12

2.2.1 Code Segment Die ................................................................................................122.2.2 Data Segment Die .................................................................................................132.2.3 xRAM Segment Die ...............................................................................................13

2.3 Product Configurations and Memory Partitioning ...............................................................132.4 Memory Map.......................................................................................................................16

3.0 Package Information ............................................................................................................18

3.1 Three Flash Dies: QUAD+ SCSP Mechanical Spec...........................................................193.2 Four Flash Dies: x16D Performance SCSP Mechanical Spec ...........................................20

4.0 Ballout and Signal Descriptions......................................................................................21

4.1 Signal Ballout......................................................................................................................214.2 Signal Descriptions .............................................................................................................23

5.0 Maximum Ratings and Operating Conditions ...........................................................25

5.1 Absolute Maximum Ratings ................................................................................................255.2 Operating Conditions ..........................................................................................................26

6.0 Electrical Specifications .....................................................................................................27

6.1 DC Current Characteristics .................................................................................................276.2 DC Voltage Characteristics.................................................................................................28

7.0 AC Characteristics ................................................................................................................29

7.1 AC Test Conditions.............................................................................................................297.2 Capacitance........................................................................................................................307.3 AC Read Specifications ......................................................................................................307.4 AC Write Specifications ......................................................................................................377.5 Program and Erase Characteristics ....................................................................................41

8.0 Power and Reset Specifications .....................................................................................42

8.1 Power-Up and Down...........................................................................................................428.2 Reset ..................................................................................................................................428.3 Power Supply Decoupling...................................................................................................438.4 Automatic Power Saving (APS) ..........................................................................................43

9.0 Design Guide: Operation Overview ...............................................................................44

9.1 Bus Operations ...................................................................................................................449.1.1 Reads ....................................................................................................................459.1.2 Writes.....................................................................................................................45

Datasheet 3

Contents

9.1.3 Output Disable ....................................................................................................... 469.1.4 Standby.................................................................................................................. 469.1.5 Reset ..................................................................................................................... 46

9.2 Flash Device Commands.................................................................................................... 479.3 Command Definitions ......................................................................................................... 49

10.0 Read Operations .................................................................................................................... 51

10.1 Asynchronous Page-Mode Read........................................................................................ 5110.2 Synchronous Burst-Mode Read (Code Segment) .............................................................. 5210.3 Burst Suspend .................................................................................................................... 5210.4 Read Array Command (0xFF) ............................................................................................ 5310.5 Read Status Register Command (0x70)............................................................................. 5310.6 Clear Status Register Command (0x50)............................................................................. 5510.7 Read Flash Device Identifier Command (0x90).................................................................. 5510.8 CFI Query Command (0x98) .............................................................................................. 57

11.0 Program Operations............................................................................................................. 58

11.1 Word Program Setup Command (0x40) ............................................................................. 5811.1.1 Factory Word Programming................................................................................... 59

11.2 Buffered Program Setup Command (0xE8)........................................................................ 6011.3 Buffered Program Confirm Command (0xD0) .................................................................... 6011.4 Buffered EFP Setup Command (0x80) ............................................................................... 6011.5 Buffered EFP Confirm Command (0xD0) ........................................................................... 61

11.5.1 Buffered EFP Setup Phase.................................................................................... 6211.6 Buffered EFP Program/Verify Phase .................................................................................. 62

11.6.1 Buffered EFP Exit Phase ....................................................................................... 62

12.0 Erase Operations................................................................................................................... 63

12.1 Block Erase Setup Command (0x20) ................................................................................. 6312.2 Block Erase Confirm Command (0xD0).............................................................................. 63

13.0 Suspend and Resume Operations ................................................................................. 64

13.1 Erase Suspend Command (0xB0) ...................................................................................... 6413.2 Program Suspend Command (0xB0).................................................................................. 6413.3 Program Resume Command (0xD0) .................................................................................. 6513.4 Erase Resume Command (0xD0)....................................................................................... 65

14.0 Block Locking and Unlocking Operations .................................................................. 66

14.1 Block Locking During Erase Suspend ................................................................................ 6614.1.1 F-WP# Lock-Down Control .................................................................................... 67

14.2 Lock Block Setup Command (0x60) ................................................................................... 6814.3 Unlock Block Command (0xD0).......................................................................................... 6814.4 Lock-Down Block Command (0x2F) ................................................................................... 68

15.0 Protection Register Operation (Code Die) .................................................................. 69

15.1 Reading the Protection Registers ....................................................................................... 6915.2 Program Protection Register Setup Command (0xC0)....................................................... 70

15.2.1 Locking the Protection Registers ........................................................................... 70

16.0 Configuration Operations .................................................................................................. 71

16.1 Read Mode Bit- RCR.15 ..................................................................................................... 73

4 Datasheet

Contents

16.2 Latency Count Bit - RCR[13:11] .........................................................................................7316.3 WAIT Polarity Bit - RCR.10.................................................................................................74

16.3.1 WAIT Signal Function ............................................................................................7516.4 Data Hold Bit - RCR.9.........................................................................................................7616.5 WAIT Delay Bit - RCR.8 .....................................................................................................7616.6 Burst Sequence Bit - RCR.7 ...............................................................................................7716.7 Clock Edge Bit - RCR.6 ......................................................................................................7816.8 Burst Wrap Bit - RCR.3.......................................................................................................7816.9 Burst Length Bit - RCR[2:0] ................................................................................................7816.10 Set Read Configuration Register Command (0x60) ...........................................................7816.11 Write Read Configuration Register Command (0x03) ........................................................78

17.0 Dual Operation Considerations .......................................................................................79

17.1 Consecutive Back-to-Back Bus Cycle Operations..............................................................7917.2 Read during a Buffered Program Operation .......................................................................8117.3 Simultaneous Operation Restrictions .................................................................................8117.4 Simultaneous Operation Details .........................................................................................82

17.4.1 Concurrent Operations Power Considerations ......................................................83

Appendix A Write State Machine (WSM) for Code Segment ......................................84

Appendix B Write State Machine (WSM) for Data Segment .......................................85

Appendix C Flowcharts .............................................................................................................86

Appendix D Common Flash Interface (CFI) for Code Segment ................................94

Appendix E Common Flash Interface (CFI) for Data Segment................................105

Appendix F Additional Information ....................................................................................110

Appendix G Ordering Information.......................................................................................111

Datasheet 5

Contents

Revision History

Date Revision Description

10/03 -001 Initial release.

02/04 -002

Updated AC and DC specs; updated available stacked lineitems; updated device block diagrams; changed all line itemsfrom UT-SCSP package option to SCSP package; and varioustext edits for clarity.

02/04 -003Corrected information in the Memory Map table, code and datasegments, bottom parameter and ballout information for theLVX family matrix listing.

6 Datasheet

1024-Mbit LV Family

1.0 Introduction

This document provides preliminary information about the Intel StrataFlash® Wireless MemorySystem (LV18/LV30 SCSP) 1024-Mbit LV family. This document describes only the flash diefeatures, operations, and specifications of the high performance code and large embedded datasegments within the memory subsystem. The complementary stacked RAM dies are described inthe associated documents, 768-Mbit LVQ Family with Asynchronous Static RAM, and 1024-MbitLVX Family with Dynamic RAM (document number 253852 and 253853 respectively).

1.1 Nomenclature

1.8 Volt Core Voltage range of 1.7 V – 2.0 V.

1.8 Volt I/O Voltage range of 1.7 V – 2.0 V.

Asserted Signal with logical voltage level VIL, or enabled.

Deasserted Signal with logical voltage level VIH, or disabled.

High-Z High Impedance.

Low-Z Signal is Driven on the bus.

Non-Array Reads Flash reads which return flash Device Identifier, CFI Query, ProtectionRegister and Status Register information.

Program An operation to Write data to the flash array.

Write Bus cycle operation at the inputs of the flash die, in which a commandor data are sent to the flash array.

Block Group of cells, bits, bytes or words within the flash memory array thatget erased with one erase instruction.

Parameter block Any 16-Kword flash array block.

Main block Any 64-Kword flash array block.

Top parameter Previously referred to as a top-boot device, a device with flashparameter partition located at the highest physical address of itsmemory map for processor system boot up.

Bottom parameter Previously referred to as a bottom-boot device, a device with flashparameter partition located at the lowest physical address of its memorymap for processor system boot up.

Partition A group of flash blocks that shares common status register read state.

Parameter partition A flash partition containing parameter and main blocks.

Main partition A flash partition containing only main blocks.

Die Individual flash or RAM die used in a stacked package memory device.

Datasheet 7

1024-Mbit LV Family

Segment A section of the stacked memory device divided for different operatingbehaviors. The stacked device can have up to three segments: a flashcode segment, a flash data segment, and a xRAM segment.

Code segment A segment that contains up to two flash memory dies optimized for highperformance code or data reads. Each die features multi-partitionssynchronous read-while-write or burst read-while-erase capability.

Data segment A segment contains up to two flash dies optimized for large embeddeddata storage. Each die feature single-partition asynchronous read, write,and erase operations.

xRAM segment A segment contains up to three xRAM memory dies. The xRAMsegment could include SRAM, PSRAM or LPSDRAM.

(Memory) System A stacked memory integration concept made up of multiple memorydies arranged in Code, Data, and xRAM segments.

Device A specific stacked flash + xRAM memory density configurationcombination within a memory system product family.

LV family Intel StrataFlash® Wireless Memory System (code-data) family.

LVQ family Denotes LV product family in a QUAD+ package ballout.

LVX family Denotes LV product family in a x16D Performance package ballout.

1.2 AcronymsBuffered EFP Buffered Enhanced Factory Programming

CUI Command User Interface

OTP One-Time Programmable

PLR Protection Lock Register

PR Protection Register

RCR Read Configuration Register

RFU Reserved for Future Use (Unused active signals in a package ballout)

SR Status Register

WSM Write State Machine

APS Automatic Power Savings

CFI Common Flash Interface

MLC technology Multi-Level Cell technology

RWW / RWE Read-While-Write / Read-While-Erase

8 Datasheet

1024-Mbit LV Family

1.3 Conventions

VCC Signal or voltage connection.

VCC Signal or voltage level.

Set Logical one (1).

Clear Logical zero (0).

0x Hexadecimal number prefix.

0b Binary number prefix.

SR4 A flash status register bit, in this case status register bit 4 of SR[7:0].

DQ[15:0] Denotes a group of similarly named signals, such as data bus.

A5 Denotes one element of a signal group, in this case address bit 5.

F1-CE# Denotes Chip Enable of flash die #1, where “F” to denote flash specificsignal suffix and “CE#” is the root signal name of the flash die. Othernotation includes: “S” to denote SRAM, “P” to denote PSRAM, “D” todenote LPSDRAM, and “R” to denote common RAM type signal.

VSS Denotes a global power signal of the stacked device, VSS is common toall memory dies within a stacked memory device.

QUAD+ Stacked package ballout containing 88 balls (8x10 active ball matrix)supporting 16-bit bus flash + PSRAM / SRAM up to 66 MHz CLK.

x16D Performance Stacked package ballout containing 103 balls (9x12 ball matrix)supporting 16-bit bus flash + xDRAM / SRAM up to 133 MHz CLK.

bit Binary unit, valid range [0, 1].

byte Eight bits, valid range [0x00 - 0xFF].

word Two bytes or sixteen bits, valid range [0x0000 - 0xFFFF].

Kbit 1024 bits.

KByte 1024 bytes (8,192 bits).

Kword 1024 words (16,384 bits).

Mbit 1,048,576 bits.

MByte 1,048,576 bytes (8,388,608 bits).

Gbit 1,073,741,824 bits.

Datasheet 9

1024-Mbit LV Family

2.0 Functional Overview

This section provides an overview of the features and capabilities of the LV18/LV30 SCSP familyin a 16-bit bus configuration. The intent of this document is to provide information describing thehigh performance code and large embedded data segments flash die features, operations, andspecifications within the memory system. The xRAM segment details are described in thefollowing datasheets:

• Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP); 768-Mbit LVQ Family withAsynchronous Static RAM (document number 253852)’

• Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP);1024-Mbit LVX Family withDynamic RAM (document number 253853).

2.1 Product Description

The Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP) family incorporates Intelfourth-generation Multi-Level Cell (MLC) on 0.13 µm ETOX™ VIII process technology toprovide a low power, high performance code execution and large embedded data solution.

The LV SCSP device is comprised of stacked high performance code segment flash dies, largeembedded data segment dies for cost-sensitive data storage, and xRAM segment dies. The highperformance code segment is a multi-partition, synchronous burst-mode Read-While-Write(RWW) or Read-While-Erase (RWE) Intel StrataFlash® wireless memory die. The large embeddeddata segment is a single partition, asynchronous Intel StrataFlash® wireless memory die optimizedfor cost-sensitive large embedded data storage applications. The LV family is available in twocommon device package footprints and ballouts: QUAD+ and x16D Performance, for seamlessupgrades through gigabit densities.

The QUAD+ ballout supports flash-only or flash + PSRAM and/or SRAM stacked memorycombinations within the LVQ device family. The QUAD+ ballout is a 0.8 mm ball pitch, 88 balls, 8x 10 active ball matrix supporting a memory system up to 66 MHz on a 16-bit bus. See Figure 8,“QUAD+ Signal Ballout for LVQ Device Family” on page 21 for electrical ballout.

The x16D Performance ballout supports flash-only or flash + LPSDRAM and/or SRAM stackedmemory combinations within the LVX device family. The x16D Performance ballout is an 0.8 mmball pitch, 103 balls, 9 x 12 active ball matrix supporting a memory system up to 133 MHz on a 16-bit bus. See Figure 9, “x16D Performance Signal Ballout for LVX Device Family” on page 22 forelectrical ballout.

The LV family is a 1.8 volt flash core device (F-VCC) with a common 1.8-volt or 3.0-volt I/O(VCCQ) bus options. The LV SCSP device is available with a minimum of one code segment flashdie and one data segment flash die. The LV SCSP device has a maximum of two flash dies per codesegment and two flash dies per data segment. See Table 2, “1024-Mbit LV Family Matrix (Flashonly)” on page 12 for available combinations.

Designed for low-voltage operations, the LV SCSP device supports flash read operations with F-VCC at 1.8 volt, erase and program operations with F-VPP at 1.8 or 9.0 volt. Buffered EnhancedFactory Programming (Buffered EFP) provides the fastest flash array programming performancethroughput. With F-VPP at 1.8 volt, F-VCC and F-VPP can be tied together for a simple, ultra-low-power design. In addition, the LV SCSP device provides data security through its individual zero-latency flash block lock capability. Each flash block can be unlocked, locked, or locked-down byhardware and/or software control. Pre-assigned flash Chip-Enable (F-CE#) signals allow the userto manage which flash die is selected. Refer to Table 1 on page 12 and Figure 1, “LVQ DeviceFamily Block Diagram and Figure 2, “LVX Device Family Flock Diagram for details.

10 Datasheet

1024-Mbit LV Family

NOTE: †: Flash die #2 and die #3 can be configured either as a Code or a Data die option within the 768-Mbit LVQ device family.

Figure 1. LVQ Device Family Block Diagram

Figure 2. LVX Device Family Flock Diagram

xRAM Segment

LVQ Family

Flash Die #1(128- or 256-Mbit)

Flash (Code/Data) Segment


S-VCC

F-WE#

CLK

A[MAX:MIN]

DQ[15:0]

F3-CE#

F1-OE#

F1-CE#

F-RST#

ADV#

WAIT

R-UB#

F2-VCC

F-VPP

VCCQVSS

F2-CE#

S-CS2

S-CS1#

R-LB#

SRAM Die #1(8-Mbit)

P-MODE/P-CRE

P2-CS#

R-OE#

R-WE#

P-VCC

F2-OE#

F-WP#

Flash Die #3†

(128- or 256-Mbit)

PSRAM Die#2

(64/128-Mbit)

PSRAM Die#1

(32/64/128-Mbit)

P1-CS#

F1-VCC

xRAM Segment

LVX Family


Flash (Code/Data) Segment




R-VCC

D-CAS#D-BA[1:0]

R-CLK

D-RAS#

D-CKE

F-RST#

WE#

F-CLK

A[MAX:MIN]

DQ[15:0]

F3-CE#

F1-CE#

F-WP1#

F-WP2#

ADV#

WAIT

OE#

D-DM1 / R-UB#

F-VCC

F-VPP

VCCQ

VSS

F4-CE#

F2-CE#

S-CS2

S-CS1#

S-VCC

D-DM0 / R-LB#

R2-CS#

SRAM Die #1(8-Mbit)

LPSDRAM Die #2(128/256-Mbit)

LPSDRAM Die #1(128/256-Mbit)

R1-CS#

Datasheet 11

1024-Mbit LV Family

Table 1. Pre-assigned Flash-CE# Definition for LVQ and LVX Device Family

2.2 Product Segment Unique Features

2.2.1 Code Segment Die

The code segment die includes the following enhanced features unless specifically notedotherwise.

• 64 unique (Intel pre-programmed) identifier bits and 2,112 user-programmable OTP bits foreach code segment flash die.

• Standard write, erase, and read modes (asynchronous, page, and burst) of Intel StrataFlash®

Wireless Memory.

• Simultaneous read-while-program or read-while-erase operations, enabling a burst readoperation in one partition with simultaneous program or erase operations in other partitions.

• Burst-read across partition boundaries is allowed, but not across segment dies within the LVSCSP device.

• User application code is responsible for ensuring that burst-mode reads does not cross into apartition that is in program or erase mode.

Stacked Combo: Flash Die #1 Flash Die #2 Flash Die #3 Flash Die #4

Code + Data F1-CE# (Code) F2-CE# (Data) N/A N/A

Code + Data + Data F1-CE# (Code) F2-CE# (Data) F3-CE# (Data) N/A

Code + Code + Data F1-CE# (Code) F2-CE# (Code) F3-CE# (Data) N/A

Code + Code + Data + Data F1-CE# (Code) F2-CE# (Code) F3-CE# (Data) F4-CE# (Data)

Table 2. 1024-Mbit LV Family Matrix (Flash only)

LVFamily

I/OVoltage

Code segmentflash die

Data segmentflash die Package Size SCSP Ballout Package

Type Notes

LVQ

1.8 V

256L18 256V18 8x11x1.2 QUAD+ SCSP 1,2

256L18 + 256L18 256V18 8x11x1.4 QUAD+ SCSP 1,2

256L18 256V18 + 256V18 8x11x1.4 QUAD+ SCSP 1,2

3.0 V256L30 256V30 8x11x1.2 QUAD+ SCSP 1,2

256L30 256V30 + 256V30 8x11x1.4 QUAD+ SCSP 1,2

LVX

1.8 V 256L18 + 256L18 256V18 + 256V18 11x11x1.4 x16DPerformance SCSP 1,2

3.0 V 256L30 + 256L30 256V30 + 256V30 11x11x1.4 x16DPerformance SCSP 1,2

NOTES:1. Available in Top or Bottom parameter configuration. Refer to Table 3, “LV Flash Code and Data Die Stacked

Configuration” on page 14 for parameter configuration specifics.2. For product combination not listed, please contact your local Intel representative for details.

12 Datasheet

1024-Mbit LV Family

2.2.2 Data Segment Die

The data segment die includes the following features unless specifically noted otherwise:

• No unique identifier bits or user-One-Time Programmable bits.

• Single partition asynchronous single word or page-mode read operations.

• No simultaneous read-while-program or read-while-erase operations. However, this capabilitycan be accomplished with software through program suspend and erase suspend operations.

2.2.3 xRAM Segment Die

The xRAM segment can consist of up to two Pseudo-SRAM (PSRAM) dies and one SRAM die inthe LVQ family. For the LVX family, the xRAM segment can consist of up to two LPSDRAM diesand one SRAM die.

For the LVQ family RAM density options:

• The first PSRAM die can have a density of 32-Mbit, 64-Mbit, or 128-Mbit.

• The second PSRAM die can have a density of 64-Mbit or 128-Mbit.

• The SRAM die has a density of 8-Mbit.

For the LVX family RAM density options:

• The first LPSDRAM die can have a density of 128-Mbit, 256-Mbit, or 512-Mbit.

• The second LPSDRAM die can have a density of 256-Mbit or 512-Mbit.

• The SRAM die has a density of 8-Mbit.

The xRAM segment details are described in the following datasheets:

• Intel StrataFlash Wireless Memory System; 768-Mbit LVQ Family with Asynchronous StaticRAM Datasheet (document number 253852).

• Intel StrataFlash Wireless Memory System; 1024-Mbit LVX Family with Dynamic RAMDatasheet (document number 253853).

2.3 Product Configurations and Memory Partitioning

The LV18/LV30 SCSP family consist of at least one code die and one data die. The minimumdensity option is 384-Mbit: 256-Mbit of code + 128-Mbit data, or 128-Mbit of code and 256-Mbitof data.

By default, the first flash die is the first code segment flash die, a fast, eXecute-In-Place (XIP)solution ideal for an instruction fetch application. This portion is the user-selected parameterconfiguration option (Top or Bottom) in either a 128-Mbit flash die or a 256-Mbit flash die, eachcontaining one parameter partition and several main partitions.

The 128-Mbit memory array is divided into sixteen 8-Mbit partitions. Each die density containsone parameter partition and fifteen main partitions. The 8-Mbit top or bottom parameter partitioncontains four 16-Kword blocks and seven 64-Kword blocks. The remaining fifteen 8-Mbit mainpartitions each contain eight 64-Kword blocks.

Datasheet 13

1024-Mbit LV Family

The 256-Mbit memory array is divided into sixteen 16-Mbit partitions. Each device contains oneparameter partition and fifteen main partitions. The 16-Mbit top or bottom parameter partitioncontains four 16-Kword blocks and fifteen 64-Kword blocks. The remaining fifteen 16-Mbit mainpartitions each contain sixteen 64-Kword blocks.

The large embedded data segment flash die is a single partition asynchronous page-mode readdevice with density options of 128-Mbit or 256-Mbit. The single partition is made up of four 16-Kword parameter blocks and 64-Kword main blocks. The parameter configuration option is notuser selectable; it is predefined as shown in Table 3, “LV Flash Code and Data Die StackedConfiguration” on page 14, and graphically shown in Figure 3 on page 15 and Figure 4 on page 15.

Table 3. LV Flash Code and Data Die Stacked Configuration

Top and Bottom Parameter Stacked Configuration

Die Stack Configuration

Code Segment Data Segment

1st FlashCode Die

(user selected)

2nd FlashCode Die

1st Flash DataDie

2nd FlashData Die

Top

Code + Data Top NA Bottom NA

Code + Data + Data Top NA Top Bottom

Code + Code + Data Top Top Bottom NA

Code + Code + Data + Data Top Bottom Top Bottom

Bottom

Code + Data Bottom NA Top NA

Code + Data + Data Bottom NA Bottom Top

Code + Code + Data Bottom Bottom Top NA

Code + Code + Data + Data Bottom Top Bottom Top

14 Datasheet

1024-Mbit LV Family

Figure 3. Top Parameter Configuration Stacked Convention

Figure 4. Bottom Parameter Configuration Stacked Convention

Top Parameter Configuration Stacked Convention

1 Code + 1 Data

Data(Bottom)

Code(Top)

Parameter Blocks

Main Blocks

Parameter Blocks

Data(Top)

1 Code + 2 Data

Code(Top)

Data(Bottom)

Code(Top)

2 Code + 1 Data

Code(Top)

Data(Bottom)

2 Code + 2 Data

Code(Top)

Code(Bottom)

Data(Top)

Data(Bottom)

Data(Top)

Code(Bottom)

Data(Top)

Data(Bottom)

Code(Top)

Code(Bottom)

Data(Bottom)

Data(Top)

Code(Bottom)

Code(Bottom)

Data(Top)

Code(Bottom)

Parameter Blocks

Main Blocks

Parameter Blocks

Bottom Parameter Configuration Stacked Convention

1 Code + 1 Data 1 Code + 2 Data 2 Code + 1 Data 2 Code + 2 Data

Datasheet 15

1024-Mbit LV Family

2.4 Memory Map

The 1024-Mbit LV family is available in numerous density and parameter configurations. Thememory map is based on the stacking of individual flash die density options of 128-Mbit or 256-Mbit. The 1024-Mbit LV family memory map shows individual flash die configurations and block/partition allocations.

The code segment flash die is made up of 128-Mbit dies or 256-Mbit dies, each containing oneparameter partition and several main partitions. Refer to Table 4, “Code Segment Flash DieMemory Map” on page 16 for details.

The data segment flash die density is made up of 128-Mbit dies or 256-Mbit dies, each containinga single partition architecture made up of four 16-Kword parameter blocks and 64-Kword mainblocks. Refer to Table 5, “Data Segment Flash Die Memory Map” on page 17 for details.

Table 4. Code Segment Flash Die Memory Map

FlashDie# Partitioning Block

Size (KW)

PartitionSize

(Mbit)

128-Mbit Flash PartitionSize (Mbit)

256-Mbit Flash

Block# Address Range Block# Address Range

Co

de

Seg

men

tF

lash

Die

Top

Par

amet

er

ParameterPartition

(Partition 0)

16

8

130 7FC000-7FFFFF

16

258 FFC000-FFFFFF

... ... ... ... ...

16 127 7F0000-7F3FFF 255 FF0000-FF3FFF

64 126 7E0000-7EFFFF 254 FE0000-FEFFFF

... ... ... ... ...

64 120 780000-78FFFF 240 F00000-FFFFFF

Main Partitions(Partition 1-7)

64 119 770000-77FFFF 239 EF0000-EFFFFF

... ... ... ...

64 64 400000-4FFFFF 128 800000-80FFFF


64 63 3F0000-3FFFFF 127 F70000-F7FFFF... ... ... ... ...

64 0 000000-00FFFF 0 000000-00FFFF

Co

de

Seg

men

tF

lash

Die

Bo

tto

mP

aram

eter


64

8

130 7F0000-7FFFFF

16

258 FF0000-FFFFFF

...

... ... ... ...

64 67 400000-40FFFF 131 800000-80FFFF


64 66 3F0000-3FFFFF 130 7F0000-7FFFFF

... ... ... ... ...

64 11 080000-08FFFF 19 100000-10FFFF

ParameterPartition

(Partition 0)

64 10 070000-07FFFF 18 0F0000-0FFFFF

... ... ... ... ...

64 4 010000-01FFFF 4 010000-01FFFF

16 3 00C000-00FFFF 3 00C000-00FFFF

... ... ... ... ...

16 0 000000-003FFF 0 000000-003FFF

16 Datasheet

1024-Mbit LV Family

Table 5. Data Segment Flash Die Memory Map

FlashDie# Partitioning Block

Size (KW)

PartitionSize

(Mbit)

128-Mbit Flash PartitionSize (Mbit)

256-Mbit Flash

Blk# Address Range Blk# Address Range

Dat

aS

egm

ent

Fla

shD

ie

Top

Par

amet

er

Single Partition

4x16 KwordParameter Blocks

127x64 KwordMain Blocks (128

Mb)


Mb

16

128

130 7FC000-7FFFFF

256

258 FFC000-FFFFFF

... ... ... ... ...

16 127 7F0000-7F3FFF 255 FF0000-FF3FFF

64 126 7E0000-7EFFFF 254 FE0000-FEFFFF

... ... ... ... ...

64 120 780000-78FFFF 240 F00000-FFFFFF

64 119 770000-77FFFF 239 EF0000-EFFFFF

... ... ... ...

64 64 400000-4FFFFF 128 800000-80FFFF

64 63 3F0000-3FFFFF 127 F70000-F7FFFF

... ... ... ... ...

64 0 000000-00FFFF 0 000000-00FFFF

Dat

aS

egm

ent

Fla

shD

ie

Bo

tto

mP

aram

eter

Single Partition

4x16 KwordParameter Blocks


Mb)


Mb

64

128

130 7F0000-7FFFFF

256

258 FF0000-FFFFFF

...

... ... ... ...

64 67 400000-40FFFF 131 800000-80FFFF

64 66 3F0000-3FFFFF 130 7F0000-7FFFFF

... ... ... ... ...

64 11 080000-08FFFF 19 100000-10FFFF

64 10 070000-07FFFF 18 0F0000-0FFFFF

... ... ... ... ...

64 4 010000-01FFFF 4 010000-01FFFF

16 3 00C000-00FFFF 3 00C000-00FFFF... ... ... ... ...

16 0 000000-003FFF 0 000000-003FFF

Datasheet 17

1024-Mbit LV Family

3.0 Package Information

The LV family is available in various die combinations in standard Intel® Stacked Chip ScalePackage (Intel® SCSP options).Two Flash Dies: QUAD+ SCSP Mechanical Spec

Figure 5. Mechanical Specifications for Two-Die QUAD+ SCSP (8x11x1.2 mm)

Millimeters InchesDimensions Symbol Min Nom Max Notes Min Nom MaxPackage Height A 1.200 0.0472Ball Height A1 0.200 0.0079Package Body Thickness A2 0.860 0.0339Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167Package Body Length D 10.900 11.000 11.100 0.4291 0.4331 0.4370Package Body Width E 7.900 8.000 8.100 0.3110 0.3150 0.3189Pitch e 0.800 0.0315Ball (Lead) Count N 88 88Seating Plane Coplanarity Y 0.100 0.0039Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512Corner to Ball A1 Distance Along D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472

Top View - Ball DownBottom View - Ball

Up

AA2

D

E

Y

A1

Draw ing not to scale.

S2

S1

A

C

B

E

D

G

F

J

H

K

L

M

e

12345678

b

A

C

B

E

D

G

F

J

H

K

L

M

A1 IndexMark

1 2 3 4 5 6 7 8

18 Datasheet

1024-Mbit LV Family

3.1 Three Flash Dies: QUAD+ SCSP Mechanical Spec

Figure 6. Mechanical Specifications for Three-Die QUAD+ SCSP (8x11x1.4 mm)

Millimeters InchesDimensions Symbol Min Nom Max Notes Min Nom MaxPackage Height A 1.400 0.0551Ball Height A1 0.200 0.0079Package Body Thickness A2 1.070 0.0421Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167Package Body Length D 10.900 11.000 11.100 0.4291 0.4331 0.4370Package Body Width E 7.900 8.000 8.100 0.3110 0.3150 0.3189Pitch e 0.800 0.0315Ball (Lead) Count N 88 88Seating Plane Coplanarity Y 0.100 0.0039Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512Corner to Ball A1 Distance Along D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472

Top View - Ball Down Bottom View - Ball Up

AA2

D

E

Y

A1

Drawing not to scale.

S2

S1

A

C

B

E

D

G

F

J

H

K

L

M

e

12345678

b

A

C

B

E

D

G

F

J

H

K

L

M

A1 IndexMark

1 2 3 4 5 6 7 8

Datasheet 19

1024-Mbit LV Family

3.2 Four Flash Dies: x16D Performance SCSP Mechanical Spec

Figure 7. Mechanical Specifications for x16D Performance SCSP (11x11x1.4 mm)

Millimeters InchesDimensions Symbol Min Nom Max Notes Min Nom MaxPackage Height A 1.4 0.0551Ball Height A1 0.200 0.0079Package Body Thickness A2 1.070 0.0421Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167Package Body Length D 10.90 11.00 11.10 0.4291 0.4331 0.4370Package Body Width E 10.90 11.00 11.10 0.4291 0.4331 0.4370Pitch e 0.800 0.0315Ball (Lead) Count N 103 103Seating Plane Coplanarity Y 0.100 0.0039Corner to Ball Distance Along E S1 2.200 2.300 2.400 0.0866 0.0906 0.0945Corner to Ball Distance Along D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472

Note: Drawing not to scale.

Pin 1Corner

D

E

b

A

B

C

D

E

F

G

H

J

K

87654321 9

L

M

SCSPTop View - Ball Side Down

S1

S2

e

A2A1 A

Y

20 Datasheet

1024-Mbit LV Family

4.0 Ballout and Signal Descriptions

4.1 Signal Ballout

The 1024-Mbit LV family devices are available in two common ballouts: QUAD+ for the LVQdevice family and x16D Performance for the LVX device family, shown in Figure 8 and Figure 9.

Figure 8. QUAD+ Signal Ballout for LVQ Device Family

Pin 11 2 3 4 5 6 7 8

A DU DU DU DU A

B A4 A18 A19 VSS F1-VCC F2-VCC A21 A11 B

C A5 R-LB# A23 VSS S-CS2 CLK A22 A12 C

D A3 A17 A24 F-VPP R-WE# P1-CS# A9 A13 D

E A2 A7 A25 F-WP# ADV# A20 A10 A15 E

F A1 A6 R-UB# F-RST# F-WE# A8 A14 A16 F

G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G

H R-OE# DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H

J S-CS1# F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J

K F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQP-Mode/ P-

CREK

L VSS VSS VCCQ F1-VCC VSS VSS VSS VSS L

M DU DU DU DU M

1 2 3 4 5 6 7 8

Legend:

Do Not Use

Flash Specific

Top View - Ball Side Down

SRAM/PSRAM Specific

De-Populated BallsGlobal Signals

Datasheet 21

1024-Mbit LV Family

Figure 9. x16D Performance Signal Ballout for LVX Device Family

Pin 11 2 3 4 5 6 7 8 9

A DU A5 A7 A8 A20 A24 A25 A26 DU A

B A3 A4 A6 A18 A19 RFU A23 A27 A17 B

C A2 VSS VSS VSS R-VCC VSS VSS VSS A16 C

D A1 S-VCC R-VCC F-VCC ADV# F-VCC R-VCC RFU A15 D

E F-WP1# WE# R2-CS# DepopF4-CE# /

A28A22 A11 A14 E

F F-WP2# R1-CS# D-CAS# D-RAS# S-CS1# A21 A10 A13 F

G RFU F2-CE# F1-CE# D-BA0 D-CKE F-RST# A9 A12 G

H RFU S-CS2 F3-CE# D-BA1 RFU OE#D-DM1 /R-UB#

D-DM0 /R-LB#

H

J F-VPP VCCQ VCCQ F-VCC R-CLK F-VCC VCCQ VCCQ WAIT J

K DQ2 VSS VSS VSS F-CLK VSS VSS VSS DQ13 K

L DQ1 DQ3 DQ5 DQ6 DQ7 DQ9 DQ11 DQ12 DQ14 L

M DU DQ0 RFU DQ4 DQ8 DQ10 RFU DQ15 DU M

1 2 3 4 5 6 7 8 9

De-Populated BallsActive Balls

Legend:

Do Not Use

Top View - Ball Side Down

Depop(RFUs)

Reserved for Future Use

22 Datasheet

1024-Mbit LV Family

4.2 Signal Descriptions

Table 6 describes the individual flash die active signals used in the 1024-Mbit LV Family

Table 6. Signal Descriptions1 (Sheet 1 of 2)

Symbol Type Name and Function Notes

A[MAX:MIN] Input

ADDRESS: Global device signals.

Address inputs for all memory dies during read and write operations for x16 data bus.

• LVQ device family: Flash die address range: 128-Mbit: A[22:0]; 256-Mbit: A[23:0]; whereA[0] = AMIN is the lowest-order address bit.

• LVX device family: Flash die address range: 128-Mbit: A[23:1]; 256-Mbit: A[24:1]; whereA[1] = AMIN is the lowest-order address bit. A[0] ball is not applicable on the x16DPerformance ballout.

1

DQ[15:0] Input/Output

DATA INPUT/OUTPUT: Global device signals.

Inputs data and commands during write cycles, outputs data during read cycles. Data signalsfloat when the device or its outputs are deselected.

Data are internally latched during writes on the flash device.

ADV# Input

DEVICE ADDRESS VALID: Global Low-true input. (For stacked combinations withoutSynchronous PSRAM, ADV# is a flash specific input.)

• During synchronous flash read operations, addresses are latched on the rising edge ofADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.

• During synchronous PSRAM read or PSRAM write operations, addresses are latched onthe rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occursfirst.

• In asynchronous flash read, PSRAM read or PSRAM write operations, addresses arelatched on the rising edge of ADV#, or are continuously flow-through when ADV# is keptasserted.

1

F[4:1]-CE# Input

CHIP ENABLE: Flash specific signal. Low-true input.

F[4:1]-CE# low selects the associated flash memory die. When asserted, flash internal controllogic, input buffers, decoders, and sense amplifiers are active. When deasserted, theassociated flash die is deselected, power is reduced to standby levels, data and WAIT outputsare placed in high-Z state.

• LVQ devices: F1-CE# selects the first code die segment in flash die #1. F2-CE# selectsthe first data die segment in flash die #2 or the second code die segment in flash die #2.F3-CE# selects the second code or data segment in flash die #3. (There is no flash die#4). Refer to Table 1 on page 12 for details.

• LVX devices: F1-CE# selects the code die segment in flash die #1. F2-CE# selects thefirst data die segment in flash die #2 or the second code die segment in flash die #2. F3-CE# selects the second code or first data die segment in flash die #3. F4-CE# selects thesecond data die segment in flash die #4. Refer to Table 1 on page 12 for details.

• Any unused F-CE# should be pull high to F-VCCQ through a 10K-ohm resistor for futuredesign flexibility.

2

CLK,

F-CLKInput

CLOCK: Synchronizes the synchronous flash or RAM dies with the memory bus clock insynchronous read or write mode and increments the internal address generator.

During synchronous flash read operations, addresses are latched on the next valid CLK edgewith ADV# low.

• CLK is used only within the LVQ device family for the flash device.

• F-CLK is used only within the LVX device family for the flash device.

2

Datasheet 23

1024-Mbit LV Family

OE#,

F[2:1]-OE#Input

OUTPUT ENABLE: Low-true input.

F[2:1]-OE# low enables the flash output buffers. F[2:1]-OE# high disables the flash outputbuffers, and places the selected flash outputs and WAIT in High-Z.

• For LVQ devices, F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputsof flash die #2 and flash die #3. F2-OE# is available on stacked combinations with two orthree flash dies, and is an RFU on stacked combinations with only one flash die.

• For LVX devices, OE# is a global signal.

F-RST# InputRESET: Low-true input.

F-RST# low disables flash operations. F-RST# high enables flash operation. Exit from resetplaces all flash dies in asynchronous read array mode and all blocks in a locked state.

WAIT Output

DEVICE WAIT: Selectable high-true or low-true output. (For stacked combinations withoutSynchronous PSRAM, WAIT is a flash specific input.)

During synchronous-burst reads (array or non-array), WAIT-asserted indicates invalid readdata. During asynchronous-page reads and writes, WAIT is deasserted. Wait is High-Zwhenever F-CE# or F-OE# / OE# is deasserted.

WE#.

F-WE#Input

WRITE ENABLE: Low-true input.

• For LVQ devices, F-WE# low controls write operations to the selected flash die. Addressand data are latched on the rising edge of F-WE#.

• For LVX devices, WE# is a global signal

F-WP#,

F-WP[2:1]#Input

WRITE PROTECT: Low-true input.

F-WP# controls the lock-down protection mechanism of the selected flash die. When low, F-WP# enables the lock-down mechanism where locked down blocks cannot be unlocked withsoftware commands. When high, F-WP# disables the lock-down mechanism, allowing lockeddown blocks to be unlocked with software commands.

• For LVQ devices, F-WP# is shared between the code and data segment flash dies.

• For LVX devices, F-WP1# controls the code segment flash die #1, while F-WP2# controlssubsequent code or data segment flash dies.

F-VPP Power

ERASE/ PROGRAM VOLTAGE LEVEL: Valid F-VPP voltage on this ball enables flashprogram/erase operations.

Flash memory array contents cannot be altered when F-VPP < VPPLK. Erase / programoperations at invalid F-VPP voltage levels should not be attempted.

F-VCC Power

FLASH CORE VOLTAGE : Flash core source voltage.

Write operations to the flash array are inhibited when F-VCC ≤ VCCLKO. Operations at invalid F-VCC voltages should not be attempted.

• For LVQ devices, F1-VCC supplies power to the core logic of flash die #1; F2-VCCsupplies power to the core logic of flash die #2 and flash die #3. F2-VCC is available onstacked combinations with two or three flash dies, and is an RFU on stacked combinationswith only one flash die.

• For LVX devices, F-VCC supplies power to all flash die cores.

• Any unused F-VCC should be tied common to other F-VCC for future design flexibility.

VCCQ Power OUTPUT VOLTAGE: Supply power for the device input and output buffers.

VSS Power GROUND: Connect to system ground. Do not float any VSS connection.

DU - DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.

RFU - RESERVED for FUTURE USE: Reserved for future device functionality/ enhancements.Contact Intel regarding the use of balls designated RFU. 2

NOTES:1. All unused signals or RFUs should be held either to a static VIL or VIH for future design flexibility and migrations.2. Signals not described in Table 6, “Signal Descriptions1” are RAM specific and can be found in subsequent datasheets: 768-

Mbit LVQ Family with Asynchronous Static RAM, and 1024-Mbit LVX Family with Dynamic RAM (document number 253852and 253853 respectively).

Table 6. Signal Descriptions1 (Sheet 2 of 2)

Symbol Type Name and Function Notes

24 Datasheet

1024-Mbit LV Family

5.0 Maximum Ratings and Operating Conditions

5.1 Absolute Maximum Ratings

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.These are stress ratings only. Please refer to Table 8, “Operating Conditions” specifications.

Table 7. Absolute Maximum Ratings

Parameter Min Max Unit Notes

Case Temperature under bias –25 +85°C

Storage temperature –65 +125

Voltage on any signal (except F-VCC, F-VPP) –0.5 +3.8

V

1

F-VPP voltage –0.2 +10 1,2,3

F-VCC voltage –0.2 +2.5 1

VCCQ voltage (for 1.8 Volt option) –0.2 +2.5 1

VCCQ voltage (for 3.0 Volt option) -0.2 +3.8

Output short circuit current 100 mA 4

NOTES:1. Voltages shown are specified with respect to VSS. Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on

F-VCC, VCCQ, and F-VPP. During transitions, this level may undershoot to –2.0 V for periods < 20 ns. Maximum DC voltageon F-VCC is F-VCC +0.5 V, which, during transitions, may overshoot to F-VCC + 2.0 V for periods < 20 ns. Maximum DCvoltage on input/output signals and VCCQ is VCCQ +0.5 V, which, during transitions, may overshoot to VCCQ +2.0 V forperiods < 20 ns.

2. Maximum DC voltage on F-VPP may overshoot to +10.0 V for periods < 20 ns.3. Program/erase voltage is typically 1.7 V–1.95 V. Additionally, 9.0 V can be applied for a total of 80 hours maximum or to any

blocks for 1000 cycles maximum. 9.0 V program/erase may reduce block cycling.4. Output shorted for no more than one second. No more than one output shorted at a time.

Datasheet 25

1024-Mbit LV Family

5.2 Operating Conditions

Warning: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyondthe “Operating Conditions” may adversely affect device reliability.

Table 8. Operating Conditions

Symbol Parameter Min Max Unit

TC Operating Temperature –25 +85 °C

F-VCC F-VCC Supply Voltage 1.7 2.0

V

VCCQ 1.8 Volt I/O Supply Voltage option 1.7 2.0

VCCQ 3.0 Volt I/O Supply Voltage option 2.7 3.3

VPPL F-VPP Voltage Supply (Logic Level) 0.9 2.0

VPPH Factory word programming F-VPP 8.5 9.5

tPPH Maximum F-VPP Hours F-VPP = VPPH – 80 Hours

Block EraseCycles

Main and Parameter Blocks F-VPP = F-VCC 100,000 –

CyclesMain Blocks F-VPP = VPPH – 1000

Parameter Blocks F-VPP =VPPH – 2500

NOTE: Operating voltage are for flash + flash only stacked device. Please refer to document numbers 253852 and 253853 forflash + RAM stacked combinations.

26 Datasheet

1024-Mbit LV Family

6.0 Electrical Specifications

6.1 DC Current Characteristics

DC current characteristics shown in Table 9 are for the individual code and data segment flash dieswithin the LV SCSP device. The LV SCSP device total current is additive for each flash die.

Table 9. DC Current Characteristics (Sheet 1 of 2)

Sym ParameterVCCQ 1.7 V - 2.0 V 2.7 V - 3.3 V

Unit Test Conditions NotesTyp Max Typ Max

ILI Input Load Current – ±1 – ±2 µAF-VCC = F-VCC MAXVCCQ = VCCQ MAXVIN = VCCQ or VSS

1

ILO

OutputLeakageCurrent

DQ[15:0], WAIT – ±1 – ±10 µAF-VCC = F-VCC MAXVCCQ = VCCQ MAXVIN = VCCQ or VSS

ICCS

ICCDF-VCC Standby, Power Down

128 Mbit 25 70 30 75

µA

F-VCC = F-VCC MAXVCCQ = VCCQ MAXF-CE# = VCCQF-RST# = VCCQ (for ICCS)F-RST# = GND (for ICCD)F-WP# = VIH

1,2256 Mbit 50 110 55 115

ICCAPS APS

128 Mbit 25 70 30 75

µA

F-VCC = F-VCC MAXVCCQ = VCCQ MAXF-CE# = VSSQF-RST# = VCCQ

All inputs are at rail to rail (VCCQor VSSQ).

1,2256 Mbit 50 110 55 115

ICCR

AverageF-VCCReadCurrent

Asynchronous Single-Wordf = 5MHz (1 CLK) 13 15 14 16 mA

F-VCC = F-VCCMAX

F-CE# = VIL

F-OE# = VIH

Inputs: VIL orVIH

1

Page-Mode Readf = 13 MHz (5 CLK) 8 9 9 10 mA 4-Word Read

Synchronous Burst Readf = 40MHz, LC = 3

12 16 13 17 mA Burst length=4


16 20 17 21 mA Burstlength=16

20 25 21 26 mA Burst length =Continuous

Synchronous Burst Read

• f=54MHz, LC=4, 1.8V I/O

• f=52MHz, LC=4, 3.0V I/O



21 25 22 26 mA Burstlength=16

22 27 23 28 mA Burst Length =Continuous

ICCW,ICCE

F-VCC Program Current,

F-VCC Erase Current

35 50 36 51 mA F-VPP = VPPL, program/erase inprogress

1,3,4,7

25 32 26 33 mA F-VPP = VPPH, program/erase inprogress

1,3,5,7

Datasheet 27

1024-Mbit LV Family

6.2 DC Voltage Characteristics

ICCWS,

ICCES

F-VCC Program SuspendCurrent,

F-VCC Erase Suspend Current

128 Mbit 25 70 30 75µA F-CE# = VCCQ; suspend in

progress 1,6,3256 Mbit 50 110 55 115

IPPS,

IPPWS,

IPPES

F-VPP Standby Current,

F-VPP Program Suspend Current,

F-VPP Erase Suspend Current

0.2 5 0.2 5 µA F-VPP = F-VPPL, suspend inprogress 1,3

IPPR F-VPP Read 2 15 2 15 µA F-VPP ≤ F-VCC

1,3IPPW F-VPP Program Current

0.05 0.10 0.05 0.10

mA

F-VPP = VPPL, program inprogress

8 22 8 22 F-VPP = VPPH, program inprogress

IPPE F-VPP Erase Current0.05 0.10 0.05 0.10

mAF-VPP = VPPL, erase in progress

8 22 8 22 F-VPP = VPPH, erase in progress

NOTES:1. All currents are RMS unless noted. Typical values at typical F-VCC, TC = +25 °C.2. ICCS is the average current measured over any 5 ms time interval 5 µs after F-CE# is deasserted.3. Sampled, not 100% tested.4. F-VCC read + program current is the sum of F-VCC read and F-VCC program currents.5. F-VCC read + erase current is the sum of F-VCC read and F-VCC erase currents.6. ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR.7. ICCW, ICCE measured over typical or Max times specified in Section 7.5, “Program and Erase Characteristics” on page 41.

Table 10. DC Voltage Characteristics


Unit Test Condition NotesMin Max Min Max

VIL Input Low Voltage 0 0.4 0 0.4 V 1

VIH Input High Voltage VCCQ–0.4 VCCQ

VCCQ–0.4 VCCQ V

VOL Output Low Voltage – 0.1 – 0.1 VF-VCC = F-VCCMINVCCQ = VCCQMINIOH = 100 µA

VOH Output High VoltageVCCQ

–0.1–

VCCQ

–0.1– V

F-VCC = F-VCCMINVCCQ = VCCQMINIOH = –100 µA

VPPLK F-VPP Lock-Out Voltage – 0.4 – 0.4 V 2

VLKO F-VCC Lock Voltage 1.0 – 1.0 – V

VLKOQ VCCQ Lock Voltage 0.9 – 0.9 – V

NOTES:1. VIL can undershoot to –0.4 V and VIH can overshoot to VCCQ + 0.4 V for durations of 20 ns or less.2. F-VPP < VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.

Table 9. DC Current Characteristics (Sheet 2 of 2)


Unit Test Conditions NotesTyp Max Typ Max

28 Datasheet

1024-Mbit LV Family

7.0 AC Characteristics

7.1 AC Test Conditions

NOTE: AC test inputs are driven at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Inputrise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at F-VCC = F-VCC MIN.

NOTES:1. See the following table for component values.2. Test configuration component value for worst case speed conditions.3. CL includes jig capacitance.

Figure 10. AC Input/Output Reference Waveform

Figure 11. Transient Equivalent Testing Load Circuit

IO REF WMF

Input VCCQ/2 VCCQ/2 Output

VCCQ

0V

Test Points

I/OOutput

Z0 = 50 Ohms

CL = 30pF50Ohms

VCC/2 = VCCQ/2

Table 11. Device Test Loading Specification for worst case speed conditions

Test Configuration CL (pF)

1.7 V Standard Test 30

Figure 12. Clock Input AC Waveform

CLK [C]VIH

VIL

R203R202

R201

Datasheet 29

1024-Mbit LV Family

7.2 Capacitance

7.3 AC Read Specifications

Table 13 and Table 14 show AC read specifications for each code segment and data segment flashdie, respectively.

Table 12. Individual Flash Die Capacitance

Symbol Parameter Typ Max Unit Condition Notes

CIN Input Capacitance 6 10 pF VIN = 0.0 V 1,2,3,4

COUT Output Capacitance 8 12 pF VOUT = 0.0 V 1,3,4

CL Input Capacitance 10 12 pF VIN = 0.0 V 1,3,4

NOTES:1. TC = +25 °C, f = 1 MHz.2. CIN MAX = 8 pF for 128 Mbit Flash Density.3. Capacitance value is for individual flash die.4. Sampled, not 100% tested.

Table 13. AC Read Specifications (Code Segment Flash) (Sheet 1 of 2)

Num Symbol Parameter1

F-VCC 1.7 V - 2.0 V 1.8 V - 2.0 V 1.7 V - 2.0 V 1.8 V - 2.0 V

Unit NotesVCCQ 1.7 V - 2.0 V 1.8 V - 2.0 V 2.7 V - 3.3 V 2.7 V - 3.3 V

Min Max Min Max Min Max Min Max

Asynchronous Specifications

R1 tAVAV Read cycle time 88 – 85 – 88 – 85 –

ns

1R2 tAVQV Address to output valid – 88 – 85 – 88 – 85

R3 tELQV F-CE# low to output valid – 88 – 85 – 88 – 85

R4 tGLQV F-OE# low to output valid – 20 – 20 – 25 – 25 1,2

R5 tPHQV F-RST# high to output valid – 150 – 150 – 150 – 150 1

R6 tELQX F-CE# low to output in Low-Z 0 – 0 – 0 – 0 – 1,3

R7 tGLQX F-OE# low to output in Low-Z 0 – 0 – 0 – 0 – 1,2,3

R8 tEHQZ F-CE# high to output in high-Z – 17 – 17 – 24 – 24

1,3R9 tGHQZ F-OE# high to output in high-Z – 17 – 17 – 24 – 24

R10 tOHOutput hold from first occurringaddress, F-CE#, or F-OE# change 0 – 0 – 0 – 0 –

R11 tEHEL F-CE# pulse width high 14 – 14 – 20 – 20 –1

R12 tELTV F-CE# low to WAIT valid – 14 – 14 – 16 – 16

R13 tEHTZ F-CE# high to WAIT high-Z – 14 – 14 – 20 – 17

1,3R15 tGLTV F-OE# low to WAIT valid – 14 – 14 – – – 17

R16 tGLTX F-OE# low to WAIT in low-Z 0 – 0 – 0 – 0 –

R17 tGHTZ F-OE# high to WAIT in high-Z – 17 – 17 – 20 – 20

30 Datasheet

1024-Mbit LV Family

Latching Specifications

R101 tAVVH Address setup to ADV# high 7 – 7 – 10 – 10 –

ns

1

R102 tELVH F-CE# low to ADV# high 10 – 10 – 10 – 10 –

R103 tVLQV ADV# low to output valid – 88 – 85 – 88 – 85

R104 tVLVH ADV# pulse width low 7 – 7 – 10 – 10 –

R105 tVHVL ADV# pulse width high 7 – 7 – 10 – 10 –

R106 tVHAX Address hold from ADV# high 7 – 7 – 9 – 9 – 1,4

R108 tAPA Page address access – 25 – 25 – 25 – 25 1

R111 tPHVH F-RST# high to ADV# high 30 – 30 – 30 – 30 –

Clock Specifications

R200 fCLK CLK frequency – 54 – 54 – 52 – 52 MHz

1,3

R201 tCLK CLK period 18.5 – 18.5 – 19.2 – 19.2 –

nsR202 tCH/CL CLK high/low time 3.5 – 3.5 – 9 – 9 –

R203 tFCLK/RCLK

CLK fall/rise time – 3 – 3 – 3 – 3

Synchronous Specifications

R301 tAVCH/L Address setup to CLK 7 – 7 – 9 – 9 –

ns

1

R302 tVLCH/L ADV# low setup to CLK 7 – 7 – 9 – 9 –

R303 tELCH/L F-CE# low setup to CLK 7 – 7 – 9 – 9 –

R304 tCHQV /tCLQV

CLK to output valid – 14 – 14 – 17 – 17

R305 tCHQX Output hold from CLK 3 – 3 – 3 – 3 – 1,5

R306 tCHAX Address hold from CLK 7 – 7 – 10 – 10 – 1,4,5

R307 tCHTV CLK to WAIT valid – 14 – 14 – 17 – 17 1,5

R311 tCHVL CLK Valid to ADV# Setup 0 – 0 – 0 – 0 – 1

R312 tCHTX WAIT Hold from CLK 3 – 3 – 3 – 3 – 1,5

NOTES:1. See Figure 10, “AC Input/Output Reference Waveform” on page 29 for timing measurements and maximum allowable input

slew rate.2. F-OE# may be delayed by up to tELQV – tGLQV after F-CE#’s falling edge without impact to tELQV.3. Sampled, not 100% tested.4. Address hold in synchronous-burst mode read is tCHAX or tVHAX, whichever timing specification is satisfied first.5. Applies only to subsequent synchronous reads.

Table 13. AC Read Specifications (Code Segment Flash) (Sheet 2 of 2)

Datasheet 31

1024-Mbit LV Family

Table 14. AC Read Specifications (Data Segment Flash)

Num Symbol Parameter1VCCQ 1.7 V & 3.0 V Unit Notes

Min Max

Asynchronous Specifications

R1 tAVAV Read cycle time 170 –

ns

1R2 tAVQV Address to output valid – 170

R3 tFLQV F-CE# low to output valid – 170

R4 tGLQV F-OE# low to output valid – 30 1,2

R5 tPHQV F-RST# high to output valid – 170 1

R6 tFLQX F-CE# low to output in low-Z 0 – 1,3

R7 tGLQX F-OE# low to output in low-Z 0 – 1,2,3

R8 tFHQZ F-CE# high to output in high-Z – 27

1,3R9 tGHQZ F-OE# high to output in high-Z – 24

R10 tOH Output hold from first occurring address, F-CE#, or F-OE# change 0 –

R11 tEHEL F-CE# pulse width high 20 – 1

R12 tELTV F-CE# low to WAIT valid – 19

R13 tEHTZ F-CE# high to WAIT high-Z – 23

R15 tGLTV F-OE# low to WAIT high-Z – 23

R16 tGLTX F-OE# low to WAIT in low-Z 0 –

R17 tGHTZ F-OE# high to WAIT in high-Z – 27

Latching Specifications

R101 tAVVH Address setup to ADV# high 18 –

ns 1

R102 tELVH F-CE# low to ADV# high 13 –

R103 tVLQV ADV# low to output valid – 170

R104 tVLVH ADV# pulse width low 13 –

R105 tVHVL ADV# pulse width high 13 –

R106 tVHAX Address hold from ADV# high 12 –

R108 tAPA Page address access – 55

NOTES:1. See Figure 10, “AC Input/Output Reference Waveform” on page 29 for timing measurements and maximum allowable

input slew rate.2. F-OE# may be delayed by up to tELQV – tGLQV after F-CE#’s falling edge without impact to tELQV.3. Sampled, not 100% tested.

32 Datasheet

1024-Mbit LV Family

NOTE: WAIT shown configured for low-true operation.


Figure 13. Asynchronous Single-Word Read with ADV# Low

R5

R7R6

R17R15

R9R4

R8R3

R1R2

R1

Address [A]

ADV# [V]

F-CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

F-RST# [P]

Figure 14. Asynchronous Single-Word Read with ADV# Latch

R10R7

R6

R17R15

R9R4

R8R3

R106R101

R105R105

R2R1

Address [A]

A[1:0][A]

ADV# [V]

F-CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

Datasheet 33

1024-Mbit LV Family


NOTES:1. WAIT is driven per F-OE# assertion during synchronous array or non-array read, and can be configured to assert either during

or one data cycle before valid data.2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by F-CE#

deassertion after the first word in the burst.

Figure 15. Asynchronous Page-Mode Read Timing

R108R108R108 R13R7

R6

R12

R9R4

R8R3

R106R101

R105R105

R10R10R10R10

R1R1R2

A[Max:2] [A]

A[1:0]

ADV# [V]

F-CE# [E]

OE# [G]

WAIT [T]

DATA [D/Q]

Figure 16. Synchronous Single-Word Array or Non-Array Read Timing (Code Segment Only)

Latency Count

R305R304R4

R13R307R12

R9R7

R8

R303R102

R3

R104

R106R101

R104R105R105

R2

R306R301

CLK [C]

Address [A]

ADV# [V]

F-CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

34 Datasheet

1024-Mbit LV Family

.

NOTES:1. EOWL = End of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not

4-word boundary aligned.2. WAIT asserted (RCR.10 = 0) during synchronous array read, and can be configured to assert either during or one data cycle

before valid data.

NOTES:1. Section 16.2, “Latency Count Bit - RCR[13:11]” on page 73 describes how to insert clock cycles during the initial access.2. WAIT asserted (RCR.10 = 0) during synchronous array read, and can be configured to assert either during or one data cycle

before valid data.

Figure 17. WAIT EOWL Timing (Code Segment Only)

Figure 18. Synchronous Burst-Mode Four-Word Read Timing (Code Segment Only)

R305R305R305R305

R304R4

R7

R307R15

R303R102

R3

R106R105R105

R101R2

R304R304R304R306R302R301

CLK [C]

Address [A]

ADV# [V]

F-CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

A

R10R304

R305

R304R4

R7

R13R307R12

R9

R8

R303

R3

R106R102

R105R105

R101R2

R306R302R301

CLK [C]

Address [A]

ADV# [V]

F-CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

Datasheet 35

1024-Mbit LV Family

NOTE: CLK can be stopped at either a static high or low state.

Figure 19. Burst Suspend Timing (Code Segment Only)

Note 1

Q0 Q1 Q1 Q2

R304R304R7

R6

R13R12

R9R4R9R4

R8R3

R106R101

R105R105

R1R1R2

R305R305R305R304

Note 1 D ring B rst S spend Clock signal can be held high or lo

CLK

Address [A]

ADV# [V]

F-CE# [E]

OE# [G]

WAIT [T]

WE# [W]

DATA [D/Q]

36 Datasheet

1024-Mbit LV Family

7.4 AC Write Specifications

Table 15 shows the write timing specifications for each code and data segment flash die.

Table 15. AC Write Specifications

Number Symbol Parameter Min Max Unit Notes

W1 tPHWL F-RST# high recovery to F-WE# low 150 –

ns

1,2,3,12

W2 tELWL F-CE# setup to F-WE# low 0 – 1,2,3

W3 tWLWH F-WE# write pulse width low 50 – 1,2,4

W4 tDVWH Data setup to F-WE# high 50 –

1,2

W5 tAVWH Address setup to F-WE# high 50 –

W6 tWHEH F-CE# hold from F-WE# high 0 –

W7 tWHDX Data hold from F-WE# high 0 –

W8 tWHAX Address hold from F-WE# high 0 –

W9 tWHWL F-WE# pulse width high 20 – 1,2,5

W10 tVPWH F-VPP setup to F-WE# high 200 –

1,2,3,7W11 tQVVL F-VPP hold from Status read 0 –

W12 tQVBL F-WP# hold from Status read 0 –

W13 tBHWH F-WP# setup to F-WE# high 200 –

W14 tWHGL F-WE# high to F-OE# low 0 – 1,2,9

W16 tWHQV F-WE# high to read valid tAVQV+35 – 1,2,3,6,10

Write to Asynchronous Read Specifications

W18 tWHAV F-WE# high to Address valid 0 – ns 1,2,3,6,8

Write to Synchronous Read Specifications

W19 tWHCH/L F-WE# high to Clock valid 19 – ns1,2,3,6,10

W20 tWHVH F-WE# high to ADV# high 19 –

W21 tVHWL ADV# high to F-WE# low – 20 ns1,2,3,11

W22 tCHWL Clock high to F-WE# low – 20 ns

NOTES:1. Write timing characteristics during erase suspend are the same as write-only operations.2. A write operation can be terminated with either F-CE# or F-WE#.3. Sampled, not 100% tested.4. Write pulse width low (tWLWH or tELEH) is defined from F-CE# or F-WE# low (whichever occurs last) to F-CE# or F-WE#

high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.5. Write pulse width high (tWHWL or tEHEL) is defined from F-CE# or F-WE# high (whichever occurs first) to F-CE# or F-

WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).6. tWHVH or tWHCH/L must be met when transition from a write cycle to a synchronous burst read.7. F-VPP and F-WP# should be at a valid level until erase or program success is determined.8. This specification is only applicable when transitional from a write cycle to an asynchronous read. See spec W19 and

W20 for synchronous read.9. When issuing a Read Status operation following a program or erase write cycle, W14 = 20 ns.10.Add 10 ns if the write operation results in a flash RCR or block lock status change, add 10ns for the subsequent read

cycle to reflect this change.11.These specs are required only when the device is in a synchronous mode and clock is active during address setup

phase.12.For Data segment flash die, W1MIN = 170 ns.

Datasheet 37

1024-Mbit LV Family

NOTE: Control signals (WE#, OE#, and WAIT) are for flash access.


Figure 20. Write to Write Timing

W1

W7W4W7W4

W3W9 W3W9W3W3

W6W2W6W2

W8W8 W5W5

Address [A]

F-CE# [E]

WE# [W]

OE# [G]

WAIT [T]

Data [D/Q]

F-RST# [P]

Figure 21. Asynchronous Read to Write Timing

Q D

R5

W7W4R10

R7R6

R17R15

W6W3W3W2

R9R4

R8R3

W8W5R1

R2R1

Address [A]

F-CE# [E]

OE# [G]

WE# [W]

WAIT [T]

Data [D/Q]

F-RST# [P]

38 Datasheet

1024-Mbit LV Family


NOTES:1. WAIT shown asserted (RCR.10 = 0) during write operation.2. Control signals (WE#, OE#, and WAIT) are for flash access.

Figure 22. Write to Asynchronous Read Timing

D Q

W1

R9R8

R4

R3R2

W7W4

R17R15

W14

W18W3W3

R10W6W2

R1R1W8W5

Address [A]

ADV# [V]

F-CE# [E]

WE# [W]

OE# [G]

WAIT [T]

Data [D/Q]

F-RST# [P]

Figure 23. Synchronous Read to Write Timing

Q D D

W7R13

R305R304

R7

R307R12

W15W9

W19W8

W9W3W3W2

R8R4

W6R11R11

R303

R3

W20R104R104R106

R102R105R105

W18W5

R101R2

R306R302R301

CLK [C]

Address [A]

ADV# [V]

F-CE# [E]

OE# [G]

WE# [W]

WAIT [T]

Data [D/Q]

Datasheet 39

1024-Mbit LV Family

NOTES:1. WAIT shown asserted (RCR.10 = 0) during write operation.2. Control signals (WE#, OE#, and WAIT) are for flash access.

Figure 24. Write to Synchronous Read Timing

D Q Q

W1

R304R305R304

R3W7

W4

R307R12

R4

W18W3W3

R11R303

R11W6

W2

R104R106

R104

R306W8W5

R302R301

R2

CLK

Address [A]

ADV# [V]

F-CE# [E]

WE# [W]

OE# [G]

WAIT [T]

Data [D/Q]

F-RST# [P]

40 Datasheet

1024-Mbit LV Family

7.5 Program and Erase Characteristics

Table 16 shows the program and erase timings for each code and data segment flash die.

Table 16. Program and Erase Timing

Number Symbol ParameterVPPL VPPH

Unit NotesMin Typ Max Min Typ Max

Word Programming

W200 tPROG/WProgramTime

Single word – 90 180 – 85 170µs 1

Single cell – 30 60 – 30 60

Write-Buffer Programming

W200 tPROG/W ProgramTime

Single word – 90 180 – 85 170µs 1

W201 tPROG/PB One Buffer (32-Words) – 440 880 – 340 680

Buffered EFP

W400 tBufferedEFP/W

Program

Single word N/A N/A N/A N/A 10 N/A

µs

1,2

W401 tBufferedEFP/Setup

Buffered EFP Setup N/A N/A N/A 5 N/A N/A 1

Erasing and Suspending

W500 tERS/PBErase Time

16-Kword Parameter – 0.4 2.5 – 0.4 2.5s

1W501 tERS/MB 64-Kword Main – 1.2 4 – 1.0 4

W600 tSUSP/P SuspendLatency

Program suspend – 20 25 – 20 25µs

W601 tSUSP/E Erase suspend – 20 25 – 20 25

NOTES:1. Typical values measured at TC = +25 °C and nominal voltages. Performance numbers are valid for all speed versions.

Excludes system overhead. Sampled, but not 100% tested.2. Averaged over each flash die.

Datasheet 41

1024-Mbit LV Family

8.0 Power and Reset Specifications

8.1 Power-Up and Down

Power supply sequencing is not required if F-VCC, VCCQ, and F-VPP are connected to the samesupply. If VCCQ and/or F-VPP are not connected to the F-VCC supply, then F-VCC should rampup to F-VCC MIN before VCCQ and F-VPP. Inputs should not be driven on the DQ[15:0] beforesupply voltage ramps F-VCC MIN.

Power supply transitions should only occur when F-RST# is low. This protects the device fromaccidental programming or erasure during power transitions.

8.2 Reset

Asserting F-RST# during a system reset is important with automated program/erase devicesbecause systems typically expect to read from flash memory when coming out of reset. If a CPUreset occurs without a flash memory reset, proper CPU initialization may not occur. This is becausethe flash memory may be providing status information, instead of array data as expected. ConnectF-RST# to the same low-true reset signal used for CPU initialization.

Also, because the device is disabled when F-RST# is asserted, it ignores its control inputs duringpower-up/down. Invalid bus conditions are masked, providing a level of memory protection.System designers should guard against spurious writes when F-VCC ≥ VCCLKO. Because both F-WE# and F-CE# must be asserted for a write operation, deasserting either signal inhibits writes tothe device.

The Command User Interface (CUI) architecture provides additional protection because alterationof memory contents can only occur after successful completion of a two-step command sequence(see Section 9.2, “Flash Device Commands” on page 47 and Section 9.3, “Command Definitions”on page 49).

Note: Asserting F-RST# resets all segments of the LV SCSP device.

Table 17. Reset Timing

Number Symbol Parameter Min Max Unit Notes

P1 tPLPH F-RST# pulse width low 100 – ns 1,2,3,4

P2 tPLRH

F-RST# low to device reset during erase – 25

µs1,3,4,7

F-RST# low to device reset during program – 25

P3 tVCCPH F-VCC Power valid to F-RST# deasserted (high) 60 – 1,4,5,6

NOTES:1. These specifications are valid for all device versions (packages and speeds).2. The device may reset if tPLPH < tPLPH MIN, but this is not guaranteed.3. Not applicable if F-RST# is tied to F-VCC.4. Sampled, but not 100% tested.5. If F-RST# is tied to the F-VCC supply, device will not be ready until tVCCPH after F-VCC ≥ VCC MIN.6. If F-RST# is tied to any supply/signal with VCCQ voltage levels, the F-RST# input voltage must not exceed F-VCC until F-VCC

≥ VCC MIN.7. Reset completes within tPLPH if F-RST# is asserted while no erase or program operation is executing.

42 Datasheet

1024-Mbit LV Family

8.3 Power Supply Decoupling

The LV SCSP memory device requires careful power supply decoupling. Some basic power supplycurrent considerations include the standby and active current levels and the transient peaks that areproduced when F-CE# and F-OE# are asserted and deasserted.

When a device is accessed, many internal conditions change. Circuits within the device enablecharge-pumps, and internal logic states change at high speed. All of these internal activitiesproduce transient signals. Transient current magnitudes depend on the device outputs’ capacitiveand inductive loading. Two-line control and correct decoupling capacitor selection suppresstransient voltage peaks.

The LV SCSP device draws power from F-VCC, F-VPP, and VCCQ, each power connectionshould have a 0.1 µF ceramic coupling capacitor. High-frequency, inherently low-inductancecapacitors should be placed as close as possible to package leads.

Additionally, for every eight dies used in the system, a 4.7 µF electrolytic capacitor should beplaced between power and ground close to the devices. The bulk capacitor is meant to overcomevoltage droop caused by PCB trace inductance.

8.4 Automatic Power Saving (APS)

Automatic Power Saving (APS) provides low power operation during a read’s active state. ICCAPSis the average current measured over any 5 ms time interval, 5 µs after F-CE# is deasserted. DuringAPS, average LV SCSP device current is measured across each segment flash die over the sametime interval of 5 µs after the following events:

• There is no internal sense activity.

• F-CE# is asserted.

• The address lines are quiescent, and at VIL or VIH.

• F-OE# may be driven during APS.

Figure 25. Reset Operation Waveforms

VCC

F-RST# [P] VIH

VIL

F-RST# [P] VIH

VIL

F-RST# [P] VIH

VIL

P2

P3

P2

P1

R5

R5

R5

0 V

AbortComplete

AbortComplete

VCC

(A) Reset during read mode

(B) Reset during program orblock erase P1 < P2

(C) Reset during program orblock erase P1 > P2

(D) VCC Power-up toF-RST# high

Datasheet 43

1024-Mbit LV Family

9.0 Design Guide: Operation Overview

This section provides an overview of device operations. The system CPU provides control of all in-system read, program, and erase operations of the device via the system bus.

Flash device commands are written to the Command User Interface (CUI) to control all flashmemory device operations. The CUI does not occupy an addressable memory location; it is themechanism through which the flash device is controlled.

Each flash die within the 1024-Mbit LV family shares basic asynchronous read and writeoperations unless otherwise specified.

9.1 Bus Operations

With F-CE# low and F-RST# high, the LV SCSP flash dies are enabled for normal operations. Theflash internally decodes upper address inputs to determine the accessed partition or block.

In asynchronous mode, addresses are latched when ADV# transition from VIL to VIH, orcontinuously flows through if ADV# is held low.

Code segment flash die, synchronous-burst mode reads, addresses are latched by the rising edge ofADV# or the next valid CLK edge when ADV# is low.

Table 18, “Example of Flash Code and Data Segment Bus Operations” summarizes the busoperations and voltage levels that must be applied to individual flash die in each mode.

44 Datasheet

1024-Mbit LV Family

9.1.1 Reads

F-OE# controls data-outputs. To perform a read operation, F-RST# and F-WE# must be deassertedwhile F-CE# and F-OE# are asserted. When F-CE# and F-OE# are asserted, the addressed flashmemory data is driven onto the memory bus. See Section 10.0, “Read Operations” on page 51 fordetails on read commands, and Section 16.0, “Configuration Operations” on page 71 for details onconfiguring code and data segment flash read modes. See Section 7.0, “AC Characteristics” onpage 29 for signal-timing details.

9.1.2 Writes

F-WE# controls data-inputs. To perform a write operation, F-RST# and F-OE# are deassertedwhile F-CE# and F-WE# are asserted. All write operations are asynchronous. During a writeoperation, addresses are latched on the rising edge of ADV#, F-WE#, or F-CE#, whichever occursfirst. Data are latched on the rising edge of F-WE# or F-CE#, whichever occurs first. In the case oftwo-cycle write operations, the address are latched on the second cycle, and the operation applies

Table 18. Example of Flash Code and Data Segment Bus Operations

Dev

ice

Mode

F-R

ST

#

F1-

CE

#

F2-

CE

#

F-O

E#

F-W

E#

AD

V#

F-VPP WAIT DQ[15:0] Notes

Fla

shD

ie#1

(co

de)

En

able

d

Sync Array Read H L H L H L X Driven Flash Die #1code outputs 1,2,3,4

Sync Non-Array Read H L H L H L X Driven Flash Die #1code outputs 1,2,3,4

Async Read H L H L H L X Deasserted Flash Die #1code outputs 1,2,3,4

Write H L H H L L F-VPP1 orF-VPP2

High-Z Flash Die #1code inputs 2,3,4,5

Output Disable H L H H H X X High-Z Flash1 High-Z 3

Standby H H H X X X X High-Z Flash1 High-Z 3

Reset L X X X X X X High-Z Flash1 High-Z 3

Fla

shD

ie#2

(dat

a)E

nab

led

Async Read H H L L H L X Deasserted Flash Die #2 dataoutputs 2,3,4,6

Write H H L H L L F-VPP1 orF-VPP2

High-Z Flash Die #2 datainputs 2,3,4,5

Output Disable H H L H H X X High-Z Flash2 High-Z 3

Standby H H H X X X X High-Z Flash2 High-Z 3

Reset L X X X X X X High-Z Flash2 High-Z 3

NOTES:1. WAIT is driven during sync burst read when F-CE# and F-OE# are asserted. WAIT is High-Z if F-CE# or F-OE# is

deasserted.2. For either flash dies, F-OE# and F-WE# should never be asserted simultaneously.3. L means VIL and H means VIH.while X can be VIL or VIH for inputs and F-VPP1, F-VPP2 or VPPLK for F-VPP.4. Flash CFI query and status register accesses use DQ[7:0] only. All other reads use DQ[15:0].5. Refer to Table 19, “Command Bus Cycles” on page 47 for valid DIN during flash writes.6. Data segment flash only operates in asynchronous mode, CLK is ignored and WAIT is deasserted.

Datasheet 45

1024-Mbit LV Family

to that address. Table 19, “Command Bus Cycles” on page 47 shows the bus cycle sequence foreach of the supported commands, while Table 20, “Command Codes and Definitions” on page 49describes each command. See Section 7.0, “AC Characteristics” on page 29 for signal-timingdetails.

Note: Write operations with invalid F-VCC and/or F-VPP voltages can produce spurious results andshould not be attempted.

9.1.3 Output Disable

When F-CE# or F-OE# is deasserted, flash outputs DQ[15:0] are disabled and placed in a High-Zstate.

9.1.4 Standby

When F-CE# is deasserted, the flash die is deselected and placed in standby, substantially reducingpower consumption. In standby, the data outputs are placed in High-Z, independent of the levelplaced on F-OE#. Standby current (ICCS) is the average current measured over any 5 ms timeinterval, 5 µs after F-CE# is deasserted (See Section 6.1, “DC Current Characteristics” on page 27for details).

When the flash device is deselected after a valid program or erase operation has started, the flashdie continues to consume active power until the program or erase operation is completed.

9.1.5 Reset

After initial power-up or reset, the LV SCSP flash dies defaults to an asynchronous Read Arraymode, and the Status Registers default to 0x80. All blocks are in locked state. All ReadConfiguration Register bits reverts to their default states. See Section 16.0, “ConfigurationOperations” on page 71 and Figure 27, “Block Locking State Diagram” on page 67 for details.

Asserting F-RST# places the output drivers in High-Z. When F-RST# is asserted, the flash dieshuts down the operation in progress, a process which takes a minimum amount of time (tPLRH) tocomplete. (See Section 8.2, “Reset” on page 42 for details.)

If F-RST# is asserted during a program or erase operation, the operation is terminated and thememory contents at the aborted location (for a program) or at the block location (for an erase) areno longer valid. Because the data may have been only partially written or erased, the memorycontent should be treated as invalid.

Upon return from reset, a minimum reset delay (tVCCH) is required before performing any initialread or write operations. When normal operation is restored, the user must reconfigure the WAITRead Configuration Register (RCR.10) bit of the data segment flash die to match the code segmentflash die WAIT (RCR.10) bit setting. This operation prevents bus contention that can resultbecause the WAIT signals are shared between code and data segment flash dies.

Note: It is important for the user to assert F-RST# when the system is reset. When the system comes outof reset, the system processor may attempt to read from the flash memory if it is the system bootdevice. If a processor reset occurs with no flash memory reset, improper processor initializationmay occur because the flash memory may be providing status information rather than array data. F-RST# should be controlled by the same low-true reset signal that resets the system processor ormemory controller

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1024-Mbit LV Family

9.2 Flash Device Commands

Flash device operations are initiated by writing specific flash commands to the Command UserInterface (CUI). See Table 20, “Command Codes and Definitions” on page 49. Flash operations areinitiated by writing specific flash commands to the CUI, as shown in Table 19. Program and Erasecommands modify flash array data.

Table 19. Command Bus Cycles (Sheet 1 of 2)

Oper Command BusCycles

First Bus Cycle Second Bus Cycle Third Bus Cycle

Oper Addr1 Data2 Oper Addr1 Data2 Oper Addr1 Data2

Rea

d

Read Array 1 Write PnA 0xFF – – – – – –

Read Device Identifier ≥ 2 Write PnA 0x90 Read PBA+IA ID – – –

CFI Query ≥ 2 Write PnA 0x98 Read PnA+QA QD – – –

Read Status Register 2 Write PnA 0x70 Read PnA SRD – – –

Clear Status Register 1 Write X 0x50 – – – – – –

Pro

gra

m(W

rite

)

Word Program 2 Write WA 0x40/0x10 Write WA WD – – –

Buffered Program3 ≥ 2 Write WA 0xE8 Write WA N - 1 Write WA 0xD0

Buffered EnhancedFactory Program(Buffered EFP)4

> 2 Write WA 0x80 Write WA 0xD0 – – –

Era

se Block Erase 2 Write BA 0x20 Write BA 0xD0 – – –

Su

spen

dan

dR

esu

me

Program/Erase Suspend 1 Write X 0xB0 – – – – – –

Program/Erase Resume 1 Write X 0xD0 – – – – – –

Blo

ckL

ock

ing

/U

nlo

ckin

g

Lock Block 2 Write BA 0x60 Write BA 0x01 – – –

Unlock Block 2 Write BA 0x60 Write BA 0xD0 – – –

Lock-down Block 2 Write BA 0x60 Write BA 0x2F – – –

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1024-Mbit LV Family

Pro

tect

ion

Reg

iste

r5

(Co

de

Seg

men

tO

nly

) Program Protection

Register52 Write PRA 0xC0 Write PRA PD – – –

Program Lock Register5 2 Write LRA 0xC0 Write LRA LRD – – –

Co

nfi

gu

rati

on

Program ConfigurationRegister 2 Write RCD 0x60 Write RCD 0x03 – – –

NOTES:1. First command cycle address should be the same as the operation’s target address.

PBA = Partition Base Address. (Note: Data segment flash access at any block address)PnA = Address within the Partition.(Note: Data segment flash access at any block address)IA = Identification code Address offset.QA = CFI Query Address offset.BA = Address within the block.WA = Word Address of memory location to be written.PRA = Protection Register Address.LRA = Lock Register Address.X = Any valid address within the flash.

2. ID = Identifier Data.QD = Query data on DQ[15:0].SRD = Status Register Data.WD = Word Data.N = Word count of data to be loaded into the buffer.PD = Protection Register Data.LRD = Lock Register Data.RCD = Read Configuration Register Data is presented on A[15:0]. A[MAX:16] bits must be zeros. See Section 21, “StatusRegister Description” on page 54.

3. The second cycle of the buffered Program command is the number of words count loaded into the buffer. This is followed byup to 32-words of data.Then a confirm command (0xD0) is issued, triggering the array program operation.

4. The confirm command (0xD0) is followed by the buffer data.5. Protection Register bits are only accessible with code segment flash. Attempts to program PR[16:0] will result in SR[4,1] error.

Table 19. Command Bus Cycles (Sheet 2 of 2)

Oper Command BusCycles

First Bus Cycle Second Bus Cycle Third Bus Cycle

Oper Addr1 Data2 Oper Addr1 Data2 Oper Addr1 Data2

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9.3 Command Definitions

Flash operations are selected by writing specific commands to the CUI. Valid commands acceptedby the CUI are described in Table 20, “Command Codes and Definitions”. All commands havebeen specified in the form of a byte, to be accepted on the lower byte of a 16-bit data bus. Theupper byte is ignored by the CUI. The Code segment flash dies are accessed by partition addresslocation, while Data segment flash dies are accessed by block address location.

Table 20. Command Codes and Definitions (Sheet 1 of 2)

Operation CommandCode Flash Die Mode Description

Read

0xFF Read Array Place the addressed partition or block in Read Array mode. Array data isoutput on DQ[15:0].

0x70 Read StatusRegister

Place the addressed partition or block in Read Status Register mode. Thepartition or block enter this mode after a program or erase command isissued. Status Register data are output on DQ[7:0].

0x90 Read DeviceIdentifier

Places the addressed partition or block in Read Device Identifier mode.Subsequent reads from addresses within the partition or block outputmanufacturer/device codes, Configuration Register data, Block Lock status,or Protection Register data on DQ[15:0].

0x98 Read CFI QueryPlace the addressed partition or block in Read CFI Query mode.Subsequent reads from the partition or block addresses output CommonFlash Interface (CFI) information on DQ[7:0].

0x50 Clear StatusRegister

The WSM can only set Status Register error bits. The Clear Status Registercommand is used to clear the Status Register error bits.

Program(Write)

0x40 Word ProgramSetup

First cycle of a two-cycle programming command; prepares the CUI for awrite operation. On the second write cycle, the address and data are latchedand the WSM executes the programming algorithm at the addressedlocation.

During program operations, the partition responds only to Read StatusRegister and Program Suspend commands. F-CE# or F-OE# must assertand deassert to update the Status Register in asynchronous read. The ReadArray command must be issued to read array data after programming hasfinished.

• For code segment flash, F-CE# or ADV# must assert and deassert toupdate the Status Register data for synchronous non-array read.

0x10 Alternate WordProgram Setup Equivalent to the Word Program Setup command, 0x40.

0xE8 Buffered ProgramSetup

First cycle of a two-cycle buffered program command; prepares the flash toreceive a variable number of bytes up to the buffer size of 32-Words.

The second cycle contains the number of bytes to be transferred.

0xD0 Buffered ProgramConfirm

The second cycle of a two-cycle buffered program command, confirm thecommand was issued after filling all data into the buffer. The confirmcommand instructs the WSM to perform its buffered program algorithm,writing the data from the buffer to the flash memory array.

0x80

BufferedEnhancedFactoryProgrammingSetup

First cycle of a two-cycle Buffered Enhanced Factory Programming(Buffered EFP) command; initiates Buffered EFP. The CUI then waits for theBuffered EFP Confirm command (0xD0) that initiates the Buffered EFPalgorithm.

All other commands are ignored when Buffered EFP mode begins.

0xD0 Buffered EFPConfirm

The second cycle of a two-cycle Buffered EFP command. The confirmcommand enable the CUI to latch the address and data, and prepares theflash for Buffered EFP mode.

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1024-Mbit LV Family

Erase

0x20 Block Erase Setup

First cycle of a two-cycle erase command; prepares the CUI for a block-erase operation. The WSM performs the erase algorithm on the blockaddressed by the Erase Confirm command. If the second command is notthe Erase Confirm (0xD0) command, the CUI sets Status Register bits SR[4]and SR[5], and place the addressed partition or block in status registermode.

0xD0 Block EraseConfirm

If the first command was Block Erase Setup (0x20), the CUI latches theaddress and data, and the WSM erases the addressed block. During block-erase operations, the partition or block responds only to Status Register andErase Suspend commands. F-CE# or F-OE# must assert and deassert toupdate the Status Register in asynchronous read.

• For code segment flash, F-CE# and ADV# must assert and deassert toupdate the Status Register data for synchronous non-array read.

Suspend andResume

0xB0 Program orErase Suspend

This command issued to any flash address initiates a suspend of thecurrently-executing program or block erase operation. The Status Registerindicates successful suspend operation by setting either SR[2] (programsuspended) or SR[6] (erase suspended), along with SR[7] (ready). TheWrite State Machine remains in the suspend mode regardless of controlsignal states (except for F-RST# asserted).

0xD0 Suspend Resume This command issued to any flash address resumes the suspendedprogram or block-erase operation.

BlockLocking/

Unlocking

0x60 Lock Block Setup

First cycle of a two-cycle lock block command; prepares the CUI for blocklock configuration changes. If the second command is not Block Lock(0x01), Block Unlock (0xD0), or Block Lock-Down (0x2F), the CUI setsStatus Register bits SR[4] and SR[5], indicating a command sequence error.

0x01 Lock Block If the previous command was Block Lock Setup (0x60), the addressed blockis locked.

0xD0 Unlock BlockIf the previous command was Block Lock Setup (0x60), the addressed blockis unlocked. If the addressed block is in a lock-down state, the Unlock Block(0xD0) command has no effect.

0x2F Lock-Down Block If the previous command was Block Lock Setup (0x60), the addressed blockis locked down.

ProtectionRegister1 0xC0

ProgramProtectionRegister Setup

First cycle of a two-cycle program protection register command; preparesthe code segment flash for a Protection Register or Lock Register programoperation. The second cycle latches the register address and data, andstarts the programming algorithm.

• F-CE# or F-OE# must assert and deassert to update the StatusRegister. The Read Array command must be issued to read array dataafter programming has finished.

Configuration

0x60ReadConfigurationRegister Setup

First cycle of a two-cycle Read Configuration Register command; preparesthe CUI for flash read configuration. If the set Read Configuration Registercommand (0x03) is not the second command, the CUI sets Status Registerbits SR[4] and SR[5], indicating a command sequence error.

0x03ReadConfigurationRegister

If the previous command was Read Configuration Register Setup (0x60),the CUI latches the address and writes A[15:0] to the Read ConfigurationRegister. Following a configured Read Configuration Register command,subsequent read operations access array data.

NOTE: Protection Register bits are only accessible with code segment flash. Attempts to program data segment flash PR[16:0]will result in SR[4,1] error.

Table 20. Command Codes and Definitions (Sheet 2 of 2)

Operation CommandCode Flash Die Mode Description

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1024-Mbit LV Family

10.0 Read Operations

The code segment supports two read modes: asynchronous page-mode read and synchronous burst-mode read. Asynchronous page-mode read is the default read mode after power-up or reset. TheRead Configuration Register bits must be configured to enable synchronous burst reads (SeeSection 16.0, “Configuration Operations” on page 71 for details). The data segment supports onlyasynchronous page-mode read. Only WAIT polarity RCR.10 must be set equal to the code segmentRCR.10 setting.

Each partition or block of the flash can be in any of four output states: Read Array, Read Status,Read Identifier, and Read CFI Query. Upon power-up or after a reset, all blocks within the flashsegments default to Read Array. To change a partition or block read state, the appropriate readcommand must be written to the selected flash (see Section 9.2, “Flash Device Commands” onpage 47 and Section 9.3, “Command Definitions” on page 49.)

10.1 Asynchronous Page-Mode Read

Following a device power-up or reset, asynchronous page-mode read is the flash default read modeand all blocks across all segments are set to Read Array. However, to perform array reads after anyother flash operation such as program, erase, CFI query, or Device ID operation, the Read Arraycommand must be issued in order to read from the flash memory array.

After a code segment flash synchronous burst-mode read operation, an asynchronous page-moderead can be performed only when Read Configuration Register bit RCR.15 is set. (See Section16.0, “Configuration Operations” on page 71).

To perform an asynchronous page-mode read, an address is driven onto A[MAX:MIN] and F-CE#and ADV# are asserted. ADV# is deasserted to latch the address, or it can be held low throughoutthe read cycle. CLK is ignored during asynchronous page-mode reads.

In asynchronous page-mode read, four data words are “sensed” simultaneously from the flashmemory array and loaded into an internal page buffer. The buffered word corresponding to theinitial address on A[MAX:MIN] is driven onto DQ[15:0] after the initial access delay. Address bitsA[MAX:MIN+2] select the 4-word group. Address bits A[MIN+1:MIN] determine which word ofthe 4-word group is output from the data buffer at any given time.

As long as the address bits A[MAX:MIN+2] do not change, the same buffered data can be readfrom the page-buffer multiple times and in any order. If A[MAX:MIN+2] address bits change atany time or if F-CE# is toggled, the flash will detect this and load four new data words into theinternal page buffer.

For designs that will only operate the code or data segment flash in asynchronous page-mode read,CLK should be tied to a valid VIH level, WAIT signal can be floated, and ADV# must be tied toground. Array data are driven onto DQ[15:0] after an initial access time tAVQV delay. (See Section7.0, “AC Characteristics” on page 29).

The code and data segments share the same WAIT pins. Validity of this pin depends on the selectedsegment and the command issued. WAIT is deasserted during asynchronous page-mode reads.

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1024-Mbit LV Family

10.2 Synchronous Burst-Mode Read (Code Segment)

A Synchronous Burst-Mode Read is code segment-only operation. Before a synchronous burst-mode read operation can be performed, appropriate Read Configuration Register bits (RCR[15:0])must be set for synchronous read. A synchronous burst-mode read can be performed for array andnon-array reads with configurable burst lengths of 4-word, 8-word, 16-word, and continuous word.

To perform a synchronous burst-mode read, an initial address is driven onto A[MAX:MIN] and F-CE# and ADV# are asserted. (Ensure that F-WE# and F-RST# are already deasserted).

There are two methods for latching the address: ADV# must be asserted then deasserted to latchthe address. Or, ADV# can remain asserted throughout the burst access, in which case the addressis latched on the next valid CLK edge while ADV# is asserted. A new burst read operation startsafter ADV# is asserted or F-CE# is asserted, whichever is last.

During synchronous array and non-array read modes, the first word is output from the data bufferon the next valid CLK edge after the initial access latency delay (see Section 16.2, “Latency CountBit - RCR[13:11]” on page 73). Subsequent data is output on valid CLK edges following a tCHQVdelay. Synchronous burst-mode reads can only step through the data once, and can do so only in asequential manner, starting from the address latched at the beginning of the burst cycle (see Section7.0, “AC Characteristics” on page 29 for timing details). However, for synchronous non-arrayreads, the same word data will be output on successive clock edges until the configured burstlength are read.

During synchronous burst-mode read operations, WAIT is driven with respect to F-OE# beingasserted. WAIT indicates invalid data when asserted, and valid data when deasserted after the setLatency Count delay.

10.3 Burst Suspend

The Burst Suspend feature of the flash can reduce or eliminate the initial access latency incurredwhen system software needs to suspend a burst sequence that is in progress in order to retrieve datafrom another non-flash device on the same system bus. The system processor can resume the burstsequence within one CLK cycle for maximum benefits in a non-cache systems.

Note: The Burst Suspend feature is used only with the code segment flash in the LVQ device family. LVXdevice family does not support Burst Suspend because F-OE# is a global control signal to allmemory dies within the 1024-Mbit LVX devices.

A burst access can be suspended during the initial access latency (before data is received) or afterdata is output. When a burst access is suspended, internal array sensing continues and anypreviously latched internal data are retained. A burst sequence can be suspended and resumedwithout limit as long as operating conditions are met.

Burst Suspend occurs when F-CE# is asserted, the current address has been latched (either risingedge of ADV# or valid CLK edge), F-OE# is deasserted, and CLK is halted (CLK = VIH or VIL).ADV# and all other flash signals needs to be maintained static. WAIT is in High-Z while F-OE# isdeasserted.

To resume the burst access, F-OE# is reasserted and CLK is restarted. The next valid CLK edgeresumes the burst sequence.

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Within the code segment flash, F-CE# or F-OE# gates WAIT signal. Therefore, during BurstSuspend, WAIT is placed in a high-Z state when F-CE# or F-OE# is deasserted. WAIT isdeasserted when F-OE# is re-asserted. See Figure 19, “Burst Suspend Timing (Code SegmentOnly)” on page 36.

10.4 Read Array Command (0xFF)

The Read Array command places the addressed partition or block in Read Array mode. Array datais output on DQ[15:0]. To perform a read operation, F-RST# and F-WE# must be deasserted whileF-CE# and F-OE# are asserted. When F-CE# and F-OE# are asserted, the addressed flash memorydata is driven onto the memory bus.

The following sections describe in detail how to read non-array read: Status Register, Register ID,and CFI register states. This section will also discuss simultaneous flash operations between the LVSCSP code and data segment.

10.5 Read Status Register Command (0x70)

This command is a non-array read command. The status of any code segment flash partition orblock is determined by reading the Status Register (SR) from the address of the target partition orblock. The status of a data segment flash is determined by reading the SR from any address withinthe flash die address range. To read the SR, issue the Read Status Register command within thedesired partition or block or address, and the SR data is output on DQ[7:0]. SR data is also madeavailable automatically following a Word Program, Block Erase, or Block Lock commandsequence. A Read from a partition or block or address after any of these command sequencesoutputs the flash SR status until another valid command is issued to the flash die partition or blockor address (e.g. Read Array command).

The SR is read in asynchronous page-mode or synchronous single word burst-mode. SR data isoutput on DQ[7:0], while 0x00 is output on DQ[15:8]. The falling edge of F-OE# or F-CE#(whichever occurs first) updates and latches the SR contents.

The SR[7] bit provides the status of each accessed flash die. The SR[0] bit indicates whether theaddressed location or some other partition or block (for code segment flash) is activelyprogramming or erasing. The SR[6:1] bits present status and error information about the program,erase, suspend, F-VPP, and block-locked operations.

Note: For code segment flash, the Read Status Register command does not affect the read state of otherpartitions. For data segment flash, a Read Status Register command sets the read state of the entireflash because it is a single partition die. To perform any other operation with the data segment flashafter a Read Status Register command, a Clear Status Register command must be issued.

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1024-Mbit LV Family

Table 21. Status Register Description

Status Register (SR) Default Value = 0x80

Die WriteStatus

EraseSuspend

Status

EraseStatus

ProgramStatus

F-VPPStatus

ProgramSuspend

Status

Block-LockedStatus

PartitionStatus

DWS ESS ES PS VPPS PSS BLS PWS

7 6 5 4 3 2 1 0

Bit Name Description

7 Die Write Status (DWS)0 = Die is busy; program or erase cycle in progress; SR[0] valid.

1 = Die is ready; SR[6:1] are valid.

6 Erase Suspend Status(ESS)

0 = Erase suspend not in effect.

1 = Erase suspend in effect.

5 Erase Status (ES)0 = Erase successful.

1 = Erase fail or program sequence error when set with SR[4,7].

4 Program Status (PS)0 = Program successful.

1 = Program fail or program sequence error when set with SR[5,7]

3 F-VPP Status (VPPS)0 = F-VPP within acceptable limits during program or eraseoperation.

1 = F-VPP < F-VPPLK during program or erase operation.

2 Program Suspend Status(PSS)

0 = Program suspend not in effect.

1 = Program suspend in effect.

1 Block-Locked Status(BLS)

0 = Block not locked during program or erase.

1 = Block locked during program or erase; operation aborted.

0 Partition Write Status(PWS)

0 = The current partition is busy or Buffered EFP prog/verify is done.

1 = Another partition is busy or Buffered EFP program is busy.

Note:

• See Table 22 for partition status interpretation details.

• See Table 23 for Buffered EFP status interpretation details.

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Table 22. Status Register bits DWS and PWS Description - Partition Status

Table 23. Status Register bits DWS and PWS Description - Buffered EFP Mode Status

Note: Always clear the SR to avoid SR ambiguity when issuing commands during Erase Suspend. Forexample if a command sequence error occurs during an erase-suspend state, the SR contains thecommand sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes,possible errors during the erase operation cannot be detected if the SR has not been cleared becauseit still contains the previous error status.

10.6 Clear Status Register Command (0x50)

This command is a non-array read command. The Clear Status Register command clears the StatusRegister (SR), leaving all partition or block read states unchanged. It functions independently of F-VPP. The Write State Machine (WSM) sets and clears SR[7, 6, 2, 0], but it sets bits SR[5:3, 1]without clearing them. The SR should be cleared before starting a command sequence to avoid anyambiguity. A device reset also clears the SR.

10.7 Read Flash Device Identifier Command (0x90)

This command is a non-array read command. The Read Flash Device Identifier Commandcommand instructs the addressed partition or block to output manufacturer ID code, die identifiercode, block-lock status, protection register (code segment only), or Read Configuration Registerdata when that partition or block addresses are read. See Section 19, “Command Bus Cycles” onpage 47 for details on issuing the Read Device Identifier command. Table 24, “Device IdentifierInformation” on page 56 and Table 25, “Device Identifier Code” on page 56 show the addressoffsets and data values for each flash die.

DWS(SR.7)

PWS(SR.0) Description

0 0 The addressed partition is performing a Program/Erase operation. No other partition is active.

0 1 A partition other than the one currently addressed is performing a Program/Erase operation.

1 0 No Program/Erase operation is in progress in any partition. Erase and Program suspend bits,SR[6, 2] indicate whether other partitions are suspended.

1 1 Reserved

NOTE: DWS and PWS only applies to the code segment flash die operations.

DWS(SR.7)

PWS(SR.0) Description

0 0 Buffer is available for loading of subsequent data during Buffered EFP operation.

0 1 Buffer is not available for loading. Buffered EFP currently being programmed.

1 0 Buffer is available for loading initial data for Buffered EFP operation.

1 1 Reserved

Note: DWS and PWS only applies to the code segment flash die operations.

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Table 24. Device Identifier Information

Item Address Data Notes

Manufacturer Code PBA + 0x00 0089h 1, 2

Die ID Code PBA + 0x01 ID (see Table 25, “DeviceIdentifier Code” on page 56) 1, 2

Block Lock Configuration:

BBA + 0x02

Lock Bit:

1, 2

• Block Is Unlocked D0 = 0b0

• Block Is Locked D0 = 0b1

• Block Is not Locked-Down D1 = 0b0

• Block Is Locked-Down D1 = 0b1

Read Configuration Register PBA + 0x05 Read Configuration RegisterData 1, 2

Lock Register 0 PBA + 0x80 Protection Register Lock Bits 1, 2

64-bit Factory-Programmed Protection Register PBA + 0x81–0x84 Factory Protection Register Data 1, 2, 3

64-bit User-Programmable Protection Register PBA + 0x85–0x88 User Protection Register Data 1, 2, 3

Lock Register 1 PBA + 0x89 Protection Register Lock Bits 1, 2, 3

128-bit User-Programmable Protection Registers PBA + 0x8A–0x109 User Protection Register Data 1, 2, 3

NOTES:1. PBA = Partition Base Address for code segment flash. Data segment flash PBA = 0x00.2. BBA = Block Base Address.3. Protection Register feature only applies to Code Segment flash dies.

Table 25. Device Identifier Code

Device Flash Dies Device ID (Hex) Parameter PartitionConfiguration

Code: 128-Mbit 880CTop

Code: 256-Mbit 880D

Code: 128-Mbit 880FBottom

Code: 256-Mbit 8810

Code: 128-Mbit 8812Top

Code: 256-Mbit 8813

Code: 128-Mbit 8815Bottom

Code: 256-Mbit 8816

Data: 128-Mbit 8818Top

Data: 256-Mbit 8819

Data: 128-Mbit 881BBottom

Data: 256-Mbit 881C

Data: 128-Mbit 881ETop

Data: 256-Mbit 881F

Data: 128-Mbit 8821Bottom

Data: 256-Mbit 8822

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10.8 CFI Query Command (0x98)

This command is a non-array read command. The CFI Query command instructs the device tooutput Common Flash Interface (CFI) data when partition or block addresses are read. SeeTable 19, “Command Bus Cycles” on page 47 for details on issuing the CFI Query command.Appendix D, “Common Flash Interface (CFI) for Code Segment” on page 94 shows CFIinformation and address offsets within the CFI database.

Issuing the CFI Query command to a partition or block that is programming or erasing places thatpartition or block outputs in the CFI Query state, while the partition or block continues to programor erase in the background. The CFI Query command is subject to read restrictions dependent onparameter partition or block availability, as described in Table 33, “Simultaneous OperationRestrictions for Flash Code Segment Die” on page 81.

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11.0 Program Operations

All flash segments support three programming methods: word programming, bufferedprogramming, and Buffered Enhanced Factory Programming (Buffered EFP). See Section 9.2,“Flash Device Commands” on page 47 and Section 9.3, “Command Definitions” on page 49 for alist of the various programming commands issued to the flash.

Successful programming requires the addressed block to be unlocked. If the block is locked down,F-WP# must be deasserted and issue the block unlock commands (setup / confirm) beforeattempting to program the block. Attempting to program a locked block causes a program error andterminates the operation. See Section 14.0, “Block Locking and Unlocking Operations” on page 66for details on locking and unlocking blocks. See Figure 21, “Status Register Description” onpage 54 for details on each segment flash status.

Programming the flash memory array changes bit state from a logical (1) to logical (0). Memoryarray bits that are logical (0) can be changed to logical (1) only by erasing the block (see Section12.0, “Erase Operations” on page 63).

11.1 Word Program Setup Command (0x40)

Word programming operations are initiated by writing the Word Program Setup command to thedevice. This is followed by a second write to the flash device with the address and data to beprogrammed. The partition or block address accessed during both write cycles outputs StatusRegister data when read. The partition or block address accessed during the second cycle (the datacycle) of the program command sequence is the location where the data is written. See Figure 35,“Word Program Flowchart” on page 86.

Programming can occur in only one partition or block at a time; all other partitions or blocks mustbe in a read state or in erase suspend. F-VPP ≥ VPPLK, and within the specified VPPL MIN/MAXvalues (nominally 1.8 V). Since the data segment flash is single partition die, word programmingstarts at the targeted block address.

During programming, the Write State Machine (WSM) executes a sequence of internally-timedevents that program the desired data bits at the addressed location, and verifies that the bits aresufficiently programmed.

The Status Register can be examined for programming progress and errors by reading any addresswithin the partition or block that is being programmed. The addressed partition or block remains inthe Status Register state until another command is written to that partition or block. Issuing theStatus Register command to another partition or block address sets that partition or block to theStatus Register state, allowing programming progress to be monitored at that partition or blockaddress.

To determine the status of a word-program during operation, poll the status register and analyze theSR[7:0] data bits. If the flash is put in standby mode during a program operation, the flash willcontinue to program the word until the operation is complete; the flash will then enter standbymode.

Status Register bit SR7 indicates the programming status while the sequence executes. Commandsthat can be issued to the programming partition during programming are Program Suspend, ReadStatus Register, Read Device Identifier, CFI Query, and Read Array. F-CE# or F-OE# must assertand deassert to update Status Register contents.

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When programming has finished, Status Register bits SR[4,3,1] indicate the result of the programoperation. SR4 will be set if there was a programming failure. If SR3 is set, the WSM could notperform the word programming operation because F-VPP was outside of its acceptable limits. IfSR1 is set, the operation attempted to program a locked block, causing the operation to abort.

Before issuing a new command, the Status Register contents should be examined and then clearedusing the Clear Status Register command. Any valid command can follow a completed programoperation. This is especially important when simultaneous operations are between the code anddata segment flash. See Section 17.0, “Dual Operation Considerations” for additional details.

11.1.1 Factory Word Programming

Factory word programming is similar to word programming in that it uses the same commands andprogramming algorithms. However, factory word programming enhances the programmingperformance with elevated F-VPP ≥ VPPH. Factory word programming is not intended for extendeduse. See Section 5.2, “Operating Conditions” on page 26 for limitations when F-VPP ≥ VPPH. Bothcode and data segments support factory programming with F-VPP ≥ VPPH.

When F-VPP ≤ VPPL, the flash draws programming current from the F-VCC supply. If F-VPP isdriven by a logic signal, VPPL ≥ VPPL MIN to program the flash. When F-VPP ≥ VPPH, the flashdraws programming current from the F-VPP supply. Figure 26 shows examples of device powersupply configurations.

When F-VPP ≤ VIL, absolute hardware write protection is provided for all flash blocks in both codeand data segments. If F-VPP ≤ VPPLK, programming operations halt and SR3 is set indicating a F-VPP level error. Block lock registers are not affected by the voltage level on F-VPP; they may stillbe programmed and read, even if F-VPP ≤ VPPLK.

.

Figure 26. Example F-VPP Supply Connections

Factory Word Programming with VPP = VPPH

Complete Write/Erase Protection when VPP < VPPLK

Low Voltage and Factory Word Programming Low Voltage Programming Only

Full Device Protection Unavailable

Low Voltage Programming Only

Logic Control of Device Protection

VCC

VPP PROT#

VCC

VPP

VCC

VPP10KΩ

VCC

VPP

VCC

VPP

VCC

VPP = VPPH

VCC

VCC

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11.2 Buffered Program Setup Command (0xE8)

To perform buffered programming, the Buffered Program command, 0xE8, is issued along with theblock address (see Section 9.2, “Flash Device Commands” on page 47). Status Registerinformation is updated, and reflects the availability of the buffer. SR7 indicates the availability ofthe buffer for loading data. If SR7 is set, the buffer is available; if not set, the buffer is notavailable. To retry, issue the Buffered Programming setup command again, and re-check SR7.When SR7 is set, the buffer is available. See Figure 37, “Buffered Programming Flowchart” onpage 88.

Each flash die in a code or data segment features a 32-word buffer to enable optimumprogramming performance. For buffered programming, data is first written to an on-chip buffer.Then the buffered data is programmed into the flash memory array in buffer-size increments. Next,a word count (32-words max) is written to the flash at the buffered address. On the next write, theflash start address is given along with the first data to be written to the flash memory array.Subsequent write cycles provide additional address and data. All data addresses must be within thestart address plus the word count. Optimum programming performance and lower power usage canbe obtained by aligning the starting address to a 32-word boundary, where A[4:0] = 0x00.

Note: A misaligned buffered programming starting address will double the total program time.

11.3 Buffered Program Confirm Command (0xD0)

After the last data is written to the buffer, the Buffered Program confirm command is issued. TheWrite State Machine begins to copy the buffered contents into the flash memory array. If acommand other than the Buffered Program confirm command is written to the flash, a commandsequence error will occur and Status Register bits SR[4,5,7] will be set. If an error occurs whilewriting to the array, the flash will stop programming, and Status Register bit SR[4] and SR[7] willbe set, indicating a programming failure.

When Buffered Programming has completed, additional buffered writes can be initiated by issuinganother Buffered Program setup command and repeating the buffered program sequence.

Anytime SR[4] and SR[5] are set, the flash will not accept Buffered Program commands. If anattempt is made to program past a block boundary using the Buffered Program command, the flashwill abort the operation. This will generate a command sequence error, and Status Register bitsSR[4] and SR[5] will be set.

If Buffered Programming is attempted while F-VPP ≤ VPPLK, Status Register bits SR[4:3] are set. Ifany errors are detected that have set Status Register bits, the Status Register should be clearedusing the Clear Status Register command.

11.4 Buffered EFP Setup Command (0x80)

Each code and data segment flash also features Buffered Enhanced Factory Programing (BufferedEFP) which further improves the Multi-Level Cell (MLC) flash programming time in beat-rate-sensitive manufacturing environments. This enhanced algorithm eliminates traditional elementsthat drive up overhead in off-board or on-board, off-line or in-line, manual or automatedprogrammer systems.

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Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 38, “BufferedEFP Flowchart” on page 89). Buffered EFP is different than non-buffered EFP mode; itincorporates a buffer to spread MLC program performance across 32 data words. Additionally,verification occurs in the same phase as programming, an inherent requirement of MLC technologyto accurately program the correct bit state.

A two-cycle command sequence programs an entire block of data. This enhancement eliminatesthree write cycles per buffer; two commands and the word count per each set of 32 data words.Host programmer bus cycles fill the flash buffer. This is followed by a status check of SR[0] todetermine when the data from that buffer has completed programming into sequential flashmemory array locations. Following the buffer-to-flash programming sequence, the WSMincrements internal addressing to automatically select the next 32-word array boundary.

Buffered EFP saves programming equipment address-bus setup overhead. With proper continuitytesting, programming equipment can rely on the WSM internal verification to ensure the device hasprogrammed properly. This capability eliminates the external post-program verification and itsassociated overhead. Buffered EFP Requirements and Considerations are shown in Table 26.

11.5 Buffered EFP Confirm Command (0xD0)

Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 38, “BufferedEFP Flowchart” on page 89).

Table 26. Buffered EFP Requirements and Considerations

Description Notes

Requirements

Case temperature: TC = 25 °C ± 5 °C

F-VCC within specified operating range. 1.7 V to 1.95 V

F-VPP driven to VPPH. Elevated F-VPP = 8.5 V to 9.5 V

Target block unlocked before issuing the Buffered EFP Setup and Confirm commands.

The first-word address (WA0) for the block to be programmed must be held constantfrom the setup phase through all data streaming into the target block, until transition tothe exit phase is desired.

WA0 must align with the start of an array buffer boundary. 1

Considerations

For optimum performance, cycling must be limited below 100 erase cycles per block 2

Buffered EFP programs one block at a time; all buffer data must fall within a singleblock. 3

Buffered EFP cannot be suspended.

Programming to the flash memory array can occur only when the buffer is full. 4

NOTES:1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00.2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly.3. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning

of the block.4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF.

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11.5.1 Buffered EFP Setup Phase

After receiving the Buffered EFP Setup and Confirm command sequence, Status Register bit SR[7](Ready) is cleared, indicating that the WSM is busy with Buffered EFP algorithm startup. A delaybefore checking SR[7] is required to allow the WSM enough time to perform all of its setups andchecks (Block-Lock status, F-VPP level, etc.). If an error is detected, SR[4] is set and Buffered EFPoperation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the erroroccurred due to an incorrect F-VPP level.

Reading from a flash die after issuing the Buffered EFP Setup and Confirm command sequenceoutputs Status Register data. Do not issue the Status Register command; it will be interpreted asdata to be loaded into the buffer. However, it is permissible to read from the another flash diewithin the LV SCSP device not undergoing Buffered EFP.

11.6 Buffered EFP Program/Verify Phase

After the Buffered EFP setup phase has completed, the host programming system must checkSR[7,0] to determine the availability of the buffer for data streaming. SR7 cleared indicates thedevice is busy and the Buffered EFP program/verify phase is activated. SR0 cleared indicates thebuffer is available.

Two basic sequences repeat in this phase: loading of the buffer, followed by programming bufferdata to the array. For Buffered EFP, the count value for loading the buffer is always the maximumbuffer size of 32-Words. During this buffer-loading sequence, data is stored to sequential bufferlocations starting at address 0x00. Programming of the buffer contents to the flash memory arraystarts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer wordlocations must be filled with 0xFFFF.

Data from the buffer are directed to sequential memory locations in the flash memory array;programming continues from where the previous buffer sequence ended. The host programmingsystem must poll SR0 to determine when the buffer program sequence completes. SR0 clearedindicates that all buffer data has been transferred to the flash array; SR0 set indicates that the bufferis not available for the next fill cycle. The host system may check full status for errors at any time,but it is only necessary on a block basis after Buffered EFP exits. The host programming systemcontinues the Buffered EFP algorithm by providing the next group of data words to be written tothe buffer. Alternatively, the host programming system can terminate this operation by changingthe block address to an address outside of the current block’s range.

The Program/Verify phase concludes when the programmer writes to a different block address;data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters theBuffered EFP Exit phase.

Caution: The buffer must be completely filled for programming to occur. Supplying an address outside of thecurrent block's range during a buffer-fill sequence causes the operation to lock-up and the BufferedEFP algorithm to exit immediately. Any data previously loaded into the buffer during the fill cycleis not programmed into the array. The starting address for data entry must be buffer-size aligned; ifnot, the Buffered EFP algorithm will be aborted and the program fail (SR4) flag will be set.

11.6.1 Buffered EFP Exit Phase

When SR7 is set, the device has returned to normal operating conditions. A full status check shouldbe performed at this time to ensure the entire block programmed successfully. After Buffered EFPexit, any valid command can be issued to the flash.

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12.0 Erase Operations

Erasing the flash is performed on a block basis. An entire block is erased each time an erasecommand sequence is issued, one block at a time. When a block is erased, all bits within that blockread as logical one’s. The following sections describe block erase operations in detail.

12.1 Block Erase Setup Command (0x20)

Block erase is a two-cycle command operation. Erase is initiated by issuing an Erase Setupcommand to the block address to be erased (see Section 9.2, “Flash Device Commands” on page 47and Section 9.3, “Command Definitions” on page 49). Next, the Erase Confirm command is issuedto the block address to be erased.

12.2 Block Erase Confirm Command (0xD0)

After the block erase operation is initiated by writing the Block Erase Setup command to theaddress of the block to be erased, the Block Erase Confirm command is written to the address ofthe block to be erased. (See Section 9.2, “Flash Device Commands” on page 47 and Section 9.3,“Command Definitions” on page 49).

An Erase operation can occur in only one partition or block at a time; all other partitions or blocksmust be in a read state. It is possible to have both code and data segment flash perform an eraseoperation by issuing successive erase command sequences to each segment and asserting either F-CE# in sequence. If the flash is placed in standby (F-CE# is deasserted) during an erase operation,the flash completes the erase operation before entering standby. F-VPP ≥ VPPLK and the block mustbe unlocked (see Figure 39, “Block Erase Flowchart” on page 90).

During a block erase, the Write State Machine (WSM) performs a sequence of internally-timedevents that conditions, erases, and verifies all bits within the block. Erasing the flash memory arraychanges logical zero to logical one. Memory array bits that are ones can be changed to zeros onlyby programming the block (see Section 11.0, “Program Operations” on page 58).

The Status Register can be examined for block erase progress and errors by reading any addresswithin the partition or block that is being erased. The partition or block remains in the Read StatusRegister state until another command is written to that partition or block. Issuing the StatusRegister command to another partition or block address sets that partition or block to the StatusRegister state, allowing erase progress to be monitored at that address location. SR[0] determineswhether the addressed partition or block or another partition or block is erasing within the sameflash. SR[0] = 1 indicates another partition or block is erasing and SR[0] = 0 indicates theaddressed partition or block is erasing. The Status Register bit SR[7] is set upon erase completion.

Status Register bit SR[7] determines block erase status while the sequence is performing. When theerase operation has finished, Status Register bit SR[5] indicates whether an erase failure hasoccurred. SR[3] set indicates the WSM could not perform the erase operation because F-VPP wasoutside of its acceptable limits. SR[1] indicates if an erase operation attempted to erase a lockedblock, causing the operation to abort. F-CE# or F-OE# must deassert, then assert to update StatusRegister contents. Before issuing a new command, the Status Register contents should be examinedand then cleared using the Clear Status Register command. Any valid command can follow oncethe block erase operation has completed.

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13.0 Suspend and Resume Operations

When F-VPP = VIL, absolute hardware erase protection is provided for all device blocks. If F-VPP ≤VPPLK, erase operations halt and SR[3] is set indicating a F-VPP level error.

13.1 Erase Suspend Command (0xB0)

Issuing the Erase Suspend command while erase is in progress suspends the block erase operation.This allows data to be accessed from a memory location other than the one being erased. The EraseSuspend command can be issued to any segment flash address within the block. A block eraseoperation can be suspended to perform a word or buffer program operation, or a read operationwithin any block except the block that is erase-suspended (see Figure 36, “Program Suspend/Resume Flowchart” on page 87).

When a block erase operation is executing, issuing the Erase Suspend command requests the WSMto suspend the erase algorithm at one of several predetermined points. The partition or block that issuspended continues to output Status Register data after the Erase Suspend command is issued.Block erase is suspended when Status Register bits SR[7:6] are set. Suspend latency is specified inSection 7.5, “Program and Erase Characteristics” on page 41.

To read data from blocks within the suspended partition or block (other than an erase-suspendedblock), the Read Array command must be issued to that partition or block first. During EraseSuspend, a Program command can be issued to any block other than the erase-suspended block.Block erase cannot resume until program operations initiated during erase suspend complete. ReadArray, Read Status Register, Read Device Identifier, CFI Query, and Erase Resume are validcommands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend,Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend.

During an erase suspend, deasserting F-CE# places the selected segment flash in standby, reducingactive current. F-VPP must remain at a valid level, and F-WP# must remain unchanged while inerase suspend. If F-RST# is asserted, both the code and data segments are reset.

Note: If both segments are executing an erase operation, the Erase Suspend command applies to thedevice segment with F-CE# asserted. If both F-CE#’s are asserted, erase operations for both devicesegments are suspended.

13.2 Program Suspend Command (0xB0)

A program suspend command pauses any programming operation. A suspend command can beissued to any flash die address. The suspend command allows data to be accessed from anymemory location other than from the one being programmed or from a block being erased. Thepartition or address corresponding to the suspend command address is not affected.

A program operation can be suspended to perform a read-only. However, an Erase operation can besuspended to perform either a program or read operation. A program command nested within asuspended Erase can be suspended to read in another address location. (see Figure 36, “ProgramSuspend/Resume Flowchart” on page 87).

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When a programming operation has started, issuing a suspend command requests the WSM tosuspend the programming algorithm at predetermined points. The partition or address that issuspended continues to output Status Register data after the program suspend command is issued.A program operation is suspended when Status Register bits SR[7,2] are set. Suspend latency(tSUSP/P) is specified in Section 7.5, “Program and Erase Characteristics” on page 41.

To read data from blocks within the suspended partition or block, other than an erase-suspendedblock, the Read Array command can be written to that partition or address. Read Array, StatusRegister, Device Identifier, CFI Query, Read Configuration Register, Enhanced ConfigurationRegister, and Program Resume are valid commands during a program suspend.

During a program suspend, deasserting F-CE# places the flash in standby which reduces supplycurrent by placing the flash in standby. F-VPP must remain at its programming level, and F-WP#must remain unchanged while in program suspend mode. If F-RST# is asserted, both the code anddata segments are reset.

13.3 Program Resume Command (0xD0)

The Resume command instructs the device to continue programming, and automatically clearsStatus Register bits SR[7,2]. This command can be written to any partition or block in anysegment. When read at the partition or block that is programming, the flash outputs data thatcorresponds to that partition last state. If error bits are set, the Status Register should be clearedbefore issuing the next instruction. F-RST# must remain deasserted (see Figure 36, “ProgramSuspend/Resume Flowchart” on page 87).

13.4 Erase Resume Command (0xD0)

The Erase Resume command instructs the corresponding segment to continue erasing, andautomatically clears status register bits SR[7:6]. This command can be written to any partition orblock. When read at the partition or block that is erasing, the flash outputs data corresponding tothe partition or block last state. If status register error bits are set, the Status Register should becleared before issuing the next instruction. F-RST# must remain deasserted (see Figure 36,“Program Suspend/Resume Flowchart” on page 87).

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14.0 Block Locking and Unlocking Operations

The 1024-Mbit LV family features security modes used to protect the information stored in thecode and data segment memory arrays. The following sections describe each security mode indetail.

Individual instant block locking is used to protect data in the flash memory array. All blocks powerup in a locked state to protect array data from being altered during power transitions. Any blockcan be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; theycan only be read. Refer to Figure 19, “Command Bus Cycles” on page 47 for block lock commandcycles, and Table 27 for block lock state diagram.

Software-controlled security is implemented using the Block Lock and Block Unlock commands.Hardware-controlled security can be implemented using the Block Lock-Down command alongwith asserting F-WP# to inhibit all program and erase operations. Figure 27, “Block Locking StateDiagram provides an overview of block lock security management.

14.1 Block Locking During Erase Suspend

Block locking changes can be made during an erase suspend (but not during program suspend) byusing the standard locking command sequences to unlock, lock, or lock-down a block. This isuseful when another block needs to be updated while an erase operation is suspended.

To change block locking during an erase operation, first issue the Erase Suspend command, thencheck the status register SR[7:6] until it indicates that the erase operation has suspended. Nextissue the desired confirmed lock command sequence to a target block, and the lock state of thetarget block will be changed. After completing block lock, read, or program operations, resume theerase operation with the Erase Resume command. If a block is locked or locked-down during anerase suspend of the same block, the locking status bits will change immediately. But, whenresumed, the erase operation will complete.

Nested lock or program commands during erase suspend can return ambiguous status registerresults. A Configuration Setup command (0x60) followed by an invalid command produces a lockcommand status register error (SR[5:4] = 1). If this error occurs during erase suspend, SR[5:4]remain at logical one (1) after the erase resumes. When erase completes, the previous lockingcommand error hides the status register’s erase errors. A similar situation occurs if a programoperation error is nested within an erase suspend. See Appendix A, “Write State Machine (WSM)for Code Segment” on page 84, which shows valid commands during an erase suspend.

Caution: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block,or Lock-Down Block produces a command sequence error and sets Status Register bits SR[4] andSR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set,even after the erase operation is resumed. Unless the Status Register is cleared using the ClearStatus Register command before resuming the erase operation, possible erase errors may bemasked by the command sequence error.

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14.1.1 F-WP# Lock-Down Control

If the lock-down status bit is set for a particular block, the F-WP# signal is then enabled as a masterlock/unlock override for that particular block.

When F-WP# is asserted, all blocks that have the lock-down status bit set are automatically put intothe lock-down state and cannot be unlocked with the Unlock Block command. Once F-WP# isdeasserted, the block reverts back to a locked state; only then can it be unlocked via software.

Figure 27. Block Locking State Diagram

[X00]

[X01]Power-Up/Reset

Unlocked

Locked

[011]

[111] [110]

Locked-Down4,5

SoftwareLocked

[011]

HardwareLocked5

Unlocked

WP# Hardware Control

Notes: 1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care.2. D1 indicates block Lock-down status. D1 = ‘0’, Lock-down has not been issued to

this block. D1 = ‘1’, Lock-down has been issued to this block.3. D0 indicates block lock status. D0 = ‘0’, block is unlocked. D0 = ‘1’, block is locked.4. Locked-down = Hardware + Software locked.5. [011] states should be tracked by system software to determine difference between

Hardware Locked and Locked-Down states.

Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)

Software Block Lock-Down (0x60/0x2F)

WP# hardware control

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14.2 Lock Block Setup Command (0x60)

To lock an unlocked block, a two cycle command sequence is required. First issue the Lock BlockSetup command. The next command must be the Lock Block command issued to the desiredblock’s address (See Figure 41, “Block Lock Operations Flowchart” on page 92).

If the Set RCR command is issued after the Lock Block Setup command, the flash configures theRCR instead. Block lock and unlock operations are not affected by the voltage level on F-VPP. Theblock lock register bits may be modified or read even if F-VPP ≤ VPPLK.

14.3 Unlock Block Command (0xD0)

Locked blocks can be unlocked by issuing the two-cycle Unlocked block commands. Unlockedblocks can be read, programmed, and erased. Unlocked blocks always return to a locked state whenthe device is reset or powered down.

14.4 Lock-Down Block Command (0x2F)

The Lock-Down Block command adds an additional level of security to the flash. Issuing the Lock-Down Block command sets the lock-down status bit and locks the block. The Lock-Down Blockcommand can be used if the block’s current state is either locked or unlocked. Once this bit is set,F-WP# is enabled as a hardware lock control for that particular block.

If a block is locked-down and F-WP# is deasserted, the user must issue the Unlock Blockcommand to allow program or erase operations on that block.Only device reset or power-down canclear the lock-down status bit.

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15.0 Protection Register Operation (Code Die)

Protection Register Operations applies only to the code segment. In a LV SCSP device, only thecode segment flash contains Protection Registers, PR[16:0]. If the code segment contains two flashdies, each die will have a total of 2176-bits of Protection Registers. The Protection Registers aresub-divided into sixteen 128-bit increments, which can be used to implement system securitymeasures and/or device identification. Each user accessible Protection Register can be individuallylocked.

PR[0] is comprised of two 64-bit (8-words) components. The lower 64-bit component is pre-programmed at the factory with a unique 64-bit number. The other 64-bit component, as well as thePR[16:1] are users programmable registers. The PR can be programmed in single word increments.The PR can be locked to prevent additional bit programming (see Figure 28, “Protection RegisterMap” on page 70).

The Protection Registers contain one-time programmable (OTP) bits; when programmed, registerbits cannot be erased; that is, they cannot be re-programmed from a logical zero (0) to a logical one(1). Each PR can be accessed multiple times to program individual bits, as long as the registerremains unlocked or if the register programmed data bit stream has logical one (1) available.

Each PR has an associated Lock Register bit. When a Lock Register bit is programmed, theassociated PR can only be read; it can no longer be programmed. Additionally, because the LockRegister bits themselves are OTP, when programmed, Lock Register bits cannot be erased.

15.1 Reading the Protection Registers

The Protection Registers can be read from within any partition address space. To read the PR data,first issue the Read Device Identifier command at any partition address to place that partition in theRead Device Identifier state (see Section 9.2, “Flash Device Commands” on page 47 and Section9.3, “Command Definitions” on page 49). Next, perform a read operation at that partition baseaddress plus the address offset corresponding to the register to be read. Table 24, “Device IdentifierInformation” on page 56 shows the address offsets of the Protection Registers and Lock Registers.Register data is read one word at a time.

Note: If a program or erase operation occurs in one partition while reading a Protection Register inanother partition, certain restrictions may apply. See Table 33, “Simultaneous OperationRestrictions for Flash Code Segment Die” on page 81 for details.

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15.2 Program Protection Register Setup Command (0xC0)

To program any of the Protection Registers, first issue the Program Protection Register commandat the parameter partition base address plus the offset to the desired Protection Register (seeSection 19, “Command Bus Cycles” on page 47). Next, write the desired Protection Register datato the same Protection Register address (see Figure 28, “Protection Register Map” on page 70).

The device programs the OTP register data one word at a time (see Figure 42, “Protection RegisterProgramming Flowchart” on page 93). Issuing the program Protection Register command outsideof the Protection Register’s address space causes a program error (SR[4] set). Attempting toprogram a locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1]set).

15.2.1 Locking the Protection Registers

Each Protection Register can be locked by programming its respective lock bit in the LockRegister. To lock a Protection Register, program the corresponding bit in the Lock Register byissuing the Program Lock Register command, followed by the desired Lock Register data. Bit 0 ofLock Register 0 is pre-programmed at Intel with unique identification numbers. Bit 1 of LockRegister 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first128-bit PR[0] section. The remaining bits in Lock Register 0 are not used and cannot be changedby the user. Lock Register 1 controls the locking of the PR[16:1]. Each of the 16 bits of LockRegister 1 correspond to each of the upper sixteen 128-bit PRs. Once locked, the PR cannot beunlocked.

Figure 28. Protection Register Map

0x89PR Lock Register 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x102

0x109

0x8A

0x91

0x84

0x88

0x85

0x81

0x80PR Lock Register 0

User-Programmable

Intel Factory-Programmed

(User-Programmable)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

(User-Programmable)

PR16

PR1

PR0

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16.0 Configuration Operations

The Read Configuration Register (RCR) is used to configure the code segment flash (synchronousor asynchronous) and data segment flash (asynchronous) read modes. RCR[15:0] contents can beexamined by using the Device Identifier command, and then reading from <partition base or blockaddress> + 0x05. For data segment flash die, only the RCR.10 can be changed by the user. Changesto the default settings cause the flash die to be in an indeterminate state. A reset of the flash isrequired to restart normal operation. The RCR bits are shown in Table 27, “Read ConfigurationRegister Description” on page 72.

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Table 27. Read Configuration Register Description

Read Configuration Register (RCR) Default Value = 0xFFFF

ReadMode RES Latency Count WAIT

PolarityData

Hold

WAIT

DelayBurstSeq

CLKEdge RES RES

Burst

WrapBurst Length

RM R LC[2:0] WP DH WD BS CE R R BW BL[2:0]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit Name Description

15 Read Mode (RM)0 = Synchronous burst-mode read

1 = Asynchronous page-mode read (default)

14 Reserved (R) Reserved bits should be cleared (0)

13:11 Latency Count (LC[2:0])

010 =Code 2

011 =Code 3

100 =Code 4

101 =Code 5

110 = Code 6

111 = Code 7 (default)

(Other bit settings are reserved)

10 Wait Polarity (WP)

0 =WAIT signal is active low

1 =WAIT signal is active high (default)

Note: The user must set the data segment flash RCR.10 to be equal to codesegment flash RCR.10 prior to normal operation.

9 Data Hold (DH) 0 =Data held for a 1-clock data cycle1 =Data held for a 2-clock data cycle (default)

8 Wait Delay (WD) 0 =WAIT deasserted with valid data1 =WAIT deasserted one data cycle before valid data (default)

7 Burst Sequence (BS) 0 =Reserved1 =Linear (default)

6 Clock Edge (CE) 0 = Falling edge1 = Rising edge (default)

5:4 Reserved (R) Reserved bits should be cleared (0)

3 Burst Wrap (BW) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]1 =No Wrap; Burst accesses do not wrap within burst length (default)

2:0 Burst Length (BL[2:0])

001 =4-word burst010 =8-word burst011 =16-word burst111 =Continuous-word burst (default)

(Other bit settings are reserved)

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16.1 Read Mode Bit- RCR.15

The Read Mode (RM) bit selects the synchronous burst-mode or the asynchronous page-modeoperation for the data segment flash. When the RM bit is set, the asynchronous page-mode read isselected (default). When RM is cleared, the synchronous-burst mode read is selected.

16.2 Latency Count Bit - RCR[13:11]

The Latency Count bits, LC[2:0], set the flash to count how many clock cycles must elapse fromthe first valid clock edge after ADV# is asserted, or from the rising edge of ADV#, until the firstdata word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value.Figure 29 shows the data output latency for the different settings of LC[2:0].

Refer to Table 28, “LC and Frequency Support for Code Die Segment Flash” on page 74 forLatency Code Settings.

During synchronous-burst mode read, a Latency Count setting of Code 4 results in a zero WAITstate. However, a Latency Count setting of code 5 causes one WAIT state after every four words,regardless of whether a 16-word boundary is crossed. (Note that a Latency Count setting of code 6causes two WAIT states and a Latency Count setting of code 7 causes three WAIT states.) If RCR.9bit is set, indicating a data hold of two clocks, this WAIT condition does not occur because enoughclocks elapse during each burst cycle to eliminate subsequent WAIT states.

Figure 29. First-Access Latency Count

Code 1(Reserved

Code 6

Code 5

Code 4

Code 3

Code 2

Code 0 (Reserved)

Code 7

ValidAddress

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

Address [A]

ADV# [V]

Data [D/Q]

CLK [C]

Data [D/Q]

Data [D/Q]

Data [D/Q]

Data [D/Q]

Data [D/Q]

Data [D/Q]

Data [D/Q]

Datasheet 73

1024-Mbit LV Family

16.3 WAIT Polarity Bit - RCR.10

The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT. WhenWP is set, WAIT is a high-true signal (default). When WP is cleared, WAIT is a low-true signal.WAIT changes state on valid clock edges during active bus cycles (F-CE# and F-OE# asserted, F-RST# deasserted).

Caution: The user is require to configure the data segment flash RCR.10 to be the same configuration settingas the code segment flash for valid operation. Configuring the code and data segment RCR.10differently may result in bus contention during read operation.

Table 28. LC and Frequency Support for Code Die Segment Flash

Latency Count Settings Frequency Support (MHz)

2 ≤ 28

3 ≤ 40

4, 5, 6, or 7 ≤ 54

Figure 30. Example Latency Count Setting Using LC=3

CLK

F-CE#

ADV#

A[MAX:0]

DQ[15:0]

tData

Code 3

Address

Data

0 1 2 3 4

R103

High-Z

74 Datasheet

1024-Mbit LV Family

16.3.1 WAIT Signal Function

The WAIT signal indicates when data is valid or invalid with the code segment flash operating insynchronous-burst mode read (RCR.15 = 0). WAIT is active for synchronous array read andsynchronous non-array read with the code segment flash. The WAIT signal is deasserted only whendata is valid on the bus.

When the device is operating in synchronous non-array read mode, such as read status, read ID, orread query, the WAIT signal is also “de-asserted” when data is valid on the bus.

When the device is operating in asynchronous page mode, asynchronous single word read mode,and all write operations, WAIT is set to a de-asserted state as determined by RCR.10. See Figure14, “Asynchronous Single-Word Read with ADV# Latch, and Figure 15, “Asynchronous Page-Mode Read Timing” on page 34.

Note: Refer to Table 29 for WAIT state in specific operational modes.

Table 29. WAIT Summary Table

CONDITION WAIT

F-CE# = VIHF-CE# = VIL

High-ZDriven

F-OE# = VIHF-OE# = VIL

High-ZDriven

Synchronous Array Reads Driven

Synchronous Non-Array Reads Driven

Asynchronous Reads Deasserted

Write operations High-Z

NOTE: Active: WAIT is asserted until LC is completed and data becomes valid, thendeasserts.

Datasheet 75

1024-Mbit LV Family

16.4 Data Hold Bit - RCR.9

For code segment burst read operations, the Data Hold (DH) bit determines whether the data outputremains valid on DQ[15:0] for one or two clock cycles. When DH is set, output data are held fortwo clocks (default). When DH is cleared, output data are held for one clock (see Figure 31). Theprocessor’s data setup time and the flash memory’s clock-to-data output delay should beconsidered when determining whether to hold output data for one or two clocks.

Note: Here is one possible method for determining the Data Hold configuration:

To set the device at one clock data hold for subsequent reads, the following condition must besatisfied:

tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)

tDATA = Data set up to Clock (defined by CPU)

For example, with a clock frequency of 54 MHz, the clock period is 18.5 ns.

Assumption, tCHQV = 14 ns and tDATA = 4ns and applying these values to the formula yields

14 ns + 4 ns ≤ 18.5 ns

The equation is satisfied and data will be available at every clock period with data hold setting atone clock.

If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), then data hold setting of 2 clock periods must beused.

16.5 WAIT Delay Bit - RCR.8

The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burstreads. WAIT can be asserted either during or one data cycle before invalid data is output onDQ[15:0]. When WD is set, WAIT is asserted one data cycle before invalid data (default). WhenWD is clear, WAIT is asserted during invalid data.

Figure 31. Data Hold Timing

ValidOutput

ValidOutput

ValidOutput

ValidOutput

ValidOutput

CLK [C]

D[15:0] [Q]

D[15:0] [Q]2 CLKData Hold

1 CLKData Hold

76 Datasheet

1024-Mbit LV Family

16.6 Burst Sequence Bit - RCR.7

The Burst Sequence (BS) bit selects linear-burst sequence (default). Table 30 Shows thesynchronous burst sequence for all burst lengths, as well as the effect of the Burst Wrap (BW)setting, RCR.3.

Table 30. Burst Sequence Word Ordering

StartAddr.(DEC)

BurstWrap

(RCR.3)

Burst Addressing Sequence (DEC)

4-Word Burst(BL[2:0] =

0b001)

8-Word Burst(BL[2:0] = 0b010)

16-Word Burst(BL[2:0] = 0b011)

Continuous Burst(BL[2:0] = 0b111)

0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…

1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5…15-0 1-2-3-4-5-6-7-…

2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6…0-1 2-3-4-5-6-7-8-…

3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7…1-2 3-4-5-6-7-8-9-…

4 0 4-5-6-7-0-1-2-3 4-5-6-7-8…2-3 4-5-6-7-8-9-10…

5 0 5-6-7-0-1-2-3-4 5-6-7-8-9…3-4 5-6-7-8-9-10-11…

6 0 6-7-0-1-2-3-4-5 6-7-8-9-10…4-5 6-7-8-9-10-11-12-…

7 0 7-0-1-2-3-4-5-6 7-8-9-10-11…5-6 7-8-9-10-11-12-13…

… … … … … …

14 0 14-15-0-1-2…12-13 14-15-16-17-18-19-20-…

15 0 15-0-1-2-3…13-14 15-16-17-18-19-20-21-…

… … … … … …

0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…

1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5…15-16 1-2-3-4-5-6-7-…

2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6…16-17 2-3-4-5-6-7-8-…

3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7…17-18 3-4-5-6-7-8-9-…

4 1 4-5-6-7-8-9-10-11 4-5-6-7-8…18-19 4-5-6-7-8-9-10…

5 1 5-6-7-8-9-10-11-12 5-6-7-8-9…19-20 5-6-7-8-9-10-11…

6 1 6-7-8-9-10-11-12-13 6-7-8-9-10…20-21 6-7-8-9-10-11-12-…

7 1 7-8-9-10-11-12-13-14 7-8-9-10-11…21-22 7-8-9-10-11-12-13…

… … … … … …

14 1 14-15-16-17-18…28-29 14-15-16-17-18-19-20-…

15 1 15-16-17-18-19…29-30 15-16-17-18-19-20-21-…

Datasheet 77

1024-Mbit LV Family

16.7 Clock Edge Bit - RCR.6

The Clock Edge bit selects either a rising (default) or falling clock edge for CLK. This clock edgeis used at the start of a burst cycle count to output synchronous data and to assert/deassert WAIT.

16.8 Burst Wrap Bit - RCR.3

The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesseswrap within the selected word-length boundaries or cross word-length boundaries. When BW isset, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs.

When performing synchronous burst reads with BW set (no wrap), an output delay may occurwhen the burst sequence crosses the first 16-word boundary. If the burst sequence start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word boundary, the worstcase output delay is one clock cycle less than the first access Latency Count. This delay can takeplace only once, and does not occur if the burst sequence does not cross the first 16-word boundary.WAIT informs the system of this delay when it occurs.

16.9 Burst Length Bit - RCR[2:0]

The Burst Length (BL) bits RCR[2:0] select the linear burst length for all synchronous burst readsof the flash memory array. The burst lengths are 4-word, 8-word, 16-word, or continuous-word.Continuous-burst accesses are linear only, and do not wrap within any word length boundaries seeTable 30, “Burst Sequence Word Ordering” on page 77. When a burst cycle begins, the codesegment flash outputs synchronous burst data until it reaches the end of the available andaccessible contiguous address space.

16.10 Set Read Configuration Register Command (0x60)

The Set Read Configuration Register command is the first cycle of a two-cycle command toprepare the CUI for flash read configuration. If the set Read Configuration Register command(0x03) is not the second command, the CUI sets Status Register bits SR[4] and SR[5], indicating acommand sequence error.

16.11 Write Read Configuration Register Command (0x03)

If the previous command was Read Configuration Register Setup (0x60), the CUI latches theaddress and writes A[15:0] to the Read Configuration Register. Following a configured ReadConfiguration Register command, subsequent read operations access array data.

78 Datasheet

1024-Mbit LV Family

17.0 Dual Operation Considerations

The multi-partition architecture of the code segment allows programming or erasing to occur inone partition or block while reading or code execution occurs from another partition or block. Inaddition, the LV SCSP device configuration enables reading from the code segment whileprogramming or erasing within the data segment; conversely it is possible to read from the datasegment while programming or erasing in the code segment. Simultaneous program and erase isnot allowed within the same partition.

17.1 Consecutive Back-to-Back Bus Cycle Operations

Consecutive bus cycles within each flash die must be properly separated from each other for validoperation. Cycle separation specifications that apply to the possible cycle transitions are listed intables Table 31 and Table 32 for devices configured in asynchronous single word read andsynchronous-burst mode read respectively.

When issuing commands to a flash, a read operation can occur between two-cycle Write commandsequence (see Figure 32 on page 80 and Figure 33 on page 80). However, a write operation issuedbetween a two-cycle Write command sequence causes a command sequence error. (See Figure 34,“Invalid Command Bus Cycle Sequence” on page 80.)

Table 31. Asynchronous Cycle Separation Specification

Cycle Transition Relevant Specifications Notes

Read to Read tAVAV (R1) No toggle required. Data valid tAVAV afteraddress valid

Read to Write tEHEL (R11) OR tVHVL (R105) Requires a toggle of either F-CE# or ADV#

Write to Write tWHWL OR tEHEL (W9) Requires a toggle of either F-CE# or F-WE#

Write to Read tWHAV (W18) Valid address is require for valid read

Table 32. Synchronous Cycle Separation within a code segment flash

Cycle Transition Relevant Specifications Notes

Read to Read tEHEL (R11) OR tVHVL (R105) Requires a toggle of either F-CE# or ADV#

Read to Write tEHEL (R11) OR tVHVL (R105) Requires a toggle of either F-CE# or ADV#

Write to Write tWHWL OR tEHEL (W9) Requires a toggle of either F-CE# or F-WE#

Write to Read tWHCH/L (W19) OR tWHVH (W20)

tWHCH/L or tWHVH both refer to the addresslatching event. One of these two specs must bemet.

Requires a toggle of either F-CE# or ADV# forvalid read.

Datasheet 79

1024-Mbit LV Family

Issuing a Read Status, a Program, or an Erase command to a partition or block places that partitionor block in the Read Status state. Status register bit SR.7 (DWS — Device Write Status) providesprogram/erase status of the flash. The Partition Write Status bit (PWS) tells whether the addressedpartition or block or some other partition or block is actively programming or erasing. Statusregister bits SR[6:1] present information about the WSM’s program, erase, suspend, F-VPP, andblock-lock status. Table 21, “Status Register Description” on page 54 presents descriptions ofDWS (SR.7) and PWS (SR.0) combinations. For sample Read to Write and Write to Read sequencewaveforms, see Figure 23, “Synchronous Read to Write Timing” on page 39.

Figure 32. Command Bus Cycle Sequence

Partition A Partition A Partition B

0x20 0xD0 0xFF

Address [A]

WE# [W]

OE# [G]

Data [D/Q]

Figure 33. Interleaved Command Bus Cycle Sequence

Partition A Partition B Partition A

0x20 Array Data 0xD0

Address [A]

WE# [W]

OE# [G]

Data [D/Q]

Figure 34. Invalid Command Bus Cycle Sequence

Partition A Partition B Partition A Partition A

0x20 0xFF 0xD0 SR[7:0]

Address [A]

WE# [W]

OE# [G]

Data [D/Q]

80 Datasheet

1024-Mbit LV Family

17.2 Read during a Buffered Program Operation

To perform a read during buffered programming operation, the Buffered Program command mustbe issued first to a partition or block. If a read operation is issued to a partition or block after asetup command has been issued, Status Register data is returned, regardless of the read mode of thepartition or block prior to issuing the setup command.

To read data from a block in another partition that is already in read array mode, a new blockaddress must be issued. However, if the other partition or block is not in read array mode, issuing aread array command will cause the Buffered Program operation to abort and a command sequenceerror will be posted in the Status Register. See Appendix C, “Flowcharts” on page 86 for moredetails.

Note: Simultaneous read-while-Buffered EFP is not supported.

17.3 Simultaneous Operation Restrictions

Since the code segment supports simultaneous read from one partition while programming orerasing in another partition, certain features like the Protection Registers and CFI Query data havespecial requirements with respect to simultaneous operation capability. (Table 33, “SimultaneousOperation Restrictions for Flash Code Segment Die” on page 81 provides details on restrictionsduring simultaneous operations.)

Note: For the 1024-Mbit LV family, simultaneous operation restrictions also apply to accesses betweencode and data operations.

Table 33. Simultaneous Operation Restrictions for Flash Code Segment Die (Sheet 1 of 2)

ProtectionRegister or

CFI data

ParameterPartition

Array Data

OtherPartitions Notes

Read (See Notes) Write/Erase

While programming or erasing in a main partition or block, the Protection Registeror CFI data may be read from any other partition or block.

Reading the parameter partition or block array data is not allowed if the ProtectionRegister or Query data is being read from addresses within the parameterpartition or block.

(See Notes) Read Write/Erase

While programming or erasing in a main partition or block, read operations areallowed in the parameter partition or block.

Accessing the Protection Registers or CFI data from parameter partition or blockaddresses is not allowed when reading array data from the parameter partition orblock.

Datasheet 81

1024-Mbit LV Family

17.4 Simultaneous Operation Details

The LV multi-die SCSP device can initiate another concurrent operation to another die as long asthe bus is not busy. Programming another die while erasing or erasing another die whileprogramming are some examples of concurrent operations.

This section explains details regarding simultaneous operations between code and data segments.The 1024-Mbit LV family enables simultaneous reading from one flash segment while a programor erase operation occurs in another flash segment. Refer to the information in “Read Operations”on page 51 before performing simultaneous operations within the data segment flash.

Table 34 provides an illustrated description of valid simultaneous access within one bus operationcycle. The operation cycle T0 represents time-zero of the device operation. To ensure contentionsare avoided and lowest power are achieved, only one flash die should be selected (F-CE# enabled)during simultaneous operations.

It is up to the user to ensure all Read, Write, or Erase operations are completed in accordance tovalid bus command shown in Table 19, “Command Bus Cycles” on page 47. Between eachoperation bus cycle, SR[7:0] should be monitored to prevent WSM contentions that can occur ifone operation is executed before another operation has completed.

When a Read or Write Command occurs, the bus is busy. Program or erase operations can continuein the background once the program or erase setup/confirm commands are completed, the bus isavailable.

• Simultaneous reads between two flash dies are prohibited within one operation bus cycle

• Simultaneous read in one flash die while issuing a program or erase command within the samedie is prohibited.

• Simultaneous background program in one flash die while reading in another flash die is OK.

• Simultaneous background program or erase in multiple flash dies are OK if the program orerase command setup/confirm are not performed within the same operation bus cycle.

• Performing simultaneous background program or erase in three flash dies and performingRWW/RWE in a code segment flash die is acceptable, long as no bus contentions occur duringthe operation cycle.

Read Read Write/Erase

While programming or erasing in a main partition or block, read operations areallowed in the parameter partition or block.

Accessing the Protection Registers or CFI data in a partition or block that isdifferent from the one being programed/erased, and also different from theparameter partition or block is allowed.

Write No AccessAllowed Read

While programming the Protection Register, reads are only allowed in the othermain partition or blocks.

Access to array data in the parameter partition or block is not allowed.Programming of the Protection Register can only occur in the parameter partitionor block, which means this partition or block is in Read Status.

No AccessAllowed Write/Erase Read

While programming or erasing the parameter partition or block, reads of theProtection Registers or CFI data are not allowed in any partition or block.

Reads in partition or blocks other than the main partition or blocks are supported.

Table 33. Simultaneous Operation Restrictions for Flash Code Segment Die (Sheet 2 of 2)

ProtectionRegister or

CFI data

ParameterPartition

Array Data

OtherPartitions Notes

82 Datasheet

1024-Mbit LV Family

Table 34. Example of a Code and Data Segment Simultaneous Operations Cycle

17.4.1 Concurrent Operations Power Considerations

Device operation current is additive during concurrent operations. As additional concurrentoperations are initiated in parallel, the operating current for each additional die adds to the totalcurrent consumed by any on-going operations. Total power at any given time will be the sum of allactive currents plus inactive (e.g., standby) currents.

Adequate power supply current capacity (e.g., voltage regulator size), delivery, and noisedecoupling measures must be implemented in the system design to ensure reliable concurrentoperations. For more details regarding concurrent program and erase using the Intel StrataFlash®

Wireless Memory System (L18/L30 SCSP), please refer to Application Note document number253856.

OperationCycle

CodeDie#1

CodeDie#2

DataDie#3

DataDie#4

CodeDie#1

CodeDie#2

DataDie#3

DataDie#4

Time (T0) CMD Read

T1 Erase CMD RWWT2 Erase Program CMD RWWT3 Erase Program Erase CMD CMDT4 Erase Program Erase Program Program CMDT5 CMD Program Erase Program Program RWE EraseT6 Program Program CMD Program RWE EraseT7 Program Program Program Program Erase Read

3) Program / Erase = On-going internal program or erase operations ? Bus is availablefor Reads or CMD

Notes:

Scenario #1 Scenario #2

1) Read or RWW/RWE (Read-W hile-W rite / Read-W hile-Erase) operation = Bus Cycle? Bus is busy2) CMD = Bus Cycle operation of 2-cycle commands: SETUP and CONFIRM ? Bus isbusy (meet all timing)

Table 35. Intel StrataFlash® Wireless Memory System (LV18 SCSP) Data Rates1, 2

Operation Single Word BufferedProgramming Buffered EFP

Erase

Main Block ParameterBlock

Device/Die KB/sec KB/sec KB/sec KB/sec KB/sec

1 23.5 188.2 200 128 80

2 47.1 376.5 400 256 160

3 70.6 564.7 600 384 240

4 94.1 752.9 800 512 320

NOTES:1. Device current is additive during concurrent operations. As additional operations are initiated in parallel,

the current for each additional device or die adds to the current consumed by any on-going operations.Adequate power supply current capacity (e.g., voltage regulator size), delivery, and noise decouplingmeasures must be implemented in the system design to ensure reliable concurrent device operations.

2. F-VPP = VPPH.

Datasheet 83

1024-Mbit LV Family

Appendix A Write State Machine (WSM) for Code Segment

The command state transitions (Next State Table) is based on incoming commands. Each partitionstays in its last read state (Read Array, Read Device ID, CFI Query or Read Status Register) until anew command changes it. The next WSM state does not depend on the partition’s output state. TheWrite State Machine Chip Next State Table (Code Segment) is TBD. For the code segment, onlyone partition can be actively programming or erasing at a time.

84 Datasheet

1024-Mbit LV Family

Appendix B Write State Machine (WSM) for Data Segment

The command state transitions (Next State Table) is based on incoming commands. Only one blockcan be actively programming or erasing at a time. Each block stays in its last read state (ReadArray, Read Device ID, CFI Query or Read Status Register) until a new command changes it. Thenext WSM state does not depend on the block’s output state. The Write State Machine Chip NextState Table (Code Segment) is TBD.

Datasheet 85

1024-Mbit LV Family

Appendix C Flowcharts

Figure 35. Word Program Flowchart

ProgramSuspend

Loop

Start

Write 0x40,Word Address

Write Data,Word Address

Read StatusRegister

SR[7] =

Full StatusCheck

(if desired)

ProgramComplete

Suspend?

1

0

No

Yes

WORD PROGRAM PROCEDURE

Repeat for subsequent Word Program operations.

Full Status Register check can be done after each program, orafter a sequence of program operations.

Write 0xFF after the last operation to set to the Read Arraystate.

CommentsBus

Operation Command

Data = 0x40Addr = Location to program

WriteProgram

Setup

Data = Data to programAddr = Location to programWrite Data

Status register dataRead None

Check SR[7]1 = WSM Ready0 = WSM Busy

Idle None

(Setup)

(Confirm)

FULL STATUS CHECK PROCEDURE

Read StatusRegister

ProgramSuccessful

SR[3] =

SR[1] =

0

0

SR[4] =

0

1

1

1 VP P RangeError

DeviceProtect Error

ProgramError

SR[3] MUST be cleared before the Write State Machine willallow further program attempts.

If an error is detected, clear the Status Register beforecontinuing operations - only the Clear Staus Registercommand clears the Status Register error bits.

Idle

Idle

BusOperation

None

None

Command

Check SR[3]:1 = V

P PError

Check SR[4]:1 = Data Program Error

Comments

Idle NoneCheck SR[1]:1 = Block locked; operation aborted

86 Datasheet

1024-Mbit LV Family

Figure 36. Program Suspend/Resume Flowchart

Read StatusRegister

SR.7 =

SR.2 =

Write FFhSusp Partition

Read ArrayData

ProgramCompleted

DoneReading

Write FFhPgm'd Partition

Write D0hAny Address

ProgramResumed

Read ArrayData

0

No

0

Yes

1

1

PROGRAM SUSPEND / RESUME PROCEDURE

WriteProgramResume

Data = D0hAddr = Suspended block (BA)

BusOperation Command Comments

WriteProgramSuspend

Data = B0hAddr = Block to suspend (BA)

StandbyCheck SR.71 = WSM ready0 = WSM busy

StandbyCheck SR.21 = Program suspended0 = Program completed

WriteReadArray

Data = FFhAddr = Any address within thesuspended partition

ReadRead array data from block other thanthe one being programmed

ReadStatus register dataAddr = Suspended block (BA)

PGM_SUS.WMF

Start

Write B0hAny Address

Program Suspend

Read Status

Program Resume Read Array

Read Array

Write 70hSame Partition Write Read

StatusData = 70hAddr = Same partition

If the suspended partition was placed in Read Array mode:

WriteReadStatus

Return partition to Status mode:Data = 70hAddr = Same partition

Write 70hSame Partition

Read Status

Datasheet 87

1024-Mbit LV Family

Figure 37. Buffered Programming Flowchart

Buffer Programming Procedure

Start

Get NextTarget Address

Issue Buffer Prog. Cmd.0xE8,

Word Address

Read Status Registerat Word Address

Write BufferAvailable?

SR[7] =

1 = Yes

DeviceSupports Buffer

Writes?

Set Timeout orLoop Counter

Timeoutor CountExpired?

Write Confirm 0xD0and Word Address

(Note 5)

Yes

No

Buffer Program Data,Start Word Address

X = 0

0 = NoYes

Use Single WordProgramming

Abort BufferProgram?

No

X = N?

Write Buffer Data,Word Address

X = X + 1

Write to anotherBlock Address

Buffer Program Aborted

No

Yes

Yes

Write Word Count,Word Address

SuspendProgram

Loop

Read Status Register(Note 7)

Is BP finished?SR[7] =

Full StatusCheck if Desired

Program Complete

SuspendProgram?

1=Yes

0=No Yes

No

Issue ReadStatus Register

Command

No

1. Word count value on D[7:0] is loaded into the word countregister. Count ranges for this device are N = 0x00 to 0x1F.2. The device outputs the Status Register when read.3. Write Buffer contents will be programmed at the issued wordaddress.4. Align the start address on a Write Buffer boundary formaximum programming performance (i.e., A[4:0] of the StartWord Address = 0x00).5. The Buffered Programming Confirm command must beissued to an address in the same block, for example, theoriginal Start Word Address, or the last address used during theloop that loaded the buffer data.6. The Status Register indicates an improper commandsequence if the Buffer Program command is aborted; use theClear Status Register command to clear error bits.7. The Status Register can be read from any addresses withinthe programming partition.

Full status check can be done after all erase and writesequences complete. Write 0xFF after the last operation toplace the partition in the Read Array state.

BusOperation

Idle

Read

Command

None

None

WriteBuffer Prog.

Setup

Read None

Idle None

Comments

Check SR[7]:1 = WSM Ready0 = WSM Busy

Status register DataAddr = Note 7

Data = 0xE8Addr = Word Address

SR[7] = ValidAddr = Word Address

Check SR[7]:1 = Write Buffer available0 = No Write Buffer available

Write(Notes 5, 6)

Buffer Prog.Conf.

Data = 0xD0Addr = Original Word Address

Write(Notes 1, 2)

NoneData = N-1 = Word CountN = 0 corresponds to count = 1Addr = Word Address

Write(Notes 3, 4)

NoneData = Write Buffer DataAddr = Start Word Address

Write(Note 3)

NoneData = Write Buffer DataAddr = Word Address

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ds

are

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rin

gth

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erio

d.)

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and

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read

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lock

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arti

tion

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88 Datasheet

1024-Mbit LV Family

Figure 38. Buffered EFP Flowchart

Write Data @ 1ST

Word Address

LastData?

Write 0xFFFF,Address Not within

Current Block

ProgramDone?

Read Status Reg.

Y

No (SR[7]=0)

Full Status CheckProcedure

ProgramComplete

Read Status Reg.

BEFPExited?

Yes (SR[7]=1)

Start

Write 0x80 @1ST Word Address

VPP applied,Block unlocked

Write 0xD0 @1ST Word Address

BEFP SetupDone?

Read Status Reg.

Exit

N

Program & Verify Phase Exit PhaseSetup Phase

BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE

X = 32?

Initialize Count:X = 0

Increment Count:X = X+1

Y

NOTES:1. First-word address to be programmed within the target blockmust be aligned on a write-buffer boundary.2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address;WSM internally increments addressing.

N

Check VPP, LockErrors (SR[3,1])

Yes (SR[7]=0)

CommentsBus

State Operation

BEFP setup delay

Data StreamReady?

Read Status Reg.

No (SR[0]=1)

Repeat for subsequent blocks;

After BEFP exit, a full Status Register check candetermine if any program error occurred;

See full Status Register check procedure in theWord Program flowchart.

Write 0xFF to enter Read Array state.

Check SR[7]:0 = Exit Not Completed1 = Exit Completed

Check ExitStatus

Read StatusRegister

Data = Status Reg. DataAddress = 1ST Word Addr

BEFP Exit

Standby

If SR[7] is set, check:SR[3] set = VPP ErrorSR[1] set = Locked Block

ErrorCondition

CheckStandby

Check SR[7]:0 = BEFP Ready1 = BEFP Not Ready

BEFPSetupDone?

Standby

Data = Status Reg. DataAddress = 1STWord Addr

StatusRegisterRead

Data = 0x80 @ 1ST WordAddress

BEFPConfirm

Write

Data = 0x80 @ 1ST WordAddress

BEFPSetup

Write(Note 1)

VPPH applied to VPPUnlockBlockWrite

BEFP Setup

BusState CommentsOperation

No (SR[0]=1)

Yes (SR[0]=0)

No (SR[7]=1)

Yes (SR[0]=0)

BEFP Program & Verify

CommentsBus State Operation

Write(Note 2)

LoadBuffer

Standby IncrementCount

Standby InitializeCount

Data = Data to ProgramAddress = 1ST Word Addr.

X = X+1

X = 0

Standby BufferFull?

X = 32?Yes = Read SR[0]No = Load Next Data Word

Read

Standby

StatusRegister

Data StreamReady?

Data = Status Register DataAddress = 1ST Word Addr.

Check SR[0]:0 = Ready for Data1 = Not Ready for Data

Read

Standby

Standby

Write

StatusRegister

ProgramDone?

LastData?

Exit Prog &Verify Phase

Data = Status Reg. dataAddress = 1ST Word Addr.

Check SR[0]:0 = Program Done1 = Program in Progress

No = Fill buffer againYes = Exit

Data = 0xFFFF @ address not incurrent block

Datasheet 89

1024-Mbit LV Family

Figure 39. Block Erase Flowchart

Start

FULL ERASE STATUS CHECK PROCEDURE

Repeat for subsequent block erasures.

Full Status register check can be done after each block eraseor after a sequence of block erasures.

Write 0xFF after the last operation to enter read array mode.

SR[1,3] must be cleared before the Write State Machine willallow further erase attempts.

Only the Clear Status Register command clears SR[1, 3, 4, 5].

If an error is detected, clear the Status register beforeattempting an erase retry or other error recovery.

No

SuspendErase

1

0

0

0

1

1,1

1

1

0 Yes

SuspendEraseLoop

0

Write 0x20,Block Address

Write 0xD0,Block Address

Read StatusRegister

SR[7] =

Full EraseStatus Check(if desired)

Block EraseComplete

Read StatusRegister

Block EraseSuccessful

SR[1] = Block LockedError

BLOCK ERASE PROCEDURE


WriteBlockEraseSetup

Data = 0x20Addr = Block to be erased (BA)

WriteErase

ConfirmData = 0xD0Addr = Block to be erased (BA)

Read None Status Register data.

Idle NoneCheck SR[7]:1 = WSM ready0 = WSM busy

BusOperation

Command Comments

SR[3] =V

PPRange

Error

SR[4,5] = CommandSequence Error

SR[5] =Block Erase

Error

Idle NoneCheck SR[3]:1 = VP P Range Error

Idle None Check SR[4,5]:Both 1 = Command Sequence Error

Idle NoneCheck SR[5]:1 = Block Erase Error

Idle NoneCheck SR[1]:1 = Attempted erase of locked block;

erase aborted.

(Block Erase)

(Erase Confirm)

90 Datasheet

1024-Mbit LV Family

Figure 40. Erase Suspend/Resume Flowchart

EraseCompleted

Read ArrayData

0

0

No

Read

1

Program

ProgramLoop

Read ArrayData

1

Start

Read StatusRegister

SR[7] =

SR[6] =

EraseResumed

Read orProgram?

Done

Write

Write

Idle

Idle

Write

EraseSuspend

Read Arrayor Program

None

None

ProgramResume

Data = 0xB0Addr = Same partition address asabove

Data = 0xFF or 0x40Addr = Any address within thesuspended partition

Check SR[7]:1 = WSM ready0 = WSM busy

Check SR[6]:1 = Erase suspended0 = Erase completed

Data = 0xD0Addr = Any address

BusOperation

Command Comments

Read None Status Register data.Addr = Same partition

Read orWrite None

Read array or program data from/toblock other than the one being erased

ERASE SUSPEND / RESUME PROCEDURE

If the suspended partition was placed inRead Array mode or a Program Loop:

Write 0xB0,Any Address

(Erase Suspend)

Write 0x70,Same Partition

(Read Status)

Write 0xD0,Any Address(Erase Resume)

Write 0x70,Same Partition

(Read Status)

Write 0xFF,Erased Partition

(Read Array)

Write ReadStatus

Data = 0x70Addr = Any partition address

WriteReadStatus

Register

Return partition to Status mode:Data = 0x70Addr = Same partition

Datasheet 91

1024-Mbit LV Family

Figure 41. Block Lock Operations Flowchart

No

Start

Write 0x60,Block Address

Write 0x90

Read BlockLock Status

LockingChange?

Lock ChangeComplete

Write either0x01/0xD0/0x2F,Block Address

Write 0xFFPartition Address

Yes

Write

Write

Write(Optional)

Read(Optional)

Idle

Write

LockSetup

Lock,Unlock, orLock-Down

Confirm

ReadDevice ID

Block LockStatus

None

ReadArray

Data = 0x60Addr = Block to lock/unlock/lock-down

Data = 0x01 (Block Lock)0xD0 (Block Unlock)0x2F (Lock-Down Block)

Addr = Block to lock/unlock/lock-down

Data = 0x90Addr = Block address + offset 2

Block Lock status dataAddr = Block address + offset 2

Confirm locking change on D[1,0].

Data = 0xFFAddr = Block address

BusOperation

Command Comments

LOCKING OPERATIONS PROCEDURE

(Lock Confirm)

(Read Device ID)

(Read Array)

Opt

iona

l

(Lock Setup)

92 Datasheet

1024-Mbit LV Family

Figure 42. Protection Register Programming Flowchart

FULL STATUS CHECK PROCEDURE

Program Protection Register operation addresses must bewithin the Protection Register address space. Addressesoutside this space will return an error.

Repeat for subsequent programming operations.

Full Status Register check can be done after each program, orafter a sequence of program operations.

Write 0xFF after the last operation to set Read Array state.

SR[3] must be cleared before the Write State Machine willallow further program attempts.

Only the Clear Staus Register command clears SR[1, 3, 4].

If an error is detected, clear the Status register beforeattempting a program retry or other error recovery.

1

0

1

1

1

PROTECTION REGISTER PROGRAMMING PROCEDURE

Start

Write 0xC0,PR Address

Write PRAddress & Data

Read StatusRegister

SR[7] =

Full StatusCheck

(if desired)

ProgramComplete

Read StatusRegister Data

ProgramSuccessful

SR[3] =

SR[4] =

SR[1] =

VPP

Range Error

Program Error

Register Locked;Program Aborted

Idle

Idle

BusOperation

None

None

Command

Check SR[3]:1 = VP P Range Error

Check SR[4]:1 = Programming Error

Comments

Write

Write

Idle

ProgramPR Setup

ProtectionProgram

None

Data = 0xC0Addr = First Location to Program

Data = Data to ProgramAddr = Location to Program

Check SR[7]:1 = WSM Ready0 = WSM Busy


Read None Status Register Data.

Idle NoneCheck SR[1]:1 = Block locked; operation aborted

(Program Setup)

(Confirm Data)

0

0

0

Datasheet 93

1024-Mbit LV Family

Appendix D Common Flash Interface (CFI) for Code Segment

The Common Flash Interface (CFI) is part of an overall specification for multiple command-setand control-interface descriptions. This appendix describes the database structure containing thedata returned by a read operation after issuing the CFI Query command (see Section 9.2, “FlashDevice Commands” on page 47 and Section 9.3, “Command Definitions” on page 49). Systemsoftware can parse this database structure to obtain information about the flash device, such asblock size, density, bus width, and electrical specifications. The system software will then knowwhich command set(s) to use to properly perform flash writes, block erases, reads and otherwisecontrol the flash device.

D.1 Query Structure Output

The Query database allows system software to obtain information for controlling the flash device.This section describes the device’s CFI-compliant interface that allows access to Query data.

Query data are presented on the lowest-order data outputs (DQ[7:0]) only. The numerical offsetvalue is the address relative to the maximum bus width supported by the device. On this family ofdevices, the Query table device starting address is a 10h, which is a word address for x16 devices.

For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear onthe low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upperbytes. The device outputs ASCII “Q” in the low byte (DQ[7:0]) and 00h in the high byte(DQ[15:8]).

At Query addresses containing two or more bytes of information, the least significant data byte ispresented at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always“00h,” the leading “00” has been dropped from the table notation and only the lower byte value isshown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.

Table 36. Summary of Query Structure Output as a Function of Device and Mode

DeviceHex

OffsetHex

CodeASCIIValue

00010: 51 "Q"Device Addresses 00011: 52 "R"

00012: 59 "Y"

94 Datasheet

1024-Mbit LV Family

Table 37. Example of Query Structure Output of x16- Devices

D.2 Query Structure Overview

The Query command causes the flash component to display the Common Flash Interface (CFI)Query structure or “database.” The structure sub-sections and address locations are summarizedbelow.

Table 38. Query Structure

NOTES:1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is

32K-word).3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.

Word Addressing:Offset Hex Code ValueAX–A0 D15–D0

00010h 0051 "Q"00011h 0052 "R"00012h 0059 "Y"00013h P_IDLO PrVendor00014h P_IDHI ID #00015h PLO PrVendor00016h PHI TblAdr00017h A_IDLO AltVendor00018h A_IDHI ID #

... ... ...

Offset Sub-Section Name Description(1)

00000h Manufacturer Code00001h Device Code(BA+2)h(2) Block Status register Block-specific information00004-Fh Reserved Reserved for vendor-specific information00010h CFI query identification string Command set IDand vendor data offset0001Bh System interface information Device timing & voltage information00027h Device geometry definition Flash device layout

P(3) Vendor-defined additional information specificto the Primary Vendor Algorithm

Primary Intel-specific ExtendedQuery Table

Datasheet 95

1024-Mbit LV Family

D.3 Block Status Register

The Block Status Register indicates whether an erase operation completed successfully or whethera given block is locked or can be accessed for flash program/erase operations.

Block Erase Status (BSR.1) allows system software to determine the success of the last block eraseoperation. BSR.1 can be used just after power-up to verify that the F-VCC supply was notaccidentally removed during an erase operation. Only issuing another operation to the block resetsthis bit. The Block Status Register is accessed from word address 02h within each block.

Table 39. Block Status Register

NOTE:1. BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64KB block) beginning location in

word mode)

Offset Length Description Add. ValueBlock Lock Status Register BA+2 --00 or --01

BA+2 (bit 0): 0 or 1

BA+2 (bit 1): 0 or 1

BSR2–7: Reserved for future use BA+2 (bit 2–7): 0

BSR.0 Block lock status0 = Unlocked1 = Locked

BSR.1 Block lock-down status0 = Not locked down1 = Locked down

(BA+2)h(1) 1

96 Datasheet

1024-Mbit LV Family

D.4 CFI Query Identification String

The Identification String provides verification that the component supports the Common FlashInterface specification. It also indicates the specification version and supported vendor-specifiedcommand set(s).

Table 40. CFI Identification

Table 41. System Interface Information

Offset Length DescriptionAdd.

HexCode Value

10h 3 Query-unique ASCII string “QRY“ 10: --51 "Q"11: --52 "R"12: --59 "Y"

13h 2 Primary vendor command set and control interface ID code. 13: --0116-bit ID code for vendor-specified algorithms 14: --00

15h 2 Extended Query Table primary algorithm address 15: --0A16: --01

17h 2 Alternate vendor command set and control interface ID code. 17: --000000h means no second vendor-specified algorithm exists 18: --00

19h 2 Secondary algorithm Extended Query Table address. 19: --000000h means none exists 1A: --00


HexCode Value

1Bh 1 1B: --17 1.7V

1Ch 1 1C: --20 2.0V

1Dh 1 1D: --85 8.5V

1Eh 1 1E: --95 9.5V

1Fh 1 “n” such that typical single word program time-out = 2n µ-sec 1F: --08 256µs20h 1 “n” such that typical max. buffer write time-out = 2n µ-sec 20: --09 512µs21h 1 “n” such that typical block erase time-out = 2n m-sec 21: --0A 1s22h 1 “n” such that typical full chip erase time-out = 2n m-sec 22: --00 NA23h 1 “n” such that maximum word program time-out = 2n times typical 23: --01 512µs24h 1 “n” such that maximum buffer write time-out = 2n times typical 24: --01 1024µs25h 1 “n” such that maximum block erase time-out = 2n times typical 25: --02 4s26h 1 “n” such that maximum chip erase time-out = 2n times typical 26: --00 NA

VCC logic supply minimum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 BCD volts

VCC logic supply maximum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 BCD volts

VPP [programming] supply minimum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 HEX volts

VPP [programming] supply maximum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 HEX volts

Datasheet 97

1024-Mbit LV Family

D.5 Device Geometry Definition

Table 42. Device Geometry Definition

Table 43. Device Geometry Definition Code

Offset Length Description Code27h 1 “n” such that device size = 2n in number of bytes 27: See table below

7 6 5 4 3 2 1 0

28h 2 — — — — x64 x32 x16 x8 28: --01 x1615 14 13 12 11 10 9 8

— — — — — — — — 29: --002Ah 2 “n” such that maximum number of bytes in write buffer = 2n 2A: --06 64

2B: --002Ch 1 2C:

2Dh 4 Erase Block Region 1 Information 2D:bits 0–15 = y, y+1 = number of identical-size erase blocks 2E:bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F:

30:31h 4 Erase Block Region 2 Information 31:

bits 0–15 = y, y+1 = number of identical-size erase blocks 32:bits 16–31 = z, region erase block(s) size are z x 256 bytes 33:

34:35h 4 Reserved for future erase block region information 35:

36:37:38:

Flash device interface code assignment:"n" such that n+1 specifies the bit field that represents the flashdevice width capabilities as described in the table:

Number of erase block regions (x) within device:1. x = 0 means no erase blocking; the device erases in bulk2. x specifies the number of device regions with one or

more contiguous same-size erase blocks.3. Symmetrically blocked partitions have one blocking region

See table below

See table below

See table below

See table below

Address–B –T –B –T

27: --18 --18 --19 --1928: --01 --01 --01 --0129: --00 --00 --00 --002A: --06 --06 --06 --062B: --00 --00 --00 --002C: --02 --02 --02 --022D: --03 --7E --03 --FE2E: --00 --00 --00 --002F: --80 --00 --80 --0030: --00 --02 --00 --0231: --7E --03 --FE --0332: --00 --00 --00 --0033: --00 --80 --00 --8034: --02 --00 --02 --0035: --00 --00 --00 --0036: --00 --00 --00 --0037: --00 --00 --00 --0038: --00 --00 --00 --00

128 Mbit 256 Mbit

98 Datasheet

1024-Mbit LV Family

D.6 Intel-Specific Extended Query Table

Table 44. Primary Vendor-Specific Extended Query

NOTE: The variable P is a pointer which is defined at CFI offset 15h.

Offset(1) Length Description HexP = 10Ah (Optional flash features and commands) Add. Code Value(P+0)h 3 Primary extended query table 10A --50 "P"(P+1)h Unique ASCII string “PRI“ 10B: --52 "R"(P+2)h 10C: --49 "I"(P+3)h 1 Major version number, ASCII 10D: --31 "1"(P+4)h 1 Minor version number, ASCII 10E: --33 "3"(P+5)h 4 Optional feature and command support (1=yes, 0=no) 10F: --E6(P+6)h bits 10–31 are reserved; undefined bits are “0.” If bit 31 is 110: --03(P+7)h “1” then another 31 bit field of Optional features follows at 111: --00(P+8)h the end of the bit–30 field. 112: --00

bit 0 Chip erase supported bit 0 = 0 Nobit 1 Suspend erase supported bit 1 = 1 Yesbit 2 Suspend program supported bit 2 = 1 Yesbit 3 Legacy lock/unlock supported bit 3 = 0 Nobit 4 Queued erase supported bit 4 = 0 Nobit 5 Instant individual block locking supported bit 5 = 1 Yesbit 6 Protection bits supported bit 6 = 1 Yesbit 7 Pagemode read supported bit 7 = 1 Yesbit 8 Synchronous read supported bit 8 = 1 Yesbit 9 Simultaneous operations supported bit 9 = 1 Yes

(P+9)h 1 113: --01

bit 0 Program supported after erase suspend bit 0 = 1 Yes(P+A)h 2 Block status register mask 114: --03(P+B)h bits 2–15 are Reserved; undefined bits are “0” 115: --00

bit 0 Block Lock-Bit Status register active bit 0 = 1 Yesbit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes

(P+C)h 1 116: --18 1.8V

(P+D)h 1 117: --90 9.0V

Supported functions after suspend: read Array, Status, QueryOther supported operations are:bits 1–7 reserved; undefined bits are “0”

VCC logic supply highest performance program/erase voltagebits 0–3 BCD value in 100 mVbits 4–7 BCD value in volts

VPP optimum program/erase supply voltagebits 0–3 BCD value in 100 mVbits 4–7 HEX value in volts

Datasheet 99

1024-Mbit LV Family

Table 45. Protection Register Information


Offset(1) Length Description HexP = 10Ah (Optional flash features and commands) Add. Code Value(P+E)h 1 118: --02 2

(P+F)h 4 Protection Field 1: Protection Description 119: --80 80h(P+10)h This field describes user-available One Time Programmable 11A: --00 00h(P+11)h (OTP) Protection register bytes. Some are pre-programmed 11B: --03 8 byte(P+12)h 11C: --03 8 byte

(P+13)h 10 Protection Field 2: Protection Description 11D: --89 89h(P+14)h 11E: --00 00h(P+15)h 11F: --00 00h(P+16)h 120: --00 00h(P+17)h 121: --00 0(P+18)h bits 40–47 = “n” ∴ n = factory pgm'd groups (high byte) 122: --00 0(P+19)h 123: --00 0(P+1A)h 124: --10 16(P+1B)h 125: --00 0(P+1C)h 126: --04 16

Number of Protection register fields in JEDEC ID space.“00h,” indicates that 256 protection fields are available

with device-unique serial numbers. Others are userprogrammable. Bits 0–15 point to the Protection register Lockbyte, the section’s first byte. The following bytes are factory pre-programmed and user-programmable.

bits 0–7 = Lock/bytes Jedec-plane physical low addressbits 8–15 = Lock/bytes Jedec-plane physical high address

bits 16–23 = “n” such that 2n = factory pre-programmed bytesbits 24–31 = “n” such that 2n = user programmable bytes

Bits 0–31 point to the Protection register physical Lock-wordaddress in the Jedec-plane.Following bytes are factory or user-programmable.

bits 32–39 = “n” ∴ n = factory pgm'd groups (low byte)

bits 48–55 = “n” \ 2n = factory programmable bytes/groupbits 56–63 = “n” ∴ n = user pgm'd groups (low byte)bits 64–71 = “n” ∴ n = user pgm'd groups (high byte)bits 72–79 = “n” ∴ 2n = user programmable bytes/group

100 Datasheet

1024-Mbit LV Family

Table 46. Burst Read Information


Offset(1) Length Description HexP = 10Ah (Optional flash features and commands) Add. Code Value(P+1D)h 1 127: --03 8 byte

(P+1E)h 1 128: --04 4

(P+1F)h 1 129: --01 4

(P+20)h 1 Synchronous mode read capability configuration 2 12A: --02 8(P+21)h 1 Synchronous mode read capability configuration 3 12B: --03 16(P+22)h 1 Synchronous mode read capability configuration 4 12C: --07 Cont

Page Mode Read capability

bits 0–7 = “n” such that 2n HEX value represents the number ofread-page bytes. See offset 28h for device word width todetermine page-mode data output width. 00h indicates noread page buffer.

Number of synchronous mode read configuration fields that follow.00h indicates no burst capability.Synchronous mode read capability configuration 1

Bits 3–7 = Reserved

bits 0–2 “n” such that 2n+1 HEX value represents themaximum number of continuous synchronous reads whenthe device is configured for its maximum word width. A valueof 07h indicates that the device is capable of continuouslinear bursts that will output data until the internal burstcounter reaches the end of the device’s burstable addressspace. This field’s 3-bit value can be written directly to theRead Configuration Register bits 0–2 if the device isconfigured for its maximum word width. See offset 28h forword width to determine the burst data output width.

Datasheet 101

1024-Mbit LV Family

Table 47. Partition and Erase-block Region 1 Information

Offset(1) See table belowP = 10Ah Description Address

Bottom Top (Optional flash features and commands) Len Bot Top

Partition Region 1 Information(P+24)h (P+24)h Number of identical partitions within the partition region 2 12E: 12E:(P+25)h (P+25)h 12F: 12F:(P+26)h (P+26)h 1 130: 130:

(P+27)h (P+27)h 1 131: 131:

(P+28)h (P+28)h 1 132: 132:

(P+29)h (P+29)h 1 133: 133:

(P+2A)h (P+2A)h Partition Region 1 Erase Block Type 1 Information 4 134: 134:(P+2B)h (P+2B)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition 135: 135:(P+2C)h (P+2C)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 136: 136:(P+2D)h (P+2D)h 137: 137:(P+2E)h (P+2E)h Partition 1 (Erase Block Type 1) 2 138: 138:(P+2F)h (P+2F)h Minimum block erase cycles x 1000 139: 139:(P+30)h (P+30)h 1 13A: 13A:

(P+31)h (P+31)h 1 13B: 13B:

(P+32)h Partition Region 1 Erase Block Type 2 Information 4 13C:(P+33)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition 13D:(P+34)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 13E:(P+35)h (bottom parameter device only) 13F:(P+36)h Partition 1 (Erase block Type 2) 2 140:(P+37)h Minimum block erase cycles x 1000 141:

(P+38)h 1 142:

(P+39)h 1 143:

Number of program or erase operations allowed in a partitionbits 0–3 = number of simultaneous Program operationsbits 4–7 = number of simultaneous Erase operations

Simultaneous program or erase operations allowed in otherpartitions while a partition in this region is in Program mode

bits 0–3 = number of simultaneous Program operationsbits 4–7 = number of simultaneous Erase operations

Simultaneous program or erase operations allowed in otherpartitions while a partition in this region is in Erase mode


Types of erase block regions in this Partition Region.x = 0 = no erase blocking; the Partition Region erases in bulkx = number of erase block regions w/ contiguous same-sizeerase blocks. Symmetrically blocked partitions have oneblocking region. Partition size = (Type 1 blocks)x(Type 1block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+(Type n blocks)x(Type n block sizes)

Partition 1 (erase block Type 1) bits per cell; internal ECCbits 0–3 = bits per cell in erase regionbit 4 = reserved for “internal ECC used” (1=yes, 0=no)bits 5–7 = reserve for future use

Partition 1 (erase block Type 1) page mode and synchronousmode capabilities defined in Table 10.

bit 0 = page-mode host reads permitted (1=yes, 0=no)bit 1 = synchronous host reads permitted (1=yes, 0=no)bit 2 = synchronous host writes permitted (1=yes, 0=no)bits 3–7 = reserved for future use

Partition 1 (Erase block Type 2) bits per cellbits 0–3 = bits per cell in erase regionbit 4 = reserved for “internal ECC used” (1=yes, 0=no)bits 5–7 = reserve for future use

Partition 1 (Erase block Type 2) pagemode and synchronousmode capabilities defined in Table 10


102 Datasheet

1024-Mbit LV Family

Table 48. Partition and Erase-block Region 2 Information

Offset(1) See table belowP = 10Ah Description Address

Bottom Top (Optional flash features and commands) Len Bot Top

(P+3A)h (P+32)h Number of identical partitions within the partition region 2 144: 13C:(P+3B)h (P+33)h 145: 13D:(P+3C)h (P+34)h 1 146: 13E:

(P+3D)h (P+35)h 1 147: 13F:

(P+3E)h (P+36)h 1 148: 140:

(P+3F)h (P+37)h 1 149: 141:

(P+40)h (P+38)h Partition Region 2 Erase Block Type 1 Information 4 14A: 142:(P+41)h (P+39)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition 14B: 143:(P+42)h (P+3A)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 14C: 144:(P+43)h (P+3B)h 14D: 145:(P+44)h (P+3C)h Partition 2 (Erase block Type 1) 2 14E: 146:(P+45)h (P+3D)h Minimum block erase cycles x 1000 14F: 147:(P+46)h (P+3E)h 1 150: 148:

(P+47)h (P+3F)h 1 151: 149:

(P+40)h Partition Region 2 Erase Block Type 2 Information 4 14A:(P+41)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition 14B:(P+42)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 14C:(P+43)h 14D:(P+44)h Partition 2 (Erase block Type 2) 2 14E:(P+45)h Minimum block erase cycles x 1000 14F:(P+46)h 1 150:

(P+47)h 1 151:

Number of program or erase operations allowed in a partitionbits 0–3 = number of simultaneous Program operationsbits 4–7 = number of simultaneous Erase operations

Simultaneous program or erase operations allowed in otherpartitions while a partition in this region is in Program mode


Simultaneous program or erase operations allowed in otherpartitions while a partition in this region is in Erase mode


Types of erase block regions in this Partition Region.x = 0 = no erase blocking; the Partition Region erases in bulkx = number of erase block regions w/ contiguous same-sizeerase blocks. Symmetrically blocked partitions have oneblocking region. Partition size = (Type 1 blocks)x(Type 1block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+(Type n blocks)x(Type n block sizes)


Partition 2 (erase block Type 1) pagemode and synchronousmode capabilities as defined in Table 10.



Partition 2 (erase block Type 2) pagemode and synchronousmode capabilities as defined in Table 10.


Datasheet 103

1024-Mbit LV Family

Table 49. Partition and Erase-block Region Information


12D: --02 --02 --02 --0212E: --01 --0F --01 --0F12F: --00 --00 --00 --00130: --11 --11 --11 --11131: --00 --00 --00 --00132: --00 --00 --00 --00133: --02 --01 --02 --01134: --03 --07 --03 --0F135: --00 --00 --00 --00136: --80 --00 --80 --00137: --00 --02 --00 --02138: --64 --64 --64 --64139: --00 --00 --00 --0013A: --02 --02 --02 --0213B: --03 --03 --03 --0313C: --06 --01 --0E --0113D: --00 --00 --00 --0013E: --00 --11 --00 --1113F: --02 --00 --02 --00140: --64 --00 --64 --00141: --00 --02 --00 --02142: --02 --06 --02 --0E143: --03 --00 --03 --00144: --0F --00 --0F --00145: --00 --02 --00 --02146: --11 --64 --11 --64147: --00 --00 --00 --00148: --00 --02 --00 --02149: --01 --03 --01 --0314A: --07 --03 --0F --0314B: --00 --00 --00 --0014C: --00 --80 --00 --8014D: --02 --00 --02 --0014E: --64 --64 --64 --6414F: --00 --00 --00 --00150: --02 --02 --02 --02151: --03 --03 --03 --03

128 Mbit 256 Mbit

104 Datasheet

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Appendix E Common Flash Interface (CFI) for Data Segment

E.1 Query Structure Output

Table 50. Summary of Query Structure Output as a Function of Device and Mode

Table 51. Example of Query Structure Output of x16- Devices

E.2 Query Structure Overview

The Query command causes the flash component to display the Common Flash Interface (CFI)Query structure or “database.” The structure sub-sections and address locations are summarizedbelow.

Table 52. Query Structure

NOTES:1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is

32K-word).3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.

DeviceHex

OffsetHex

CodeASCIIValue

00010: 51 "Q"Device Addresses 00011: 52 "R"

00012: 59 "Y"

Word Addressing:Offset Hex Code ValueAX–A0 D15–D0

00010h 0051 "Q"00011h 0052 "R"00012h 0059 "Y"00013h P_IDLO PrVendor00014h P_IDHI ID #00015h PLO PrVendor00016h PHI TblAdr00017h A_IDLO AltVendor00018h A_IDHI ID #

... ... ...

Offset Sub-Section Name Description(1)

00000h Manufacturer Code00001h Device Code(BA+2)h(2) Block Status register Block-specific information00004-Fh Reserved Reserved for vendor-specific information00010h CFI query identification string Command set IDand vendor data offset0001Bh System interface information Device timing & voltage information00027h Device geometry definition Flash device layout

P(3) Vendor-defined additional information specificto the Primary Vendor Algorithm

Primary Intel-specific ExtendedQuery Table

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1024-Mbit LV Family

E.3 Block Status Register

The Block Status Register indicates whether an erase operation completed successfully or whethera given block is locked or can be accessed for flash program/erase operations.

Block Erase Status (BSR.1) allows system software to determine the success of the last block eraseoperation. BSR.1 can be used just after power-up to verify that the F-VCC supply was notaccidentally removed during an erase operation. Only issuing another operation to the block resetsthis bit. The Block Status Register is accessed from word address 02h within each block.

Table 53. Block Status Register

NOTE: BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64KB block) beginninglocation in word mode)

Offset Length Description Add. ValueBlock Lock Status Register BA+2 --00 or --01

BA+2 (bit 0): 0 or 1

BA+2 (bit 1): 0 or 1

BSR2–7: Reserved for future use BA+2 (bit 2–7): 0

BSR.0 Block lock status0 = Unlocked1 = Locked

BSR.1 Block lock-down status0 = Not locked down1 = Locked down

(BA+2)h(1) 1

106 Datasheet

1024-Mbit LV Family

E.4 CFI Query Identification String

The Identification String provides verification that the component supports the Common FlashInterface specification. It also indicates the specification version and supported vendor-specifiedcommand set(s).

Table 54. CFI Identification

Table 55. System Interface Information


HexCode Value

10h 3 Query-unique ASCII string “QRY“ 10: --51 "Q"11: --52 "R"12: --59 "Y"

13h 2 Primary vendor command set and control interface ID code. 13: --0116-bit ID code for vendor-specified algorithms 14: --00

15h 2 Extended Query Table primary algorithm address 15: --3516: --00

17h 2 Alternate vendor command set and control interface ID code. 17: --000000h means no second vendor-specified algorithm exists 18: --00

19h 2 Secondary algorithm Extended Query Table address. 19: --000000h means none exists 1A: --00


HexCode Value

1Bh 1 1B: --17 1.7V

1Ch 1 1C: --20 2.0V

1Dh 1 1D: --85 8.5V

1Eh 1 1E: --95 9.5V

1Fh 1 “n” such that typical single word program time-out = 2n µ-sec 1F: --08 256µs20h 1 “n” such that typical max. buffer write time-out = 2n µ-sec 20: --09 512µs21h 1 “n” such that typical block erase time-out = 2n m-sec 21: --0A 1s22h 1 “n” such that typical full chip erase time-out = 2n m-sec 22: --00 NA23h 1 “n” such that maximum word program time-out = 2n times typical 23: --01 512µs24h 1 “n” such that maximum buffer write time-out = 2n times typical 24: --01 1024µs25h 1 “n” such that maximum block erase time-out = 2n times typical 25: --02 4s26h 1 “n” such that maximum chip erase time-out = 2n times typical 26: --00 NA

VCC logic supply minimum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 BCD volts

VCC logic supply maximum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 BCD volts

VPP [programming] supply minimum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 HEX volts

VPP [programming] supply maximum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 HEX volts

Datasheet 107

1024-Mbit LV Family

E.5 Device Geometry Definition

Table 56. Device Geometry Definition

Table 57. Device Geometry Definition Code

Offset Length Description Code27h 1 “n” such that device size = 2n in number of bytes 27: See table below

7 6 5 4 3 2 1 0

28h 2 — — — — x64 x32 x16 x8 28: --01 x1615 14 13 12 11 10 9 8

— — — — — — — — 29: --002Ah 2 “n” such that maximum number of bytes in write buffer = 2n 2A: --06 64

2B: --002Ch 1 2C:

2Dh 4 Erase Block Region 1 Information 2D:bits 0–15 = y, y+1 = number of identical-size erase blocks 2E:bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F:

30:31h 4 Erase Block Region 2 Information 31:

bits 0–15 = y, y+1 = number of identical-size erase blocks 32:bits 16–31 = z, region erase block(s) size are z x 256 bytes 33:

34:35h 4 Reserved for future erase block region information 35:

36:37:38:

Flash device interface code assignment:"n" such that n+1 specifies the bit field that represents the flashdevice width capabilities as described in the table:

Number of erase block regions (x) within device:1. x = 0 means no erase blocking; the device erases in bulk2. x specifies the number of device regions with one or

more contiguous same-size erase blocks.3. Symmetrically blocked partitions have one blocking region

See table below

See table below

See table below

See table below


27: --18 --18 --19 --1928: --01 --01 --01 --0129: --00 --00 --00 --002A: --06 --06 --06 --062B: --00 --00 --00 --002C: --02 --02 --02 --022D: --03 --7E --03 --FE2E: --00 --00 --00 --002F: --80 --00 --80 --0030: --00 --02 --00 --0231: --7E --03 --FE --0332: --00 --00 --00 --0033: --00 --80 --00 --8034: --02 --00 --02 --00

128 Mbit 256 Mbit

108 Datasheet

1024-Mbit LV Family

E.6 Intel-Specific Extended Query Table

Table 58. Primary Vendor-Specific Extended Query


Table 59. Page Read Information


Offset(1) Length Description HexP = 35h (Optional flash features and commands) Add. Code Value(P+0)h 3 Primary extended query table 35 --50 "P"(P+1)h Unique ASCII string “PRI“ 036: --52 "R"(P+2)h 037: --49 "I"(P+3)h 1 Major version number, ASCII 038: --31 "1"(P+4)h 1 Minor version number, ASCII 039: --33 "3"(P+5)h 4 Optional feature and command support (1=yes, 0=no) 03A: --A6(P+6)h bits 10–31 are reserved; undefined bits are “0.” If bit 31 is 03B: --00(P+7)h “1” then another 31 bit field of Optional features follows at 03C: --00(P+8)h the end of the bit–30 field. 03D: --00

bit 0 Chip erase supported bit 0 = 0 Nobit 1 Suspend erase supported bit 1 = 1 Yesbit 2 Suspend program supported bit 2 = 1 Yesbit 3 Legacy lock/unlock supported bit 3 = 0 Nobit 4 Queued erase supported bit 4 = 0 Nobit 5 Instant individual block locking supported bit 5 = 1 Yesbit 6 Protection bits supported bit 6 = 0 Nobit 7 Pagemode read supported bit 7 = 1 Yesbit 8 Synchronous read supported bit 8 = 0 Nobit 9 Simultaneous operations supported bit 9 = 0 No

(P+9)h 1 03E: --01

bit 0 Program supported after erase suspend bit 0 = 1 Yes(P+A)h 2 Block status register mask 03F: --03(P+B)h bits 2–15 are Reserved; undefined bits are “0” 040: --00

bit 0 Block Lock-Bit Status register active bit 0 = 1 Yesbit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes

(P+C)h 1 041: --18 1.8V

(P+D)h 1 042: --90 9.0V

Supported functions after suspend: read Array, Status, QueryOther supported operations are:bits 1–7 reserved; undefined bits are “0”

VCC logic supply highest performance program/erase voltagebits 0–3 BCD value in 100 mVbits 4–7 BCD value in volts

VPP optimum program/erase supply voltagebits 0–3 BCD value in 100 mVbits 4–7 HEX value in volts

Offset(1) Length Description HexP = 35h (Optional flash features and commands) Add. Code Value(P+E)h 1 043: --03 8 byte

(P+F)h 1 044: --00 0Number of synchronous mode read configuration fields thatfollow. 00h indicates no burst capability.

Page Mode Read capability

bits 0–7 = “n” such that 2n HEX value represents the number ofread-page bytes. See offset 28h for device word width todetermine page-mode data output width. 00h indicates noread page buffer.

Datasheet 109

1024-Mbit LV Family

Appendix F Additional Information

Order/DocumentNumber Document/Tool

Datasheets

253852 Intel StrataFlash® Wireless Memory System (L18/L30 SCSP); 768-Mbit LVQ Familywith Asynchronous Static RAM

253853 Intel StrataFlash® Wireless Memory System(L18/L30 SCSP); 1024-Mbit LVX Familywith Dynamic RAM

Application Notes

253856 Concurrent Program and Erase Using the Intel StrataFlash® Wireless Memory System(L18/L30 SCSP)

292221 AP-663 Using the Intel StrataFlash® memory write buffer®

292286 AP-738 Reduce Manufacturing Costs with Intel® Flash Memory Enhanced FactoryProgramming

251237 AP-759 Intel® Flash Memory Programming Algorithm Optimizations

297769 AP-678 Improving Programming Throughput of Automated Flash Memories

292186 AP-630 Designing for On-Board Programming Using IEEE1149.1 (JTAG) Access Port

292185 AP-629 Simplifying Manufacturing by Using Automatic Test Equipment for On-BoardProgramming

Software

297833 Intel® Flash Data Integrator (FDI) User’s Guide

298136 Intel® Persistent Storage Manager (PSM)

298132 Intel® Virtual Small Block File Manager (VFM)

User’s Guides

298161 Intel® Flash Memory Chip Scale Package User’s Guide

NOTES:1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.3. For the most current information on Intel StrataFlash® Wireless Memory System, visit our website at http://

developer.intel.com/design/flcomp/prodbref/253528.htm.

110 Datasheet

1024-Mbit LV Family

Appendix G Ordering Information

Table 60, “Ordering Information: Available 1024-Mbit LV Family Matrix (Flash only)” shows theordering information for the LVX family. The figures and tables listed here show the decoderinformation for the Flash + RAM combinations in the LVX family.

• Figure 43, “Decoder for Flash Code and Data SCSP Combinations”

• Table 61, “38F and 48F Product Density Decoder” on page 112

Table 60. Ordering Information: Available 1024-Mbit LV Family Matrix (Flash only)

LVFamily

I/OVoltage Code segment flash die Data segment flash die Package

SizePackageBall Type Valid Order Number

LVQ

1.8 V

256L18 256V18 8x11x1.2 Leaded RD48F4040LVYTQ0

256L18 256V18 8x11x1.2 Leaded RD48F4040LVYBQ0

256L18 256V18 8x11x1.2 Lead-Free PF48F4040LVYTQ0

256L18 256V18 8x11x1.2 Lead-Free PF48F4040LVYBQ0

256L18 + 256L18 256V18 8x11x1.4 Leaded RD48F4440LVYTQ0

256L18 + 256L18 256V18 8x11x1.4 Leaded RD48F4440LVYBQ0

256L18 256V18 + 256V18 8x11x1.4 Leaded RD48F4044LVYTQ0

256L18 256V18 + 256V18 8x11x1.4 Leaded RD48F4044LVYBQ0

3.0 V

256L30 256V30 8x11x1.2 Leaded RD48F4040LVZTQ0

256L30 256V30 8x11x1.2 Leaded RD48F4040LVZBQ0

256L30 256V30 + 256V30 8x11x1.4 Leaded RD48F4044LVZTQ0

256L30 256V30 + 256V30 8x11x1.4 Leaded RD48F4044LVZBQ0

LVX

1.8 V256L18 + 256L18 256V18 + 256V18 11x11x1.4 Leaded RD48F4444LVYTB0

256L18 + 256L18 256V18 + 256V18 11x11x1.4 Leaded RD48F4444LVYBB0

3.0 V256L30 + 256L30 256V30 + 256V30 11x11x1.4 Leaded RD48F4444LVZTB0

256L30 + 256L30 256V30 + 256V30 11x11x1.4 Leaded RD48F4444LVZBB0

NOTE: For product combination not listed, please contact your local Intel representative for details.

Datasheet 111

1024-Mbit LV Family

Figure 43. Decoder for Flash Code and Data SCSP Combinations

RD 58F 0012 LV Z B B x

Flash Product Family

L = Intel® StrataFlash Wireless Memory

LV = Intel® StrataFlash Wireless Memory System

0 = No die

Voltage Options

Z = 3.0 V I/O

Y = 1.8 V I/O

Ballout Identifier

B = x16D Performance

Device Details

x = Variable that can be 0- 9 orA - Z (excluding characters I and O)

0 = Initial version of a product asdefined by the first 14 characters.

Parameter Configuration

B = Bottom

T = Top

Product Die / Density Configuration

See the 38F/48F and 58F ProductDensity Decoder Tables.

Package Designator

RD = SCSP, leaded

PF = SCSP, Pb-free

NZ = Intel® UT-SCSP, BT, leaded

LZ = Intel® UT-SCSP, Tape, leaded

JZ = Intel® UT-SCSP, BT, Pb-free

RZ = Intel® UT-SCSP, Tape, Pb-free

Product Line Designator

38F = Stacked Flash + RAM

48F = Stacked Flash Only

58F = Stacked Flash / RAM

Table 61. 38F and 48F Product Density Decoder

Code Flash Die Density RAM Die Density

0 No Die No Die

1 32-Mbit 4-Mbit

2 64-Mbit 8-Mbit

3 128-Mbit 16-Mbit

4 256-Mbit 32-Mbit

5 512-Mbit 64-Mbit

6 1-Gbit 128-Mbit

7 2-Gbit 256-Mbit

8 4-Gbit 512-Mbit

9 8-Gbit 1-Gbit

A 16-Gbit 2-Gbit

112 Datasheet

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