CONTENTS 1 INTRODUCTION 1
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CONTENTS PREFACE xvi 1 INTRODUCTION 1 1.1 STRUCTURED COMPUTER ORGANIZATION 2 1.1.1 Languages, Levels, and Virtual Machines 2 1.1.2 Contemporary Multilevel Machines 4 1.1.3 Evolution of Multilevel Machines 8 1.2 MILESTONES IN COMPUTER ARCHITECTURE 13 1.2.1 The Zeroth Generation-Mechanical Computers (1642-1945) 13 1.2.2 The First Generation-Vacuum Tubes (1945-1955) 16 1.2.3 The Second Generation- Transistors (1955-1965) 19 1.2.4 The Third Generation-Integrated Circuits (1965-1980) 21 1.2.5 The Fourth Generation-Very Large Scale Integration (1980-?) 23 1.3 THE COMPUTER ZOO 24 1.3.1 Technological and Economic Forces 25 1.3.2 The Computer Spectrum 26 1.4 EXAMPLE COMPUTER FAMILIES 29 1.4.1 Introduction to the Pentium II 29 1.4.2 Introduction to the UltraSPARC II 31 1.4.3 Introduction to the picoJava II 34 1.5 OUTLINE OF THIS BOOK 36 vii
Transcript of CONTENTS 1 INTRODUCTION 1
CONTENTS
PREFACE xvi
1 INTRODUCTION 1
1.1 STRUCTURED COMPUTER ORGANIZATION 21.1.1 Languages, Levels, and Virtual Machines 21.1.2 Contemporary Multilevel Machines 41.1.3 Evolution of Multilevel Machines 8
1.2 MILESTONES IN COMPUTER ARCHITECTURE 131.2.1 The Zeroth Generation-Mechanical Computers (1642-1945) 131.2.2 The First Generation-Vacuum Tubes (1945-1955) 161.2.3 The Second Generation- Transistors (1955-1965) 191.2.4 The Third Generation-Integrated Circuits (1965-1980) 211.2.5 The Fourth Generation-Very Large Scale Integration (1980-?) 23
1.3 THE COMPUTER ZOO 241.3.1 Technological and Economic Forces 251.3.2 The Computer Spectrum 26
1.4 EXAMPLE COMPUTER FAMILIES 291.4.1 Introduction to the Pentium II 291.4.2 Introduction to the UltraSPARC II 311.4.3 Introduction to the picoJava II 34
1.5 OUTLINE OF THIS BOOK 36
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viii CONTENTS
2 COMPUTER SYSTEMS ORGANIZATION 39
2.1 PROCESSORS 392.l.1 CPU Organization 402.1.2 Instruction Execution 422.1.3 RISC versus CISC 462.l.4 Design Principies for Modem Computers 472.l.5 Instruction-Level Parallelism 492.l.6 Processor-Level Parallelism 53
2.2 PRIMARY MEMORY 562.2.1 Bits 562.2.2 Memory Addresses 572.2.3 Byte Ordering 582.2.4 Error-Correcting Codes 612.2.5 Cache Memory 652.2.6 Memory Packaging and Types 67
2.3 SECONDARY MEMORY 682.3.1 Memory Hierarchies 692.3.2 Magnetic Disks 702.3.3 Floppy Disks 732.3.4 IDE Disks 732.3.5 SCSI Disks 752.3.6 RAID 762.3.7 CD-ROMs 802.3.8 CD-Recordables 842.3.9 CD-Rewritables 862.3.10 DVD 86
2.4 INPUT/OUTPUT 892.4.1 Buses 892.4.2 Terminais 912.4.3 Mice 992.4.4 Printers 1012.4.5 Modems 1062.4.6 Character Codes 109
2.5 SUMMAR Y 113
CONTENTS ix
3 THE DIGITAL LOGIC LEVEL 117
3.1 GATES AND BOOLEAN ALGEBRA 1173.1.1 Gates 1183.1.2 Boo1ean Algebra 1203.1.3 Imp1ementation of Boolean Functions 1223.1.4 Circuit Equivalence 123
3.2 BASIC DIGITAL LOGIC CIRCUITS 1283.2.1 Integrated Circuits 1283.2.2 Combinational Circuits 1293.2.3 Arithmetic Circuits 1343.2.4 Clocks 139
3.3 MEMORY 1413.3.1 Latches 1413.3.2 Flip-Flops 1433.3.3 Registers 1453.3.4 Memory Organization 1463.3.5 Memory Chips 1503.3.6 RAMs and ROMs 152
3.4 CPU CHIPS AND BUSES 1543.4.1 CPU Chips 1543.4.2 Computer Buses 1563.4.3 Bus Width 1593.4.4 Bus Clocking 1603.4.5 Bus Arbitration 1653.4.6 Bus Operations 167
3.5 EXAMPLE CPU CHIPS 1703.5.1 The Pentium 11 1703.5.2 The UltraSPARC 11 1763.5.3 The picoJava 11 179
3.6 EXAMPLE BUSES 1813.6.1 The ISA Bus 1813.6.2 The PCI Bus 1833.6.3 The Universal Seria1 Bus 189
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3.7 INTERFACING 1933.7.1 IIO Chips 1933.7.2 Address Decoding 195
3.8 SUMMARY 198
4 THE MICROARCHITECTURE LEVEL 2034.1 AN EXAMPLE MICROARCHITECTURE 203
4.1.1 The Data Path 2044.1.2 Microinstructions 2114.1.3 Microinstruction ControI: The Mic-l 213
4.2 AN EXAMPLE ISA: IJVM 2184.2.1 Stacks 2184.2.2 The IJVM Memory Model 2204.2.3 The IJVM Instruction Set 2224.2.4 Compiling Java to IJVM 226
4.3 AN EXAMPLE IMPLEMENTATION 2274.3.1 Microinstructions and Notation 2274.3.2 Implementation of IJVM Using the Mic-l 232
4.4 DESIGN OF THE MICROARCHITECTURE LEVEL 2434.4.1 Speed versus Cost 2434.4.2 Reducing the Execution Path Length 2454.4.3 A Design with Prefetching: The Mic-2 2534.4.4 A Pipelined Design: The Mic-3 2534.4.5 A Seven-Stage Pipeline: The Mic-4 260
4.5 IMPROVING PERFORMANCE 2644.5.1 Cache Memory 2654.5.2 Branch Prediction 2704.5.3 Out-of-Order Execution and Register Renaming 2764.5.4 Speculative Execution 281
4.6 EXAMPLES OF THE MICROARCHITECTURE LEVEL 2834.6.1 The Microarchitecture of the Pentium 11CPU 2834.6.2 The Microarchitecture ofthe UltraSPARC-II CPU 2884.6.3 The Microarchitecture of t~e picoJava 11CPU 2914.6.4 A Comparison ofthe Pentium, UltraSPARC, and picoJava 296
4.7 SUMMARY 298
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5 THE INSTRUCTION SET ARCHITECTURE LEVEL 3035.1 OVERVIEW OF THE ISA LEVEL 305
5.1.1 Properties of the ISA LeveI 3055.1.2 Memory ModeIs 3075.1.3 Registers 3095.l.4 Instructions 3115.1.5 Overview of the The Pentium 11ISA Level 3115.1.6 Overview ofthe The UltraSPARC 11ISA Level 3135.l.7 Overview ofthe Java Virtual Machine 317
5.2 DATA TYPES 3185.2.1 Numeric Data Types 3195.2.2 Nonnumeric Data Types 3195.2.3 Data Types on the Pentium 11 3205.2.4 Data Types on the UltraSPARC 11 3215.2.5 Data Types on the Java Virtual Machine 321
5.3 INSTRUCTION FORMATS 3225.3.1 Design Criteria for Instruction Formats 3225.3.2 Expanding Opcodes 3255.3.3 The Pentium 11Instruction Formats 3275.3.4 The UltraSPARC 11Instruction Formats 3285.3.5 The JVM Instruction Formats 330
5.4 ADDRESSING 3325.4.1 Addressing Modes 3335.4.2 lmmediate Addressing 3345.4.3 Direct Addressing 3345.4.4 Register Addressing 3345.4.5 Register Indirect Addressing 3355.4.6 Indexed Addressing 3365.4.7 Based-Indexed Addressing 3385.4.8 Stack Addressing 3385.4.9 Addressing Modes for Branch Instructions 3415.4.10 Orthogonality of Opcodes and Addressing Modes 3425.4.11 The Pentium 11Addressing Modes 3445.4.12 The UltraSPARC 11Addressing Modes 3465.4.13 The JVM Addressing Modes 3465.4.14 Discussion of Addressing Modes 347
5.5 INSTRUCTION TYPES 3485.5.1 Data Movement Instructions 348
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5.5.2 Dyadic Operations 3495.5.3 Monadic Operations 3505.5.4 Comparisons and ConditionaI Branches 3525.5.5 Procedure Call Instructions 3535.5.6 Loop ControI 3545.5.7 Input/Output 3565.5.8 The Pentium II Instructions 3595.5.9 The UltraSPARC 11Instructions 3625.5.10 The picoJava 11Instructions 3645.5.11 Comparison ofInstruction Sets 369
5.6 FLOW OF CONTROL 3705.6.1 SequentiaI Flow of ControI and Branches 3715.6.2 Procedures 3725.6.3 Corou tines 3765.6.4 Traps 3795.6.5 Interrupts 379
5.7 A DETAILED EXAMPLE: THE TOWERS OF HANOI 3835.7.1 The Towers of Hanoi in Pentium 11AssembIy Language 3845.7.2 The Towers ofHanoi in UltraSPARC 11AssembIy Language 3845.7.3 The Towers of Hanoi in JVM AssembIy Language 386
5.8 THE INTEL IA-64 3885.8.1 The Problem with the Pentium 11 3905.8.2 The IA-64 ModeI: ExpIicitly ParalleI Instruction Computing 3915.8.3 Predication 3935.8.4 SpecuIative Loads 3955.8.5 ReaIity Check 396
5.9 SUMMARY 397
6 THE OPERATING SYSTEM MACHINE LEVEL 4036.1 VIRTUAL MEMORY 404
6.1.1 Paging 4056.1.2 Implementation of Paging 4076.1.3 Demand Paging and the Working Set Model 4096.1.4 Page RepIacement PoIicy 4126.1.5 Page Size and Fragmentation 4146.1.6 Segmentation 4156.1. 7 ImpIementation of Segmentation 418
CONTENTS xiii
6.1.8 Virtual Memory on the Pentium II 4216.1.9 Virtual Memory on the UltraSPARC 4266.1.10 Virtual Memory and Caching 428
6.2 VIRTUAL 1/0 INSTRUCTIONS 4296.2.1 Files 4306.2.2 Implementation of Virtual 1/0 Instructions 4316.2.3 Directory Management Instructions 435
6.3 VIRTUAL INSTRUCTIONS FOR PARALLEL PROCESSING 4366.3.1 Process Creation 4376.3.2 Race Conditions 4386.3.3 Process Synchronization Using Semaphores 442
6.4 EXAMPLE OPERA TING SYSTEMS 4466.4.1 Introduction 4466.4.2 Examples of Virtual Memory 4556.4.3 Examples of Virtual 1/0 4596.4.4 Examples of Process Management 470
6.5 SUMMARY 476
7 THE ASSEMBLV LANGUAGE LEVEL 4837.1 INTRODUCTION TO ASSEMBL Y LANGUAGE 484
7.1.1 What Is an Assembly Language? 4847.1.2 Why Use Assembly Language? 4857.1.3 Format of an Assembly Language Statement 4887.1.4 Pseudoinstructions 491
7.2 MACROS 4947.2.1 Macro Definition, Call, and Expansion 4947.2.2 Macros with Parameters 4967.2.3 Advanced Features 4977.2.4 Implementation of a Macro Facility in an Assembler 498
7.3 THE ASSEMBL Y PROCESS 4987.3.1 Two-Pass Assemblers 4987.3.2 Pass One 4997.3.3 Pass Two 5027.3.4 The Symbol Table 505
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7.4 LINKING AND LOADING 5067.4.1 Tasks Performed by the Linker 5087.4.2 Structure of an Object Module 5117.4.3 Binding Time and Dynamic Relocation 5127.4.4 Dynamic Linking 515
7.5 SUMMARY 519
8 PARALLEL COMPUTER ARCHITECTURES 5238.1 DESIGN ISSUES FOR PARALLEL COMPUTERS 524
8.1.1 Communication Models 5268.1.2 Interconnection Networks 5308.1.3 Performance 5398.1.4 Software 5458.1.5 Taxonomy of Parallel Computers 551
8.2 SIMD COMPUTERS 5548.2.1 Array Processors 5548.2.2 Vector Processors 555
8.3 SHARED-MEMORY MULTIPROCESSORS 5598.3.1 Memory Semantics 5598.3.2 UMA Bus-Based SMP Architectures 5648.3.3 UMA Multiprocessors Using Crossbar Switches 5698.3.4 UMA Multiprocessors Using Multistage Switching Networks 5718.3.5 NUMA Multiprocessors 5738.3.6 Cache Coherent NUMA Multiprocessors 5758.3.7 COMA Multiprocessors 585
8.4 MESSAGE-PASSING MULTICOMPUTERS 5868.4.1 MPPs-Massively Parallel Processors 5878.4.2 COWs-Clusters ofWorkstations 5928.4.3 Scheduling 5938.4.4 Communication Software for Multicomputers 5988.4.5 Application-Level Shared Memory 601
8.5 SUMMARY 609
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9 REAOING LlST ANO BIBLlOGRAPHV 6139.1 SUGGESTIONS FOR FURTHER READING 613
9.1.1 Introduction and General Works 6139.1.2 Computer Systems Organization 6149.1.3 The Digital Logic Level 6159.1.4 The Microarchitecture Level 6169.1.5 The Instruction Set Architecture Level 6179.1.6 The Operating System Machine Level 6179.1.7 The Assernbly Language Level 6189.1.8 Parallel Computer Architectures 6189.1.9 Binary and Floating-Point Numbers 620
9.2 ALPHABETICAL BIBLIOGRAPHY 620
A BINARV NUMBERS 631A.I FINITE-PRECISION NUMBERS 631A.2 RADIX NUMBER SYSTEMS 633A.3 CONVERSION FROM ONE RADIX TO ANOTHER 635A.4 NEGATIVE BINARY NUMBERS 637A.5 BINARY ARITHMETIC 640
B FLOATING-POINT NUMBERS 643B.l PRINCIPLES OF FLOA TING POINT 644B.2 IEEE FLOATING-POINT STANDARD 754 646
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