Contattare il substrato - franchi/Dida01/RisultatoRC.pdf · Contattare il substrato Adapted from J....
Transcript of Contattare il substrato - franchi/Dida01/RisultatoRC.pdf · Contattare il substrato Adapted from J....
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Metal 1
n +
n well
p -Si
R? metal 1 = 57 mO/ ?
R? n + = 1.5 O/ ?
R contatto = 1.5 O
ContattareContattare ilil substratosubstrato
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Metal 1
p +
p -Si
R? metal 1 = 57 mO/ ?
R? p + = 1.5 O/ ?
R contatto = 1.5 O
ContattareContattare ilil substratosubstrato
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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The Gate CapacitanceThe Gate CapacitancePolysilicon gate
tox
n+ n+
Cross section
L
Gate oxide
L
Top view
Gate-bulkoverlap
Source
n+
Drain
n+W
Cgate,tot≈ Cox WL
= Cox L2 (W/L)
= Cg (W/L)
Cg = Cox L2 = (eox/tox) L2
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Junction CapacitanceJunction Capacitance
Bottom
Side wall
Side wallChannel
Source
W
xj
Z
CSB = Cbottom + Csw= Cj Area + Cjsw Perimeter= Cj W Z + Cjsw (2Z +W)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
11CapacitàCapacità di di uscitauscita dell’inverterdell’invertersenzasenza i i transistoritransistori di di isolamentoisolamento
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
12CapacitàCapacità di di uscitauscita dell’inverterdell’inverter con con i i transistoritransistori di di isolamentoisolamento
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Inverter with LoadInverter with Load
CL
Tp
CL Tp,int
CL = somma Cin,eq + Clinea
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Delay DefinitionsDelay Definitions
Vout
tf
tpHL tpLH
tr
t
V in
t
90%
10%
50%
50%
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
15CMOS Inverter Propagation DelayCMOS Inverter Propagation DelaySimplified approach 1Simplified approach 1
• modello di ordine 0 del MOSFET• capacità concentrata in uscita• fronti istantanei
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
16CMOS Inverter Propagation DelayCMOS Inverter Propagation DelaySimplified approach 2Simplified approach 2
Imax
VDD
Vout
Vin = VDD
CLImax
tpHL = CL VDD /2
I = vsat W Cox(Vdd –Vtn) max
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
17Propagation delay model for logic Propagation delay model for logic synthesis and simulation toolssynthesis and simulation tools
• TP,int: intrinsic delay (i.e. delay with no output loading)• RC : fraction of the delay caused by the output load• STr: fraction of the delay due to input slope
C = ΣCin,eq + Clinea
7 parameters: TP,int,HL TP,int ,LH Rup RDown SS,UP SS,Down Ceq,in
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
19Delay models using lookup tablesDelay models using lookup tables
........
........
........
......value
TP = TP,int + TD(Ts,in, Cext)
TD(Ts,in, Cext)Cext
Ts,in
TS,OUT(Ts,in, Cext)
........
........
........
......value
CextTs,in
Inoltre sono da calcolare: TP,int Ceq,in
Cext = ΣCin,eq + Clinea
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
20ExampleExample
Cext
val(ps)
Ts,in
4 12 28 80
5.6
101
261
533
160 (fF)
1069
(Ts in ns)
(Cext in pF)
1500
(ps)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Example: INVERTER 0.13um
pF
ns
pFns
Ts,
in
Ts,
in
Cext
CextTp,HL
Tfall
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Where Does Power Go in CMOS?Where Does Power Go in CMOS?
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
24Inverter
pW
pW (valore medio)
pW
pF
ns
pFns
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Energia assorbita a seguitodella transizione degli ingressiespressa in pJ
in questo valore sono solo consideratii contributi associati alla corrente di cortocircuito e agli effetti reattivi intrinseci
Ts,
in
Cext
Cext
Ts,
in
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
26RisultatiRisultati caratterizzazionecaratterizzazione dell’Inverterdell’Inverter((duratadurata transizionetransizione in in ingressoingresso 100 100 psps))
Tp,int,HL = 35 psTp,int,LH = 54 ps Tpint,NOT = 45 ps
R,HL = 1 ps/fFR,LH = 1.5 ps/fF RNOT = 1.25 ps/fF
23 ps
24 ps
24 ps21 ps
15 ps
15 ps13 ps
13 ps
Tpint,NOTRNOT Cin,NOT
= 451.25 * 13
≈2.7γ =
Cin,not = 13 fFStima Cint ≈ 36fF assumendo Tpint= Rnot Cint
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
27DipendenzaDipendenza del tempo di del tempo di propagazionepropagazione dalladalla capacitàcapacità esternaesterna
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Tempi di Tempi di salitasalita e e discesadiscesa
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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EnergiaEnergia associataassociata allaalla transizionetransizioneLL--H_L H_L dell’uscitadell’uscita
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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ProgettoProgetto Buffer Buffer nelnel SOGSOGTp,i = Tp,int,medio,i + Ri Cin,i +1 = Tp,int,not + f Rnot Cin,not
f =Cin,i +1Cin,i
CL
Cin,1F =
tpoTp,int,nottdo
tpo/γRnot Cin,nottd1
γ = Tp,int,not/Rnot Cin,notγ = tdo/td1
ffr
FFR
J. RabaeyE.FranchiProf. G. Baccarani
fN = F
( )ff γ+= 1exp
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
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Optimum Effective Optimum Effective FanoutFanout ffOptimum f for given process defined by γ
( )ff γ+= 1exp
fopt = 3.6for γ=1
fopt = 4.7for γ=2.7
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
32Sensibilità al fattore di dimensionamentoSensibilità al fattore di dimensionamento
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2006-2007
33TransizioneTransizione degli degli ingressiingressi cheche renderendemassimomassimo ilil tempo di tempo di propagazionepropagazione
• è sempre quella a cui corrisponde la carica/scaricadei nodi interni oltre che del nodo di uscita• è quella in cui l’ingresso che varia è applicata al transistore con il source a gnd (o Vdd)