Constructing Circuits Using Wired Descriptions€¦ · A half adder layout using ST 90nm...

Constructing Circuits Using

Wired Descriptions

Kasyab P. Subramaniyan

Department of Computer Science and Engineering

Chalmers University of [email protected]

mailto:[email protected]

Outline• Motivation and Background

• Wired

• Backend Flow

• Case Studies

• Future Work

Motivation • Transistor geometries growing smaller

- density increasing Moore’s Law

• Designs becoming larger and more complex

• Variability adversely affects circuits

- affects yield

• Methodologies to support design of large

designs

Motivation

• Custom layout

– high NRE

– requires special competence

– fully utilizes performance of technology

A half adder layout

using ST 90nm

technology

Motivation

• Automatic place & route

– low NRE

– heuristics don’t guarantee efficient use of technology

A Fully placed &

routed 32-bit HPM

Mulitplier using ST

90-nm library cells

Background

• Tegola Structure Optimizer:http://www.tuscanyda.com

• Intel Integrated Design & Verification (IDV):

C. Seger, “Integrating Design and Verification - from Simple Idea to Practical System,” in Fourth ACM and IEEE Intl Conf. on Formal Methods and Models for Co-Design (MEMOCODE), 2006.

• Work on data path circuits of fixed word length.

Wired

• Developed by Emil Axelsson

• More information :http://www.cs.chalmers.se/~emax/wired/index.html

• Implemented using Haskell

• Applicable to layouts that exhibit regularity

Wired

myFunc (a,b,c) = doc’ <- ivsvtx2 cbc <- an2svtx2 (b,c’)or2svtx2 (a,bc)

Description of (A + B.C’) in Wired

• Covers three aspects of a circuit description - 1:

– Logic function as technology mapped netlist

Wired

bitMultPlaced (a,bs) = rightwards $mapM bitMult1 bswherebitMult1 b = downwards $(nd2svtx2 >=> ivsvtx2) (a,b)

Placement in Wired


– Cell placement

Wired

*Main> analyzeTiming (input >>= myFunc)Time 9.781e-11

Basic Wire Awareness in Wired


– Some aspects of the wiring (experimental)

Wired

*Main> simulate myFunc (0,1,1)0*Main> simulate myFunc (0,1,0)1

Logic Simulation in Wired

• Logical simulation is also possible

• Interactive development

• As output, DEF files can be produced

Backend Flow

Wired

SoCEncounter

DE

F fi

le

Inpu

t net

list

GDSII

Foundry Libs

RTL Compiler

Black Box Information

RTL Circuit Description• RTL Compiler :

• Technology mapped to 90-nm GP-SVT ST Micro.

• Parts integrated via Wired made black boxes.

• Wired netlist integrated in SoC Encounter

• Backend flow completed to produce GDS II

Backend FlowLoad Netlist

Floorplan & Partitions

Block Development

Integration

Place

Route

Verify

GDSII

• Import design with LEF files for the black boxes

• Set up initial floorplan

• Create physical hierarchies

• Specify & commit the partition(s) (black boxes)

• Run a (non-timing driven) placement

• Save the partitions & unload design using `freeDesign`

Backend FlowLoad Netlist


Block Development

Integration

Place

Route

Verify

GDSII

• Load technology libraries

• Use `loadDefFile` to load the Wired netlist

• Perform any additional placement tasks

• Save (replace) the partition netlist

Load Netlist


Block Development

Integration

Place

Route

Verify

GDSII

Backend Flow• Run `updateBlock`

• Adjust the floorplan

• Run timing driven placement

• Set up the clock tree and synthesize it

• Run routing for the entire design

• Ensure all DRC's are satisfied

• Complete pre-Sign-Off checks

Case Studies• Previous work using only Wired descriptions.

• Focused on purely combinational circuits

- mainly prefix adders and multipliersM. Sheeran, “Generating Fast Multipliers Using Clever Circuits,” in 5th Intl Conf. on Formal Methods in Computer-Aided Design (FMCAD), ser. Lecture Notes in Computer Science, vol.

3312. Springer, 2004, pp.6–20.

• These case studies focus on implementations

• Multipliers:K. P. Subramaniyan, E. Axelsson, M. Sheeran, and P. Larsson-Edefors, “Layout Exploration

of Geometrically Accurate Arithmetic Circuits,” in IEEE International Conference on Electronics, Circuits, and Systems, Dec. 2009.

• Shifters:A. Bardizbanyan, K. P. Subramaniyan and P. Larsson-Edefors,” Generation

and Exploration of Layouts for Area-Efficient Barrel Shifters”, IEEE Computer Society Annual Symposium on VLSI, Jul. 2010 (Accepted for publication).

Case Studies - Multipliers

• Commonly used in circuits

• Two types of Parallel Multipliers: Array Multipliers

Logarithmic Depth Multipliers

• High Performance Multiplier (HPM):

• Based on the log depth Dadda Multiplier

• Exhibits regularity as well

• Original layout triangular Transformation to rectangular layout


Triangular 32-Bit HPM Multiplier


Triangular 32-Bit HPM Multiplier with Routing

Channels

Case Studies - MultipliersResults :

• Frequency for all designs limited to 250 MHz at 1.08V

• Switching power determined by statistical switching of primary inputs

• Tool built into Encounter used for power analysis.

PPRT Geometry Switching Power (mW) Slack (ns)

HPM Triangular 1.65 0.543

HPM Triangular

Channeled

1.42 0.320

Comparison/Control Cases

Dadda 1.32 0.992

Wallace 1.43 0.614


0

20000

40000

60000

80000

100000

120000

140000

160000

180000

200000

RTL Flow Triangular Triangular 5ML

Triangular RC

Total Wire Length

RTL Flow

Triangular

Triangular 5ML

Triangular RC

Congestion(1/2):

0

10000

20000

30000

40000

50000

60000

M1 M2 M3 M4 M5 M6 M7

RTL Flow

Triangular

Triangular 5ML

Triangular RC

Congestion(2/2):Case Studies - Multipliers

Case Studies - Shifters

• Shifters are vital components of the processors.

• Most known example:

• shift right by n bits divide by 2n

• shift left by n bits multiply by 2n

• Occupy large area & dissipate a lot of power.

• Regular architectures good candidates for the wired approach.

• 8 bit, arithmetic and logic shiftlog2(8) = 3 levels 8x3 = 24 (2-to-1) mux

Case Studies - Shifters>renderWiredWithNets “circ” circ1


• Fanout is the most important problem for these kind of shifters.

• Every select line drives input-size-times multiplexers.

• Standard Cells have max fanout and max cap limits.

• Check the correctness of the design in Soc Encounter:‘reportfanoutviolation’, ‘reportcapviolation’

• CORE90GPSVT_1.20V library is used for the evaluation and the

comparison with the CAD tool.

Case Studies - ShiftersSoC Dimensions (um) Area(um2) Slack time (ps) Power (mW)

80.5 * 35.28 2827.16 FAIL FAIL

90 * 39 3510 43 5.588

85 * 43.12 3665,2 12 5.47

87*43.12 3751.44 54 5.587

90*43.12 3880,8 50 5.734

90*43.12 3880,8 52 5.545

Wired Dimensions (um) Area(um2) Slack time (ps) Power (mW)

80.5 * 35.28 2827.16 28 4.08

82.7 * 35.28 2917,6 34 4.098

87.5 * 35.28 3087 36 4.47

92.3 * 35.28 3256,34 44 4.793

92.3 * 43.12 3256,34 46 4.769

101.4 * 35.28 3577,39 52 4.94

96.92 * 35.28 3419,33 54 4.876

Future Work

• Dense regular layouts lead to routing congestion

• Routing channels added to layouts of regular circuits mitigates this somewhat.

• What else can be done?

• Custom characterized cells“Impact of Standard Cell Pin Placement on Routing Regularity of HPM

Architectures”, Affaq Qamar, Kasyab P. Subramaniyan, and Per Larsson-Edefors, Swedish System on Chip Conference, May 2010.

Future Work

A CO

CI

B Z

A CO

CI

B Z

B Z

CI

A CO

B Z

CI

A CO

A CO

CI

B Z

A CO

CI

B Z

B Z

CI

A CO

B Z

CI

A CO

Future Work

HAA

B

CO

S

HACO

S

A

B

HAA

B

CO

SHAA

B

CO

S

FACO

Z

A

B

FA

A

B

CO

ZCI

CI

FAA

B

CO

ZFA

A

B

CO

ZCI CI

Future Work

Future Work

Slack

(ns)

Total wire

length (µm)

Avg. wire

length (µm)

No. of

Vias

Flipped 0.185 208,938 52.0 24,352

Normal 0.259 230,058 57.3 39,784

ST. Lib. 0.804 165,783 41.3 41,110

NOTE:

HA from custom library occupies the same area as the FA from ST library…

Future Work

• Routing length decreases significantly

• Number of Vias also decreases

• Combine these observations to assess variability

• Can this assessment be built into Wired?

Questions?

Constructing Circuits Using Wired Descriptions€¦ · A half adder layout using ST 90nm...

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