Constellations 2010 Silicon Valley - Complete Slide Set

© IPextreme, Inc.Confidential Information.

Constellations Conference Silicon Valley 2010Constellations Conference Silicon Valley 2010

A collaborative group of IP companies working together to

serve common customers

MCU &DSP

Periph-erals Audio Video

Inter-faces

Network-ing

On-Chip Interconnect Memory

Encrypt-ion

Compilers

withData Flow Services

Legend Soft IP Hard IP Software Other

ESD

http://www.ip-extreme.com/partners/constellations_chipsnmedia.html

http://www.ip-extreme.com/partners/constellations_novelics.html

http://www.ip-extreme.com/partners/constellations_posedge.html

http://www.ip-extreme.com/partners/constellations_sonics.html

© IPextreme, Inc. Confidential Information. Slide 3

Agenda

8:30am Breakfast

9:15am Welcome & Introductions Warren Savage

9:25am Keynote Presentation Jim Hogan

9:40am Increasing ESD Challenges Stephen Fairbanks

10:00am Integrating high performance, ultra-low power Clockless IP Serge Maginot

10:20am Turn your Engineering Cost Center to a Profit Center Rick Tomihiro

10:40am Panel: IP Business Models

11:40am Lunch


Agenda

12:15pm Leveraging Your On-chip Networks and Maximizing Multi-layer Bus Designs Jack Browne

12:35pm The Need for a New Breed of Embedded NVM Jim Lipman

12:55pm Can You Trust Your IP Vendor? How Not to Lose Sleep Over it Hal Barbour

1:15pm Bringing HD video to multimedia applications Philip Han

1:35pm Afternoon Break & Refreshments

1:55pm Ultra Low Power CoolFlux DSP Cores Sweetening Your Green Chip Dreams Sven De Bie

2:15pm Rest in the comfort and security of knowing you have Selected the Optimum Memory IPs Farzad Zarrinfar

2:35pm The role of Networking IP in Wired/Wireless Applications Surya Hotha


Agenda

2:55pm Panel: Technical Considerations

3:55pm Luck Draw – Apple iPad

4:10pm Closing Statement Warren Savage

4:20pm Networking

5:00pm End

IPextreme Constellations Conference - Silicon Valley 2010Jim Hogan - Wednesday, March 31, 2010

Major Market Directions• Exploding HW complexity

– $$$ per chip only allow major volume components to be successful

• Exploding SW complexity– Growth 10 fold in 10 years

• Costs driving out smaller semi’s– Big semi’s aggregating, collaborating, shrinking, disappearing

• Major players (Japan Inc) looking for future direction– Foundry agnostic

– Content, system expertise still strongholds

• New players (China Inc) driving into every aspect of Semi’s– Video, local consumption, local standards driving models

– Closing on innovation gap quickly

HW Development

• Industry investment is stagnant

• Costs are escalating beyond the reach of many fabless semi’s

• Substantial investment dip in recent past has rippled to EDA/IP

– Outlook for the next 5 years is slightly better than single digit growth

-20.0

-15.0

-10.0

-5.0

0.0

5.0

10.0

15.0

20.0

25.0

% Y

ea

rly

Gro

wth

HW Growth Rate (%)

HW Growth Rate (%) 0.4 -8.3 0.4 20.5 7.9 10.4 7.3 -5.3 -17.8 5.5 12.0 14.1 14.1 9.5 6.4

2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015

Source: GLOBAL SYSTEM IC (ASSP/ASIC) SERVICE MANAGEMENT REPORT - 8/09Source: GLOBAL SYSTEM IC (ASSP/ASIC) SERVICE MANAGEMENT REPORT - 8/09

Industry Trends –SW IP Outpaces HW IP

2007 2008 2009 2010 2011 2012 2013 2014 2015

Hardware product development ($M) 18,830 17,837 14,665 15,478 17,336 19,786 22,574 24,713 26,283

HW IP ($M) 3,088 3,104 2,713 3,049 3,641 4,432 5,395 6,302 7,175

• Percent HW prod dev (%) 16.4 17.4 18.5 19.7 21 22.4 23.9 25.5 27.3

• Growth rate (%) 13.6 0.5 -12.6 12.4 19.4 21.7 21.7 16.8 13.9

HW Growth Rate (%) 7.3 -5.3 -17.8 5.5 12.0 14.1 14.1 9.5 6.4

HW Growth Baseline YR ‘2000 42.6 35.1 11.0 17.2 31.3 49.8 70.9 87.1 99.0

SW product development ($M) 6,384 7,003 6,291 7,365 9,450 11,867 14,825 18,587 22,921

SW IP ($M) 441 616 692 987 1,503 2,207 3,202 4,628 6,555

• Percent SW prod dev (%) 6.9 8.8 11 13.4 15.9 18.6 21.6 24.9 28.6

• SW Growth (%) 61.5 39.9 12.3 42.6 52.3 46.9 45.1 44.5 41.6

SW Growth Rate (%) 19.39 9.70 -10.17 17.07 28.31 25.58 24.93 25.38 23.32

SW Growth Baseline YR ‘2000 182.7 210.1 178.6 226.2 318.5 425.6 556.6 723.2 915.1

TOTAL product development ($M) 25,214 24,840 20,956 22,843 26,787 31,653 37,399 43,300 49,204


SW Growth as part of the Semiconductor Industry Outpaces HW significantly

HW Growth (%)SW Growth (%)

-100.0

0.0

100.0

200.0

300.0

400.0

500.0

600.0

700.0

800.0

900.0

1000.0

2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015

2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015

HW Growth (%) 0.4 -7.9 -7.5 11.4 20.3 32.8 42.6 35.1 11.0 17.2 31.3 49.8 70.9 87.1 99.0

SW Growth (%) 6.1 4.2 17.9 60.9 95.0 136.8 182.7 210.1 178.6 226.2 318.5 425.6 556.6 723.2 915.1

HW Growth (%) SW Growth (%)


• Fabless and IDMs will:

– Utilize SoCs to integrate system application knowledge and capture user experience

• Capture more value than standard discrete component

– Deploy heterogeneous multiple processors running distinct hardware operating software

– Focus increasingly limited resources on architecture and

software, with ecosystem partnerships in non- differentiated IP, physical

implementation, foundry and test• Core competencies in specialized

differentiating IP (hardware and software) and in SoC integration strength

• Shed the need for ongoing investment in ubiquitous design and commoditized assets such as standardized intellectual

property (USB, PCI, DDR…)

Multi-Processor SoC

FPGAFPGAPeriph

eMEMMEM

DSP

I/O I/OI/O

CPUCustom

DSP

SoC New WorldSoC New World

• Requirements– Heterogeneous integration of any IP core on any SoC at any

time… to optimize for the system software application

– Flexibility to match system application needs without over-design

– Predictable logical and physical implementation…and silicon proven

– Rapid adaptation to changing markets

– Automated derivative design and verification

• Elements– Complete SoC communication architectures

• System level services – quality of service ( QoS), security, power, error management

• Flexible sockets

• Scalable fabrics

– Cycle accurate architectural performance models (i.e. Carbon)

– Coherent SoC capture, refinement, and verification environment

SoC Platform StandardSoC Platform Standard

Android Based System

PVRApp

HDPlayer App

Digital Rights MgmtConditional Access Audio

µCodeVideoµCode

DemurµCode

DirectFBVideo/Graphics

Libraries

Linux Kernel 2.6.29

WebkitAndroid Libraries3rd Party

Middleware

Android Application Framework

TV AppStreaming

AppAndroid

AppAndroid

AppAndroid

App

Adobe®FlashFor

DigitalHome

BD-J

Dalvik VM

Core Libraries

SW Challenges• Multi-core complexity and core count explosion drives

up SW complexity– Multi-mode operation mixes and matches SW tasks

• Disaggregation of former centrally managed resource fractures system integration– SoC resource manager for heterogeneous systems

• Exponential cost growth– Non-differentiated SW must be provided at no cost by

Semi’s

– Development elapsed time exceeds life cycle of device or electronic product such as a phone

Redefine EDA/IP• For the EDA/IP Industry to grow it must address

SW growth opportunity• Evolutionary: ESL as a language/tool to enable

earlier SW development– Only addresses development elapsed time

– Synopsys has acted to capture inorganic growth opportunities

• Revolutionary: SW tasks are abstracted from the HW – Through the use of machine-to-machine

communications

– Through the introduction of HW assist: SoC resource manager

– Removes SW workload

System Design Considerations• Direct mapping to various silicon vendors

– Architectural floor planner– Persistency - design intent capture and re-entrant design flow

• Strong suite of IP libraries– Re-usable– Pervasive– Non-competitive

• Resource management for: – Error handling, protection mechanisms, system addressing,

QoS, power management

• SW virtualization layer between HW specific resources and operating systems/applications

• Architectural Intent must be captured

– Persistence through the design/implementation hardware flow must be ensured

• Architectural Intent must solidify the tool chain

– Verification: re-use from Architectural specification to 100% validation

• Architectural Intent must be transparent

– Machine to machine interactions for the millions of lines required to describe the system

“The integration platform must subsume the traditional design flow, rather than displacing it.”

(Alberto Sangiovanni-Vincentelli)

PlatformDesign-Space

Export

PlatformMapping

Architectural Space

Application SpaceApplication Instance

Platform Instance

Semantic PlatformPlatform

PlatformDesign-Space

Export

PlatformMapping

Architectural Space

Application SpaceApplication Instance

Platform Instance

Semantic PlatformPlatform

Beyond EDA Classic Global Considerations

Geographical – Then and Now• Massive Market shift in the last decade

– Europe system knowledge evaporating with massive consolidation, restructuring and refocus as consumption moves to non European markets

• ST, ST-Ericsson, Nokia, NXP, Infineon all have undergone massive changes

– USA manufacturing has re-located or partnered with Taiwan• IBM-Chartered-Samsung-ST

• TSMC-Intel

• AMD-Chartered-Global Foundries-ST

– Japan, Inc struggling to understand the roadmap for the industry

– Taiwan and China designing increasingly complex SoCs and complete systems

Synopsys Cadence Mentor

USA 48.5% 46% 46%

EU 14.5% 22% 33%

Japan 20% 18% 15%

Asia 17% 14% 13%

• Huge mistake to ignore US and Japan– Strategy must encompass and protect

existing revenue streams

– Rifle shot approach to Europe

– Strategic approach to Japan

– Follow the complex curve in China, Korea and India

Japan, Inc

• Struggling to understand where their electronics industry is going– Foundry technology too expensive

• Abandoning @ 40nm, going with TSMC?

– Manufacturing consumption over seas

• Japan’s value – still the leader in consumer electronics– System expertise – consumer and automotive– Content ownership– System level market presence– Cohesive action while maintaining independence

• INCJ approved funding to $8B (http://www.incj.co.jp/)

China Inc• Moving up the food chain and

attacking electronic development– World class innovators in 5 years

• Leveraging local consumption, local standards and local manufacturing– Dominating emerging markets (Latin

America, Africa, India)

• Challenging all cost assumptions in the industry vendor chain

• Major developing area – opportunity to shape thought process from ground level

Cannot treat as simply a “market share” opportunityCannot treat as simply a

“market share” opportunity

India Inc.

• India vying for the development of libraries and basic IP

– Virtually no fabless or SoC companies in India

– Focus seems to be standards based software, digital and mixed signal IP

• Major players such as Wipro and HCL have sprung up design service partners for IDMs and fabless semiconductor companies

– Emerging private label brands with complete systems engineering

• Most major US, European and Japanese semiconductor companies have design centers in India

– Purchase decisions go through HQ

– Although as is the case at ST all Mixed Signal design is now India

• 50% of the cost of developing libraries and basic IP can be trimmed by an Indian technology follower strategy (lagging the leader by 12 months)

Increasing ESD challenges for IP Vendors and Suppliers

Stephen Fairbanks

Managing Director

[email protected]

Copyright © CERTUS Semic., LLC, 2010 proprietary & confidential

Certus Semiconductor

About Certus Semiconductor, LLC.

Certus Semiconductor is a cooperative corporation, joining efforts of several of the worlds leading ESD and IO designers, to bring to the semiconductor IP market a novel support and service model in the area of ESD and IO design. Along with the standard silicon proven ESD and IO libraries in several technologies and foundries, Certus also offers the world’s first “IO template” libraries, as well as low cost, quick turn around and simulation proven custom ESD and IO libraries; using unique device models based on silicon proven designs that offer high confidence of first silicon passing ESD standards. Certus also offers the worlds best ESD strategies/devices for RF and III-V semiconductor products.

www.certus-semi.com

24


ESD challenges in the IP Business

A few realities about ESD

We don’t usually sell ESD….it is never the product. Because of this no one wants to spend money or time on it. This also makes ESD protection an afterthought in many IP projects.

Without ESD … manufacturing can be a very difficult process. Its hard to qualify the ESD impact

ESD is usually one of the first suspects in a yield or field failure situation.

If something fails in your customers assembly process, your ESD performance can either be a liability or a saving grace when it comes to customer relations and reputation.

ESD can be a marketing difference between two competing products



Increasing Challenges about ESD

Advanced technologies nodes are producing transistors and devices that are much more susceptible to ESD failure than previous designs.

26

NMOS Failure Trends: Jedec JEP157



Increasing Challenges about ESD

Product Complexity is straining traditional ESD design architectures

Products routinely have >10 separate Power and Ground Domains Blocks of different size and sensitivity are commonly integrated

PLL’s, RF, Analog, Audio, Sensors, Memories, SerDes

New power sequencing and power down modes can challenge traditional ESD architectures.

27

These complexities lead to the situation where the ESD performance of an IC is increasingly dependent on chip level ESD architecture, as opposed to individual IO and power domains.

This means that an IP block may pass ESD for one customer’s product, but fail in another.



28

Traditional IP block integration had all the ESD protection residing in the Padring.

Example, here we have a network processor example, where a High Speed SerDes IP block was integrated.

Traditional ESD was handled by clamping the ground together in the padring. (shown by blue arrows)

However, multitudes of internal signals cross block boundaries (shown by red arrows)

Core failures on internal signals are increasing.



Traditional approach for IP validation of ESD is no longer sufficient.

Focus beyond IO and padring

Internal Failures are increasing.

A result of greater complexity and integration.

29

Here is an internal buffer for a signal between an RF Transmitter and a digital core that failed during CDM stressing.



There are a multitude of techniques for protecting internal signals, one such examples.

Individual signal protection: Pros:

– Very Effective– Easy to Implement

Cons: – Big area increase– Timing delay/skew

30

Input Buffer

Output Buffer

Vdd1

Vss1

Vdd2

Vss2ESD Clamp in

Padring

Individual Protection



There are a multitude of techniques for protecting internal signals, one such examples.

Internal Clamp Placement Blue Squares represent

traditional ESD clamps found in padring.

Red Squares demonstrate that with intelligently designed and placed power and ground clamps, internal signals can be protected.

31

Pros: No need for individual signal protection

Cons:

Big area increase

Clamp design is not straightforward

Power Busses in core need redesign.



Concluding remarks:

Bad Situations that strain business relationships: IP Vendor: A supposedly passing IP block fails in 1 customer. IP Customer: Product failures are in an IP block Failure Analysis: Is it the IP or the Integration?

Debugging ESD problems is much harder than just avoiding them in the first place. Awareness of new and emerging failure mechanisms can help avoid them. IP Vendors: ESD design beyond the IO’s IP Providers: Expand ESD architecture beyond the padring.

32

As products increase in complexity and technologies advance, expect to see ESD challenges continue to increase. There will be an increased need for both IP Vendors and IP Customers to be aware of these increasing challenges and have methods in place to address them.

March 31st, 2010

Constellations Conference – Santa ClaraConstellations Conference – Santa Clara

www.tiempo-ic.com [email protected]

Copyright TIEMPO 2010 – March 31st, 2010 – Constellations Conference, Santa Clara

TIEMPO mission

• Offer powerful asynchronous core IPs supported by an innovative design and synthesis flow for low power embedded electronics and secured devices

• Allow our customers to design chips with outstanding performances in ultra-low power consumption, speed and security against hardware attacks

Ultra-low power embedded electronics

Mobile consumer electronics

Automotive Aerospace Contactless and otherelectronic transactions


AgendaAgenda

• IntroductionIntroduction• Tiempo technology benefitsTiempo technology benefits• Tiempo IP portfolioTiempo IP portfolio• Tiempo design flowTiempo design flow• ConclusionConclusion


Tiempo asynchronous design technology offers breakthrough performances on all these aspects

Case study: contactless Case study: contactless applicationsapplications

Ultra-low power with high

processing speed

Ultra-low power with high

processing speed

High level of security against hardware attacks

High level of security against hardware attacks

Works at variable voltage & remote

power source

Works at variable voltage & remote

power source

Immediate wake-upImmediate wake-up


Demo at “Cartes 2009” : Illustration of Tiempo Demo at “Cartes 2009” : Illustration of Tiempo benefits on a PayPassbenefits on a PayPass™™ Magstripe transaction Magstripe transaction

22

11

2211

TAM16 DES • With Tiempo, the processing & crypto time is divided by 6

• PayPass™ Magstripe transaction in 49ms

Sm

art

card

wit

h

sta

nd

ard

ch

ipS

mart

card

wit

h

Tie

mp

o c

hip

s


Proven breakthrough performancesProven breakthrough performances

• Breaking today’s barriers: on a Breaking today’s barriers: on a PaypassPaypass™™ Magstripe transaction Magstripe transaction• Transaction completed in less than

50ms• Processing & crypto time divided by

6• Total transaction time is reduced by

38%

• Breaking tomorrow’s barriersBreaking tomorrow’s barriers• Contactless transaction are

spreading out to more applications in the security conscious industry

• As more processing is required on the card, processing performance (with extremely limited power) is now a key success factor

Smart Card TrendsSept-Oct 2009 (Cover)


TIEMPO technology benefits TIEMPO technology benefits (1)(1)

• Lower dynamic power consumption• Lower energy consumption (/4)• Lower current peaks (/15)

• Lower static power consumption• Power gating at finer-grain level• Cells optimized for lower leakage

• Works at lower voltage level• Ex: 0.6V on CMOS 130 nm GP

• Works at variable voltage range• Robustness against voltage

variations• Easy DVS implementation

• Immediate sleep & wake-up• Transitions in a few ns instead of µs

/5

/3


TIEMPO technology benefits TIEMPO technology benefits (2)(2)

• Lower noise, lower electromagnetic emission• Adapted to systems with EMI constraints

(automotive, medical, aerospace)• High performances

• Operators can work at maximum execution speed

• Allows very modular designs (ideal for multi-cores)

• Higher resistance to PVT variations• Delay insensitivity allows better robustness

against process-voltage-temperature variations• Ideal for advanced technologies (65 nm and

below)• Higher resistance to hardware attacks

• Attacks using power analysis and fault injections

• Ideal for secured systems (smartcards, NFC)


• Technology for the design of Technology for the design of asynchronous asynchronous andand delay delay insensitive insensitive integrated circuitsintegrated circuits• Asynchronous = no clock at all

• Delay insensitive = functionally correct regardless of any delay in gates and wires (no delay assumption)

• Allow designs with both ultra-low power and high performances

• Can be described with high-level models, in standard language

TIEMPO technology principlesTIEMPO technology principles

Asynchronous Asynchronous delay delay insensitiveinsensitive(without clock, (without clock, without delay without delay assumption)assumption)

DataReq

Ack

AReg AReg

HazardFreeLogic

AReg

RegReg LogicLogic LogicLogicRegReg RegRegData

Clock

SynchronousSynchronous(with clock)(with clock)

HazardFreeLogic


AgendaAgenda



TIEMPO IP coresTIEMPO IP cores

• TAM16,TAM16, asynchronousasynchronous 16-bit microcontroller 16-bit microcontroller core core• With peripherals (UART, SPI, I2C, Timers, Int Ctrl..)• With SDK and customizable instruction set• Coming soon: TAM32, 32-bit microprocessor core

• Asynchronous Asynchronous crypto-processorcrypto-processor cores cores• PKA (Public Key Accelerator) for RSA & ECC• AES• DES/3DES

• All cores available with different options: All cores available with different options: • Top-level asynchronous/synchronous interface • Netlist secured against power/fault attacks

TAM1616-bit µC

+ Crypto- processor cores

+ Security counter- measures

TAM3232-bit µP


TAM16 microcontroller coreTAM16 microcontroller core

• Outstanding power Outstanding power performancesperformances• Lower energy consumption

(divided by 4)• Lower current peaks (divided

by 15)• Faster wake-up time (< 5 ns),

immediate sleep mode

• Power-efficient instruction setPower-efficient instruction set• Easily programmable: 65 instructions and 7 addressing modes• Fast and energy-efficient interrupt control and peripheral

communication• Software Development Kit: assembler, linker, instruction set

simulator, C compiler and debugger (based on GCC/GDB)

• Instruction set can be easily customizedInstruction set can be easily customized• To match de-facto industry standards


TAM16 microcontroller chipTAM16 microcontroller chip

• Silicon-proven IP core Silicon-proven IP core • CMOS 130 nm GP technology• Test chip fully operational• With expected performances (speed,

energy consumption)

• TAM16 chip includesTAM16 chip includes• TAM16 core with peripherals• 16 KB RAM, 1 KB ROM (3rd-party)• BIST (412 instructions)

• Next silicon: run in Feb 2010Next silicon: run in Feb 2010• TSMC CMOS 130 nm LP• Asynchronous memories• Multiple power domains • Minimal static consumption

Speed and power measurements on actual chip

Power supply (Volt)

0.7V1.2V

Execution speed (MIPS) 6.1 11.8Core consumption (µA/MIPS)

37.2 47.6


DES crypto-processor coreDES crypto-processor core

• Standard ciphering & deciphering algorithms: DES & 3DES

• Outstanding power performances • Ultra-low power (energy &

peaks)• Ultra-low noise/EMI• High speed (no need for fast

clock)• Secured option

• Protection against attacks (power analysis and fault injections)

• Two interface options• Asynchronous 16-bit interface

(use as TAM16 coprocessor)

• Synchronous 8 or 16-bit interface (integration into sync. designs)

Performances measured on DES4 chip (CMOS 130nm GP)

Supply voltage range

0.6V 1.2V

Max. current peaks 250 µA800 µA

Current consumption 200 µA 1 mA

DES execution time 2.3 µs 250 ns


AES crypto-processor core

• Standard ciphering & deciphering Standard ciphering & deciphering AES algorithmAES algorithm• Key: 128/192/256 bit• Data: 128 bit

• Outstanding power performances Outstanding power performances • Ultra-low power (energy & peaks)• High speed (no need for fast clock)• Two mode: priority on

performance or power

• Secured optionSecured option• Protection against attacks (power

analysis and fault injections)

• Top-level interface choiceTop-level interface choice• Asynchronous interface (use as TAM16 co-processor)• Synchronous interface (integration into synchronous

designs)


Public key accelerator (RSA/ECC)

• RSA & ECC acceleratorRSA & ECC accelerator• Key: up to 2048/4096 bit• Int/Mod operations• Specific functions (FSMs)• Primitives for ECC & RSA

acceleration

• Outstanding power Outstanding power performances performances • Ultra-low power (energy & peaks)• High speed (no need for fast

clock)

• Secured optionSecured option• Protection against attacks (power

analysis and fault injections)• Top-level interface choiceTop-level interface choice• Asynchronous interface (use as TAM16 co-

processor)• Synchronous interface (integration into

synchronous designs)


TAM32 microprocessor coreTAM32 microprocessor core

• Applications: low power & high Applications: low power & high performance embedded performance embedded electronicselectronics• Mobile consumer electronics

• Outstanding power Outstanding power performancesperformances• Lower energy consumption

(divided by 2) for equivalent or higher speed (> 400 MIPS on CMOS 65 nm LP)

• No PLL required (less power)• Lower current peaks (/15)• Fast wake-up time (< 5 ns) and

immediate sleep mode

• Roadmap driven by partnershipsRoadmap driven by partnerships

Instruction memory

Mem

ory

, deb

ug

, cop

rocessor

Data memory

Register File

Multiplier Shifter

ALU

Fetch

Load/Store Branch

Decode

Work inprogress


AgendaAgenda



TIEMPO Design FlowTIEMPO Design Flow

• Specific synthesis: Asynchronous Circuit Compiler (ACC)Specific synthesis: Asynchronous Circuit Compiler (ACC)• Fully-automated synthesis tool for asynchronous design• Using standard hardware description languages

• Input: TLM-like descriptions in SystemVerilog • Output: gate-level netlists in Verilog

• Using standard cell libraries• Complemented (by Tiempo) with optimized asynchronous cells

• Available with IP license or design service

• Standard design flow: use of industry-standard toolsStandard design flow: use of industry-standard tools• SystemVerilog models can be simulated with any HDL

simulator• Easy simulation of mixed asynchronous/synchronous designs

• Implementation with industry-standard P&R and STA tools• Easy implementation of mixed asynchronous/synchronous designs• Asynchronous/synchronous interfaces automatically generated by ACC


STA

TIEMPO flow for mixed TIEMPO flow for mixed asynchronous-synchronous designasynchronous-synchronous design

Verilog/VHDL RTLSynchronous part

RTL Synthesis

Verilog Gate-levelAsynchronous part

Verilog Gate-levelSynchronous part

Asynchronous-synchronous Interfaces

SystemVerilog TLM

Asynchronous part

ACCVerilog, VHDL, SystemVerilog

, SystemC,Testbenches

Verilog, VHDL, SystemVerilog

, SystemC,Testbenches

Tiempo tools

Standard tools

HDL SimulationVMM / OVM

Place & Route


Use of standard tools to Use of standard tools to simulate/debug Tiempo asynchronous simulate/debug Tiempo asynchronous

SV modelsSV models


module FSM ( push_channel_opcode_t.out OP, // Control ALU operation type push_channel_event_type.out ST, // Specifies that opcode has been sent to ALU push_channel_go_t.in GO, // Starts FSM and selects sequence of actions push_channel_bit.in AB // Abort signal (return to initial state S0) );always begin : fsm_process // Unique process implementing the fsm go_t go; bit ab; opcode-t op; state_t state; // local and state variables unique case (state) S0: begin GO.Read(go); unique case (go) SEQ1: state = S1; SEQ2: state = S2; endcase end S1, S2: begin unique if (state == S1) op = ADD; else op = SUB; AB.Read(ab); unique if (ab == 1'b1) state = S0; else begin OP.Write(op); state = S3; end end S3: begin ST.Write(SREVENT); state = S0; end endcaseend endmodule

SV asynchronous model : FSM exampleSV asynchronous model : FSM example

S0

S1

S2

S3

GO = SEQ1

AB = 0

AB = 1

AB = 0

AB = 1

GO = SEQ2


module ALU( push_channel_byte.out Z, // ALU output push_channel_byte.in A, // ALU first operand push_channel_byte.in B, // ALU second operand push_channel_opcode_t.in OP // Control signal to define computation type);always begin : compute opcode_t op; byte a, b, z; // local variables fork OP.BeginRead(op); A.BeginRead(a); B.BeginRead(b); join unique case (op) // computation phase ADD: z = a + b; SUB: z = a - b; endcase Z.Write(z); // output update fork OP.EndRead(); A.EndRead(); B.EndRead(); joinend endmodule

SV asynchronous model : SV asynchronous model : ALU ALU exampleexample

B

Z

ALU

OP

A


AgendaAgenda



Conclusion

• Tiempo innovative design technology offers significant gains in • Ultra low power consumption• Processing speed in power constrained

environments

• Tiempo asynchronous synthesis flow is integrated into standard design flows• Standard language, simulation and back-end tools

Ultra-low power embedded electronics

Mobile consumer electronics

Automotive Aerospace Contactless and otherelectronic transactions


Turn Your Engineering Cost Center Into an IP Profit Center

Turn Your Engineering Cost Center Into an IP Profit Center

© IPextreme, Inc. Confidential Information.

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IntroductionLeveraging Your IP AssetsIP Licensing ExamplesSummary

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Early PeakLate

Extend the Life And Value of Your Designs

Reuse Your Design on Future Projects

Retain integrating customers & manage end-of-chip-life


The IP Challenges

Packaging IP for ease of use and ease of support Preserving the original designers knowledge Consistency in IP delivery package

Knowing what IP is available What IP have we developed? What IP have we purchased?

Tracking usage of IP Who is using the IP? What revisions are being used? Notifying users of updates

Tracking internal usage of IP licensed from IP vendor Ensuring all licensed IP is being used legally

Distribution of IP to users Controlling who receives IP

Supporting IP users Tracking issues across various IP teams and internal users Monitor support costs for each IP

Slide 66


IP Packaging Requirements

Requirement Solution

Ease of UseStandardized IP format for a

consistent look and feel

Low Support CostPackage IP with Designer’s Intent

and Knowledge


IP Database Requirements

Slide 68


Centralized storage of IP IP Database

Users easily browse available IP Organized IP Catalog

Users easily find specific IP IP Search Engine


IP Distribution Requirements


Control who can access IP IP access management

Know who has/is using the IP IP access tracking

Easy communication to users User contact management

Security for IP access Secure IP distribution

Security for IP support Secure file sharing


IP Support Requirements

Slide 70


No lost support requests Support tracking system

Ability to easily find the right person Support ticket routing

Easy communication to IP usersAutomated distribution of IP bulletins

and change notices

Ability to analyze support cost Support hour tracking

Low IP support cost IP support knowledge base


IP User Requirements

Slide 71


Ease of Use Common look and feel

Minimize errors and support cost Self checking parameter settings

Support for all EDA flows Automated EDA script generation


XPack™ IP Management System

CustomerSupport

IP LicenseControl

IP Access & Tracking

IP Repository & Search

Secure WebDistribution

Fully Integrated IP Packaging, Repository, Distribution and Support System

Advanced Search


Examples of IP we have productizedExamples of IP we have productized



IP Commercialization Activities

Activities PartnerDesign Preparation

Packaging

Marketing

Sales

Legal Contracts

Distribution

Support

Maintenance

Revenue Collection

Royalty Reports & Collection


Industry-leading Soft Processors

>200K gates

32-Bit High-End

100-200K gates

32-Bit Mid-Range

40-100K gates

32-Bit Entry Level

TriCore

TriCore14-Stge OCDSFPI

FPU

32 BIT

DSP 3 Pipe

ColdFire

ColdFire v2 4-Stge NEXUSAMBA32-BIT

DSP

Power Arch

e200 z34-Stge NEXUS

FPU DSP

AMBA

MMU

32 BIT

VLE

Power Arch

e200 z67-Stge NEXUS

FPU DSP

AMBA

MMU

32 BIT

VLE

C166

C166 v14-Stge OCDSFPI16-BIT

DSP

HC08

HCS08BDM8-BIT

MMU

Power Arch

e200 z14-Stge NEXUSAMBA

MMU

32 BIT

VLE

Power Arch

e200 z04-Stge NEXUSAMBA32-BIT

VLE Only

ColdFire

ColdFire v1 4-Stge BDMAMBA32-BIT

DSP

8051

M80512-Cyc 8-BIT DBG

8-15K gates

8-Bit Family

CR16

CR16CP3-Stge NEXUSAMBA16-BIT

40-90K gates

16-Bit Family

ColdFire

ColdFire v4 9-Stge NEXUSAMBA32-BIT

DSP MMU


AMBA Peripheral Library

Library of 20 AMBA 2.0 PeripheralsAll proven in high-volume National Semi ProductsLow-cost, royalty-free

AHB-to-APBBridge

AMBA Watcher

DMA Controller

Processor(32-Bit AHB Master)

AHB System Bus

RAM Controller

RAM

AHB Backbone

AccessBus/I2C

Interface

General Purpose USART

Interrupt Controller

Multi-Input Wakeup Module

Real Time Clock

Module

Smart Card Interface

Timing and Watchdog

Module

Versatile Timer Unit

Advanced Audio

Interface

General Purpose I/O

Ports

I2S Audio

Interface

MICROWIRE/SPI Interface

Enhanced Multi-Function

Timer

APB Peripheral Bus

AMBA Library

Full-CAN


#1 Automotive IP Portfolio

Automotive IP Lineup

Controllers

Power ArchitectureCR16C166

TriCore

NetworkingFlexRay

CAN

DebugNexus5001

MCDSCJTAG 1149.7

SerialInterfaces

MLIMSC

Horizontal Peripherals


USB20Hub IP Features

Cypress USB market share leaderProven in Cypress EZ-USB HX2LP™ family of Hub chipsUSB-IF and WHQL certifiedConfigurable: 2-7 downstream ports Single-TT to minimize size or Multi-TT for max FS throughput Once implemented via EEPROM

Supports high, full and low speedUltra-low power, runs on Bus PowerLow gate count, small die sizeFull hardware implementation, no firmware or microcodeConfigurable once implemented via external SPI EEPROM

1.5 Mbps1.5 Mbps

12 Mbps12 Mbps

480 Mbps480 Mbps

480 Mbps480 Mbps

US

B U

pst

ream

Port

US

B U

pst

ream

Port

SerialSerialInterfaceInterfaceEngineEngine(SIE)(SIE)

Hub RepeaterHub Repeater

HS USBHS USBTrafficTraffic

USB HUBUSB HUB

LS USBLS USBDeviceDevice

FS USBFS USBDeviceDevice

HS USBHS USBDeviceDevice

HS USBHS USBDeviceDevice

12 Mbps12 Mbps

480 Mbps480 Mbps Rou

tin

g L

og

icR

ou

tin

g L

og

ic

TransactionTransactionTranslatorTranslator

(TT)(TT)

1.5 Mbps1.5 Mbps

1.5 Mbps1.5 Mbps

12 Mbps12 Mbps

12 Mbps12 Mbps

US

B U

pst

ream

Port

US

B U

pst

ream

Port

SerialSerialInterfaceInterfaceEngineEngine(SIE)(SIE)

Hub RepeaterHub Repeater

HS USBHS USBTrafficTraffic

Multi-TT USB HUBMulti-TT USB HUB





12 Mbps12 Mbps

480 Mbps480 Mbps

Rou

tin

g L

og

icR

ou

tin

g L

og

ic


(TT)(TT)


(TT)(TT)


(TT)(TT)


(TT)(TT)


IEEE 1149.7 CJTAG

Industry’s First CJTAG Core Provides increased functionality to embedded

designs over the IEEE 1149.1 standard Endorsed by IEEE and MIPI standards

organizations for next generation test and debug

Supports IEEE 1149.7 classes 0–5 (selected through hardware configuration parameter)

Partitioned along IEEE 1149.7-specified functional boundaries (so that only the required hardware is included): Extended Processing Unit (EPU) for class 0–3

operation Advanced Processing Unit (APU) for class 4–5

operation Further partitioning within EPU and APU for

class-specific and optional features Separate blocks for clock and reset signal

conditioning

Supports all mandatory and optional scan formats: JScan0–3, SScan0–3, OScan0–7, and MScan

Deliverables Synthesizable source code Integration testbench and tests Documentation Scripts

• Simulation and synthesis• Support for common EDA tools


HighlightsHighlights

Main FeaturesMain Features

BlueMoon 2.1® Bluetooth 2.1+EDR

Single core Bluetooth solution Integrated RF, Baseband, Firmware (ROM-able) Connection to host via standard HCI UART

Bluetooth 1.2, 2.0 + EDR & 2.1 + EDR compliant Firmware upgradable to Bluetooth 3.0

Enhanced Data Rate Throughput >2Mb/s (3Mbps modulation)

Compatible with all 3rd-party Bluetooth applications Through standard HCI software interface

Advanced features for enhanced audio qualityFirmware in integrated ROM for lowest cost

Patch RAM area for easy firmware upgrades

Roadmap for Bluetooth Ultra Low Energy

0.13 µm standard CMOS (UMC) RF amplifier output max +7 dBm at package pin RF sensitivity -89 dBm(BDR) @ 0.1 % BER

-91 dBm(EDR) @ 0.1 % BER

HCI interface UART alt. 3-wire, up to 3.25Mbaud Dual PCM audio interface ( I2S mode, A-law, µ-law, Linear ) 3-wire WLAN Coex interface Control lines for external Class-1 PA Clock input 26 MHz 32kHz Low Power Clock input (optional)

Link Controller Baseband Radio

UART

RAM

ROM

Firmware

PCM

GPIO

Power Management

PCM

HCI

32-Bit CPU

Tx

Rx

Tx

BTDSP

Output Power Control

BlueMoon Block Diagram

Rx


SummarySummary



XPack - IP Management System

Packages IP for reuse Packages designer knowledge with IP Consistent look and feel with configuration GUI Automated EDA script generation (EDA tool neutral)

IP database cataloging and searchLicense Management prevents unauthorized usage of IPSecure IP distribution and secure file sharingComplete support infrastructure to lower support costs and accelerate resolution of support requestsConfigurable and customizable to match your company’s precise requirements

Packages and manages IP assets for higher productivity, lower cost and lower risk


IP Portfolio

32-bit Microprocessors Freescale Coldfire v1, v2, v4 Freescale Coldfire v1 for Altera Cyclone III Freescale Power Architecture Infineon Tricore

16-bit Microprocessors Infineon C166 National Semiconductor CR16

8-bit Microprocessor Mentor Graphics M8051 Freescale HCS08

AMBA Interfaces USART, I2S, I2C, AAI, Microwire, CAN

AMBA System Functions Interrupt Controller, DMA Controller, RAM

Controller, Timer & Watchdog, Timers RTC

Debug Texas Instruments 1149.7 CJTAG

Cypress USB 2.0 Hub

Infineon BlueMoonTM Bluetooth 2.1+EDR IP Licensing BlueMoon Die

Automotive Freescale FlexRay Infineon MultiCAN Infineon Microsecond Channel Infineon Multiprocessor Link Interface

Technology Licensing Motorola Digital Clock Generator

• PLL Replacement

Infineon Multicore Debug System• Automotive multiprocessor debug system


IPextreme Summary

World’s Leading Supplier of Production Proven IP from Leading IDMs

IP and Design Reuse technology and expertise

100% focused on semiconductor IP

Please let us know how we can help


Welcome to the Future – Start Running

Every morning in Africa, a gazelle wakes up

It knows it must outrun the fastest lion or it will be killed

Every morning a lion wakes up

It knows it must outrun the slowest gazelle or it will starve

It doesn’t matter whether you are a lion or a gazelle

When the sun comes up, you better start running – African proverb

Thank You!!!


Business Model Panel

87

Turn-key IP Block to Simplify AMBA-based SoC Designs

Turn-key IP Block to Simplify AMBA-based SoC Designs

88

Sonics – Company IntroductionSonics – Company Introduction

OEMs

Licensees• Sonics set out to solve the biggest problem facing the SoC industry: Ever increasing design costs.

• Sonics has succeeded in dramatically lower design costs by developing highly configurable IP for the on-chip communications networks that enable the design of complex chips.

• The world’s leading companies have turned to Sonics for their most demanding SoCs designs, and in turn they have sold more than 750 million chips based on Sonics’ IP.

• Sonics has invested over $65 million to develop its unique IP, resulting in more than 50 patent properties.

• Sonics is the Number 1 global provider of on-chip communications network IP.

89

Sonics Network for AMBA Protocol - Product OverviewSonics Network for AMBA Protocol - Product Overview

Sonics is addressing the industry problem of building SoCs that have an increasing number of heterogeneous cores with a fast and reliable methodology

• SNAP is the first turn-key product on the market that turns a multilayer AHB design into an IP block

• Ideal for Embedded SoCs with a large number of IP cores having AHB and APB interfaces but also contain other interfaces like AXI and/or OCP

• Product is optimized for low-gate count• Simple to use tools that require little or no training along with a unique ‘client-

server’ model to reduce cost• Reduces customers’ development cost - not wasting engineering resources on

complex multilayer designDesign time is reduced from months to days! ‘Good by design’ IP reduces test and debug time

• SNAP is ideal for Embedded SoCs for in the follow market segments:• Wireless communications: 3G/4G basebands, WLAN, WiMax• Wired communications: Home gateways, wireless routers• Consumer electronics: PMP, MP3• Automotive: Control, Telematics

90

SNAP High-Level ArchitectureSNAP High-Level Architecture

• Replace traditional bus with advanced on-chip Network:– Interconnect Matrix

– AHB Masters Layers

– AHB/APB Branches

• Data Flow services

• Decoupled socket based architecture

• Power Management

• Memory scheduler (optional)

91

You are Ready for SNAP when…You are Ready for SNAP when…

Your SoC Connectivity is growing in Complexity:

• Increasing number of cores with new and legacy interfaces

• Reaching the limits of AHB bus performance• Increased engineering resources needed due to

the shortcomings of existing bus design tools and methodology

• Evolving designs to incorporate faster processors • ARM AXI processors • MIPS AHB, OCP processors

• Re-architect designs to optimize for low power• Hitting the Memory Bottleneck

• AHB designs have a bottleneck at the memory port

• Lack of concurrency and frequency limit the solution

Simplify Your Design:

• No need to worry about clocks, arbitration, bus widths or data formats

• Provides protocol translation

• Reduce wire congestion

• Provides clock division bridges

• Allows engineering innovation for value-added functions

92

SNAP FeaturesSNAP Features

• Hubs (aka interconnect matrix, crossbar, exchange):

• Provide dedicated connections between agents embedded in the hub. SNAP allows two hubs per design which can be connected through a pipeline point

• Layers

• Allow multiple masters to be connected to a single hub port

• Branches

• Allow multiple slaves to be connected to a single hub port

core core core

slave slave slave

93

Client-Server InteractionClient-Server Interaction

SNAP Server

Company A

Internet

Company B

Overview• Simple and free download of the SNAP Capture

tool – No tools purchase necessary• Users configure their designs using the

snapCapture GUI• User uploads design to SNAP Server• The SNAP Server then sends back RTL,

synthesis scripts, and test bench.• Server keeps track of user ‘credits’

SNAP Client 1

SNAP Client owner

SNAP Client NSNAP Client 1

SNAP Client 2

SNAP Client Owner… …

Internet

94

SNAP Design CaptureSNAP Design Capture

• Interface Overview:

Tool BarTool Bar

SNAP Components

SNAP Components

DesignWindow

DesignWindow

ConfigurationTabs

ConfigurationTabs

QuickHelp

QuickHelp

95

Sample SNAP Design - OverviewSample SNAP Design - Overview

Set Top Box • SoC Design Features• 19 Masters

• CPU subsystem, DSP subsystem, Video subsystem

• 39 Slaves• Audio, USB, Storage,

Memory

• System Speed: 200MHz

96

Sample SNAP Design – System Block DiagramSample SNAP Design – System Block Diagram

97

hubSYS

VF

E

SATA

VB

E

ED

MA

Apb

Sb

0

Sto

rag

e

CO

MM

hubLL

ddr2sram

ARM9IDSP

ARM9D

SIO

SY

SC

axi

ahb

apb

ocp

Sample SNAP Design – SNAP view of block diagramSample SNAP Design – SNAP view of block diagram

98

Sample SNAP Design – SNAP GUI Design CaptureSample SNAP Design – SNAP GUI Design Capture

99

Sample SNAP Design – By the numbersSample SNAP Design – By the numbers

• Frequency• Target: 250MHz

• Synthesis: 465MHz

• Synthesis (w/ 30% margin): 325MHz

• Area• TSMC 65G: 146K gates

• Only 2500 gates / core

• Cost to add additional…

• AHB Master layer: 900 gates

• AHB Master: 1000 gates

• AHB Slave branch: 1500 gates

• AHB Slave: 100 gates

• APB Slave branch: 20 gates

• APB Slave: 45 gates

146K gates

100

Summary - BenefitsSummary - Benefits

• Increased design productivity – multilayer interconnect is one IP block with easy to use GUI• Seamless upgrade path from a multilayer AHB architecture• Superior performance, power, and area than competitive solutions using

AXI matrix + AHB buses

• Ultra-low power with Automatic clock gating

• High performance • Cross-bar structure, separate request / response network• AHB multi-ports agents: up to 8x the bandwidth of an AHB bus

• Supports all popular interfaces• Does all the protocol, data width and clock conversions• No need for bridges• No stand alone validation required

• Lowest risk - Fully verified IP

SidenseNon-Volatile Memory IP

March 31, 2010

102 The Future of Logic NVMTM

Company Profile

Name: Sidense Corp. - Private

Founded: September 2004

Headquarters: Ottawa, Canada

Offices: USA, Japan, Korea, China, Taiwan, and France

Product: One-time-programmable (OTP) antifuse-based non-volatile memory (NVM) targeting standard-logic CMOS processes

Employees: 40+

Customers: 80+ customer designs

Patents: Over 60 patents issued or pending


Embedded NVM Landscape

Low Scalability challenges High

Floating Gate

NORFlash

Mask

ROM

2TNVM

POLYPOLY

eFUSE

40nm

180nm

130nm

90nm

65nm

Pro

cess C

om

ple

xit

y

32nm


A Better NVM Solution


Target Markets and Applications

RFID Tags

HD Set-top Boxes

Micro-controllers

Hearing aids

HD recorders

RFICs

Configurable Processors DVD players

Timer chips

Military/Space

Industrial Equipment

Smart Phones

Implantable devices

Automotive ICs


The Sidense Edge (Top 5 Reasons)


Smallest Bit Cell – 1T Split-Channel

WL

1T-Fuse™BL

ISOLChannelN+ LDD

1T-Fuse™BL

N

1T-FuseBL

Program Area

The only reliable 1T architecture

IO Oxide

Gate Oxide


Broad Foundry and Node Support


Technology Flexibility

32 Kbits Mask ROM

16 Kbits Single-cell

512bits x16 eMTP

4 Kbits x2 Fast Read

2

Kw

ord

s1

K

word

1 K

word

16-bit IO

SiP

RO

M -

64

Kb

its (

4K

x1

6)


Highly Secure – Code and Data

Bit 1 Bit 2


Most Reliable Bit-Cell Architecture


SiPROM – High-Density NVM


SLP – Very Low Power NVM

F - PROM

SHIFT REG

PGM / Verify CTRLWE

VS

S

SEL,

OE

OTP

IO Latch

PGM CTRL

CLK

MODE

VD

D

VR

R

A

Q

VP

P

D


Summary

Can You Trust Can You Trust Your IP Vendor?Your IP Vendor?

How Not to How Not to Lose Sleep Lose Sleep

Over itOver it

Can You Trust Can You Trust Your IP Vendor?Your IP Vendor?

How Not to How Not to Lose Sleep Lose Sleep

Over itOver it

Hal BarbourPresident, CAST, Inc.

Constellations Seminar — slide 116

IP Horror StoriesIP Horror Stories

We all hear about the “bad IP” news Unfulfilled promises Missed deadlines Poor quality code & materials Lousy support

IP companies have come and gone Amphion inSilicon Dozens of smaller companies


Trust is a Key FactorTrust is a Key Factor

Even the best IP will present some technical challenges

What matters most is if you can trust the provider to help you make it work External, commercial IP vendor In-house, IP & reuse group

But how do you judge trustworthiness in advance? A matter of continual style, not a simple check-list Every organization has it’s own style, just like an

individual’s personality

There are some critical things to look for …


First Impressions MatterFirst Impressions Matter

Do they freely provide important information? Can you: Download datasheets without registering? See sample ASIC & FPGA implementation

results (Fmax, resource numbers) without asking?

Does their paranoia get in the way? Do they require an NDA for basic technical info? Do they demand an NDA for price info?

Do they waste your time? Are you buried in marketing fluff? Will they quickly get you tech docs,

design specs, etc.?


Can They Run with You?Can They Run with You?

Is the organization geared towards rapid, effective response?

What is their process for responding to technical questions?

Do their engineers seem as good as yours?

How do they deal with time zone differences?


Can They Deliver What They Promise?Can They Deliver What They Promise? Do they they know how to productize IP

for easy reuse?

Do they have a track record of financial success? Are they profitable? Any short-term

investor pressure?

Is IP critical to their success (or design services)?

Will they give you customer references? Don’t go by published “testimonials” Ask for — and talk with — engineers who have already

used the IP you want


Do They Understand System Integration?Do They Understand System Integration?

Do they help make sure the IP is best for your specific project?

Most problems with a core are really problems understanding the application and designing the system correctly


System Integration ExampleSystem Integration Example Challenge:

Need means for customers to try complex compression technology

Enable evaluation with own media, algorithm & core study, system dev head start

Solution: H.264/JPEG 2000

Reference Design Platform Multiple CAST cores FPGA Prototyping Board SW GUI for Parameters &

Control


Licensing & Sales IssuesLicensing & Sales Issues

Does the licensing meet your needs? Straight forward and adequately flexible Doesn’t bury you in legal minutia

Is the pricing competitive? A good value for you A reasonable business

model for them (you want the vendor to stay alive)


Post-Sales TrustPost-Sales Trust

Do you seem to matter as much after the sale as before?

Do they have highly-commissioned salespeople who are now on to their next deal?

Is their Support Organization effective?

Would you buy from them again?


CAST Knows About Building TrustCAST Knows About Building Trust

Successful IP provider, developer, and partner Sixteen years experience with IP Continually profitable, no debt Privately held, financially stable

Unique market approach We only do digital IP,

designed for reusability Independent of semiconductor

technologies and EDA tools

Effective Virtual Organization Global team of ~100 people:

stable, long-term partnerships 24/7 culture with very fast response Always online with Email, IM & Skype Original developers available to

help with support

Experience with diverse customers and applications 1,000 sales to over 600 customers Pre-sales help in selecting the right IP Post-sales support during system integration


CAST Knows About Building TrustCAST Knows About Building Trust


Broad IP Product LineBroad IP Product Line


CAST IP HighlightsCAST IP Highlights 8051s — the fastest and smallest available versions,

from the largest independent supplier

H.264 — the highest-quality 1080p Baseline video encoder

Image Compression — the most choices, JPEG to JPEG 2000

PCI Express — easy system integration with application interface

USB — a complete family of solutions

Memory Controllers — advanced IP for DDR, NAND Flash, SD, SDR mobile

System IP Solutions — pre-integrated cores and software for a system design head start


ConclusionsConclusions

In judging IP provider trust:

The quality of the people and character of the company can ultimately be as important as the product

Choose wisely, and get some sleep!

Chips&Media, Inc.

Selecting the right HD Video IP for Multimedia Applications

Market Outlook

Confidential

Market Outlook

HD Home CE MarketHD Home CE Market

4569

97

128

226

292

338

Unit : Million unit

Source : iSuppli, In-Stat, Futire Horizons , C&M

Multimedia Market Opportunities

Confidential

SoC Technology Challenge

Users Expectation Rapidly Changing

Rich multimedia experience

Computing functionality

Wireless connectivity options

“Always ON”

Compact and light design

Increasing number of cores

Gigabits of frequency

interfaces

Increasing process variability

Exploding data volume

Low power modes

Small foot print

Rising Complexity in SoC Design

Increasing Complexity and Time to Market Pressures drive SoC Challenge

Confidential

In-House vs 3’rd party IP

In-house vs. Third-Party Multimedia IP Market Share for 2009

Note : Includes the use of any 3rd party Intellectual Property for graphics, audio or videoSource : In-Stat, 9/09

Buying IP is main stream for designing Mobile System-on-Chip(SoC)

Selecting Good Quality IP

Confidential

Selecting Good Quality IP for Multimedia

Die size(mm2) / Cost($)

Performance (MHz)

Power (mW)Bandwidth management (MB/s)

Multi-standards

Confidential

Die Size (mm2) & Cost ($)

Silicon cost – driven by die size

6.0mm2 in TSMC 90G with 200MHz cclkIncluding 2.0mm2 Internal SRAM

BIT Processor

H.264

AMBA BUS

MPEG2 MPEG4 VC-1 DivX

RV H.263 WMV Spark AVS

MJPEG

Boda7503

Boda7503

Boda7503-MJPEG

- RV

- VC1- AVS

- H.264

-MP4

Logic gate count can be reduce by pre-configurability of decoding format according to target applications

Confidential

Performance (MHz)

Resolution

High performance video processing

20MHz

60MHz

133MHz

Clock required

Higher clock rates mean higher power

Boda7503 decodes H.264 HP up to 1080p 30fps at 133MHz

Confidential

Performance - Latency Resilience

High Memory Latency Tolerance Minimize the effect of memory latency on decoding performance # of Cycles (decoding H.264) vs Memory Latency

Boda7503 decodes in time– even if bus latency approaches 200 cycles

Memory access latency(cycles)

0 100 200 300 500

Higher bandwidth requirements

Lower bandwidth requirements

Confidential

Power Consumption (mW)

Active management of dynamic and leakage power

Saving power using Clock gating from 17%~ 30%

Clock gating scheme : Clocks can be shut down from blocks currently not needed

Boda7503 uses multi-level clock gating to lower power consumption

Confidential

Bandwidth Management - Bandwidth requirement(MB/sec)

Problem

Preventing memory bandwidth congestion may be challenging with HD

resolutions.

Additional SRAM may reduce an amount of bandwidth, but increase SOC size.

2D smart cache

Smart algorithm of cache control will make significant bandwidth reduction,

with a little sacrificing in die size

An optimized mapping configuration to store data (i.e H.264 pixels) into

external memory decrease the transfer amount between the decoding unit

and the memory.

Confidential

Bandwidth Management - Bandwidth requirement (MB/sec) cont’

Tiled memory map

Taken from the 100 frames of the clip “AVC=MP Allegro_BdWidth_CABAC_01_L41_HD”

Boda7503_LinearBoda7503_Linear Boda7503_TiledBoda7503_Tiled64b-SDR@c=266,a=266

32b-DDR2@c=266,a=266

Alleviate the BUS traffic congestions by 20% by increasing efficiency of bus

utilization

Confidential

Multi-standards

Extensive Multi-format Video Support to Enable the MORE

Enables MORE adaptable devices Enables MORE adaptable

districts Common format Common format

• H.264, MPEG-4, MPEG-2

Popular format by district

Popular format by district

• KOR : DivX• CHN : RMVB, AVS• US : VC-1

H.263

Mobile

DTV/STB

Portable

Blu-ray

Confidential

Multi-standards cont’

Format

Internetstreaming

Portable Mobile DTV STB DVD Security

H.264 O O O O O O O

VC-1 O 　 O

WMV9 O O O

H.263 O

MPEG-4 O O O O

DivX O O

MPEG-2 O O O O

AVS O O

RMVB O O

Sorenson O

MJPEG O

Application

Boda7503 supports multi-codec in a single core

Confidential

Chips&Media Solution

BODA/CODA video codec hardware blocks provides : Cost-effective small gate count Full HD decoding/encoding at lowest power Lowest bandwidth with high latency tolerance Multi-codec supported covering broadcasting, web or PC contents

Selecting Verified IP Provider

Confidential

IP-provider Selection Criteria

Selecting Verified IP Provider by Assessing the Risk of Failure :

Does the company have a history of commercially manufacturing the IP? Customer references Silicon-proven and market-proven experiences

Does the company have the experience and support level you need? Standard documented design support Dedicated R&D engineers involved in support

Does the company develop all IP deliverables itself? Technology leadership R&D expertise and practices

Does the company have clear strategy to keep long-term partnership? Financial records enough to maintain Competitive product/technology roadmap

Confidential

Summary

What does Chips&Media Deliver?

The Best-in Class IP Best class performance Power and silicon area leadership Rich video decode and encode IP portfolio

Complete & Reliable IP Fully-verified IP deliverables Worldwide +40 customer references Over 70 consumer devices powered Chips&Media’s technology

Strong support capability Dedicated technical support with rich experience in the field Fast and in-depth support service via ticketing system

Complete product roadmap Continuous investment in employees and technologies Competitive roadmap to response for the most market requirements

Q&[email protected]

om

Slide 150

Afternoon Break20 Minutes

Ultra Low Power CoolFlux DSP Cores Sweetening Your Green Chip Dreams Licensable for SoCs, ASICs & ASSPs Bringing Affordable Ultra Low Power DSP Performance to your Chip Designs

Constellations Event, March 31st, 2010

© NXP B.V. 2010

152

Overview

CoolFlux success stories in Audio and 4G Basebands

Ultra Low Power Performance Design

Cool Technical merits for Green Chips

Application Software and Development Tools for high productivity

Conclusions

© NXP B.V. 2010

153

CoolFlux Success Stories

Cool References to CoolFlux DSP – DSPFactory, (now part of On Semiconductors)

licensed CoolFlux DSP for their ultra low power hearing aid chips

– Phonak, licensed CoolFlux DSP for their ultra low power digital audio hearing aid communication system

– Cochlear, licensed CoolFlux DSP for next generation Hearing Implants

– Other known users of CoolFlux DSP are Renesas and NXP next to 2 undisclosed global 2008 top 10 semiconductor companies and many other fabless semis and system companies.

Cool Application areas– CoolFlux DSP is used in chips for Headphones

and Headsets, MP3 players, Mobile Multimedia, Blue Ray players, Wireless Audio, Car Stereo, Digital TV … any embedded audio subsystem is candidate

– CoolFlux BSP is used in chips for WiMAX and multi-standard software defined radio basebands chips for emerging 4G standard LTE

© NXP B.V. 2010

154

CoolFlux DSP/BSP Design Goals

Domain: – CoolFlux DSP: Audio, – CoolFlux BSP Software Defined Radio & Wireline Basebands

Ultra low power consumption– Well balanced with good performance and low gate count– ULP techniques used throughout the design hierarchy like

• Clock gating• Operand isolation• Locality of reference

Programmable in ANSI-C– Highly optimizing and efficient compiler – More maintainable and shorter SW development schedules, without loss of quality

Small core, small memory footprints, minimizing dynamic and static power

Core to be usable: – Stand-alone mode (including control)– Coprocessor for microcontroller – Multi-core, also to cool down chips: reducing voltage and clock through parallellism

© NXP B.V. 2010

155

CoolFlux DSP architecture

24/56 bit data paths (CF6-24)

2x 24x24 bit multipliers

2x 56 bit ALUs + 1x24 bit ALU

4x 56 bit accumulators

JTAG debug interface (multicore)

8 Operations in parallel per clock cycle

© NXP B.V. 2010

156

CoolFlux BSP Architecture Enhanced for Baseband Signal Processing

All 24/56 bit data paths of CoolFlux DSP usable backwards compatible at C-level

24 bit addressing

PLUS:

Modes for Complex Arithmetic and SIMD

8x 12x12 bit multipliers

4x 12/28 bit ALUs + 2x12 bit ALU

4x 28 bit dual accumulators

Instruction enhancements for FFT and Viterbi

RESULTING IN e.g.:

20 Operations in parallel per clock cycle

2 cycle complex butterfly Radix-2 FFT level performance

© NXP B.V. 2010

157

CoolFlux DSP – Cool Well Balanced Results*

Small core: – 43kgates + 4.5kgates JTAG

Good Performance (svt lib) – peak MOPS = 8x MIPS (=MHz)

– >200 MHz WCCOM @ 1.2 V 130 nm CMOS– >245 MHz WCCOM @ 1.2 V 90 nm CMOS– >300 MHz WCCOM @ 1.2 V 65 nm CMOS– >339 MHz WCCOM @ 1.1 V 45 nm CMOS (>2700 MOPS)

Low Power Consumption (core only)– 80 μw/MHz @ 1.2 V in 130 nm CMOS– 36 μw/MHz @ 0.8 V in 130 nm CMOS– 60 μw/MHz @ 1.2 V in 90 nm CMOS– 27 μw/MHz @ 0.8 V in 90 nm CMOS– 45 μw/MHz @ 1.2 V in 65 nm CMOS– 20 μw/MHz @ 0.8 V in 65 nm CMOS– 20 μw/MHz @ 1.1 V in 45 nm CMOS– 11 μw/MHz @ 0.8 V in 45 nm CMOS

*Numbers based on svt digital CMOS libraries, comparable with TSMC. Synthesis optimized for power consumption. Results subject to change and depend on used technology, library selection and synthesis settings

© NXP B.V. 2010

158

CoolFlux BSP – Cool Well Balanced Results*

Small core: – 65kgates + 4.5kgates JTAG

Good Performance (svt lib) – peak MOPS = 8x MIPS (=MHz)

– >190 MHz WCCOM @ 1.2 V 130 nm CMOS– >290 MHz WCCOM @ 1.2 V 90 nm CMOS– >290 MHz WCCOM @ 1.2 V 65 nm CMOS– >310 MHz WCCOM @ 1.1 V 45 nm CMOS (>6200 MOPS)

Low Power Consumption (core only)– 120 μw/MHz @ 1.2 V in 130 nm CMOS– 53 μw/MHz @ 0.8 V in 130 nm CMOS– 90 μw/MHz @ 1.2 V in 90 nm CMOS– 40 μw/MHz @ 0.8 V in 90 nm CMOS– 70 μw/MHz @ 1.2 V in 65 nm CMOS– 31 μw/MHz @ 0.8 V in 65 nm CMOS– 31 μw/MHz @ 1.1 V in 45 nm CMOS– 17 μw/MHz @ 0.8 V in 45 nm CMOS

*Numbers based on svt digital CMOS libraries, comparable with TSMC. Synthesis optimized for power consumption. Results subject to change and depend on used technology, library selection and synthesis settings

© NXP B.V. 2010

159

Software development environment(Target Compiler Technologies tool suite, distributed by NXP)

CoolFlux DSP & BSP ISA designed together with compiler for best compiler performance, starting from existing compiler

– Highly efficient ANSI-C compiler: compact, cycle efficient code, exploiting instruction level parallelism

– No extra assembly programming needed

– C-compiler friendly cores

Cycle-true, bit-accurate instruction set simulator

– Source level graphic debugging– Extensive profiling information

Complete tool suite available– Assembler, compiler, linker, simulator

and debugger

© NXP B.V. 2010

161

Large (and growing) Appl. Software LibAvailable : CODECS

MP3 CODEC

WMA9 Decoder

AAC LC Decoder with Dynamic Range Compression

AAC-LC Encoder with Long Windows, MS Stereo, TNS enabled

HE-AAC Vs. 1 & 2 CODEC

IMA ADPCM CODEC

AMR NB CODEC

AMR WB CODEC

Wideband Speech CODEC G.722

High quality low bit rate voice decode and encode (<10k-bps)

SBC CODEC for Bluetooth Audio

OGG Vorbis decoder

BSAC decoder

AC3 CODEC (5.1-Stereo)

Available : SOUND PROCESSING

Graphic equalizer

Spectrum analyzer

Dynamic Bass Boost

Surround Sound

Noise reduction for voice rec.

Time Scaling var. speed/keep tone for voice

MIDI playback

Sample Rate Converter

Up/Downsampling filters (first stages) for sigma delta convertors

Available: RADIO

FM demodulation

Stereo Decoding

AM demodulation

RDS demodulation

Available : OTHER

Bluetooth Audio Upper Stack

Mathematical library

JPEG decoder

USB Audio Device Class

Soon Available:

LifeVibes Voice Engine (AEC, Noise reduction)

Dolby Mobile

Future Roadmap:

G711 Voice CODEC

DTMF Touch Tone

MPEG Surround

More Multi Channel Audio CODEC's

VOIP Stack

RealAudio decoder

WMA9 Encoder

WMA DRM 10

Lossless Audio Codec

Text to Speech (TTS)

More available on customer request , future roadmap subject to customer driven changes

© NXP B.V. 2010

162

CoolFlux BSP software libraries

12-bit complex mathlib– FIR– Radix-2 FFT/IFFT– Radix-4 FFT/IFFT– Vector functions (add, sub, mul, etc.)– Complex/polar conversion

12-bit SIMD mathlib– FIR– Vector functions– IDCT

24-bit fixed point mathlib– FIR– IIR biquad– Vector operations– Complex FFT/IFFT– Real FFT/IFFT– Quantizers

• Linear• ADPCM

– IMDCT– sqrt– ln

Communication library– Viterbi decoding

• R=1/2, 1/3• Puncturing/depuncturing

– Mapper/demapper• BPSK, QPSK, 8PSK• DBPSK, DQPSK, D8PSK• 16QAM• 64QAM

– GFSK– Pseudo-random generator

• Prbs11• Prbs15

– FEC• Reed-Solomon encoder/decoder• CRC

– OFDM Channel tracking• Estimator• Corrector

– Synchronizer• Autocorrelation

– Frequency offset compensation– Time/Interleaver/Deinterleaver– OFDM

© NXP B.V. 2010

163

Summary

The CoolFlux DSP & BSP are ultra low power programmable core optimized for audio & software defined base band applications

– Well-balancing power, area and performance– C-compiler friendly– Robust market proven IP, over 6 years in business now without any HW bug

had to be corrected– Extensive Application Software Library available– Lowest Total Cost of Ownership (TCO): small area and software costs

World wide adoption by Tier 1 Semiconductor companies and OEMs

We offer partnership providing world leading expertise in:– Ultra low power systems design– Digital audio algorithms and acoustics & Modem development– DSP SW maintenance– IP design in support

THANK YOU, any questions ?

Rest in the comfort and security of knowing you have Selected the

Optimum Memory IPs Farzad ZarrinfarNovelics Corp.

[email protected]

IPextreme Constellations Conference - Silicon Valley 2010

March 31th, 2010, Santa Clara, Ca

mailto:[email protected]

©2008 Novelics Proprietary & Confidential

Applications Driving Embedded Memory Usage

Leading-Edge Applications Requiring

High-performance, Low-Power, & High-Density

Embedded SRAMs, DRAMs, Caches, CAMs, Flashes, OTPs, MTPs, ROMs, etc. High-PerformanceCAM, Cache, SRAM

Networking

High-PerformanceDRAM & Cache

Office Automation

High-PerformanceLow-Power & High-Density

SRAM, DRAM, FlashMobile

High-PerformanceWide Memory Buses

LCD & Other DisplayApplications

High-DensityHigh-Reliability

MTP, OTP, Flash Automotive

High-PerformanceLow-Power

High-DensityDRAM, SRAM, Cache, OTP

Multimedia Applications


SoC Embedded Memory Usage on typical SoC

0102030405060708090

100

Percentof

Area

1999 2000 2005 2008 2011 2014 2017

Year

Area Memory

Area ReusedLogic

Area NewLogic

Increasing amount of on-chip memoryIncreasing amount of on-chip memory

Source: Semico Research Corp. – ASIC IP report; 2007


Optimized Memories – Automatically Generated!

Full nodes: 180nm, 130nm, 90nm, 65nm, 40nm

Half nodes: 160nm, 152nm, 110nm, 55nm

Power

Best Solution

Speed

Density

Reliability

Cost

Market Demand for Memory IPs

167


Critical Factors in Selecting Mem. IPs

• Architectural Factors

• Implementation Factors

• Business Related Factors

168


Architectural Factors

169


•Separate power island

•APB

•AHB

CPU

16 KB-I 4-way

coolSRAM-6T

8 KB-D4way

coolSRAM-6T

3D Graphics

Processor

2D/3D Sound

Processor&

Audio Codec

2D GraphicsProcessor

(Layering Engine)

DigitalSignal

Processor IP

NTSC/PALEncoder

TFT/STNLCD

Controller

Video

DAC

Configurable coolSRAM-1T

NAND Flash

Controller

802.11 nBB& RF

Arbiter/ AHB to APB

Bridge*

DMA

Controller

SDIOHost

Controller

Program

Memory&CoolROM & coolREG

PCI

Cont.SPI PMU RTC

USB

Cont.TIMER*

PLLs

POR

Key I •F

•WAKEUP •Signal

•UART

Wide data buses

Embedded Memory Usage on typical SoC


MemQuestTM: Memory Compiler

171


Novelics Memory Engine & Optimizer

Area/Power/Speed Trade-offs

.pdf

.lib

.lef

.v

.mbist.cir

.gds

Exploration

Front-End View Compiler

Back-End View Compiler

Architectural Analysis & Implementation

MemQuestTM

1

2

3



• Selection Tradeoffs Area, Speed, Dynamic Power, Leakage, Data Retention,

Custom /std PVT, Block-by-block leakage control

• Selection of SRAM/ROM Bitcell Alternatives • Memory Repair

173


Memory Compiler for Architectural Analysis

04/10/23175


coolSRAM-6T vs competitor in TSMC-65LP

04/10/23176

Memory cut

Competitor IP Type

Competitor vs Novelics

depth width Size (bits) Area Tac (ns) Pwr (uA/Mhz)

64 8 512 SP 139% 188% 121%

32 64 2048 SP 176% 213% 219%

128 32 4096 SP 142% 169% 194%

512 32 16384 SP 109% 136% 178%

1024 32 32768 SP 108% 118% 207%

2048 16 32768 SP 106% 118% 201%

576 64 36864 SP 108% 132% 205%

1408 32 45056 High Speed 105% 125% 197%

2048 32 65536 SP 107% 111% 332%

1024 64 65536 SP 104% 119% 221%

4096 64 262144 SP 99% 129% 265%


• coolSRAM-6TTM:• Lowest-power, highest-speed AND highest-density

• coolSRAM-1TTM: • Only 1T SRAM in portable bulk CMOS process

• coolROMTM: • Densest single layer programmable ROM

• coolREGTM:• Highest-speed, multi-ports

Novelics is the Innovation Leader

177



• Selection Tradeoffs • Selection of SRAM/ROM Bitcells Alternatives

SRAM:1T, 6T, 8T 1T Alternatives : Stack Poly, Trench Well, MIM, Bulk CMOS (No additional

masks) ROM Alternatives: Metal/Via/Diffusion Programmable Single & Dual VDD, Single & multi-VT

• Memory Repair

178


Typical Six-Transistor SRAM Cell


Typical Single-Transistor/Single-Capacitor Dynamic Memory Storage Cell

Typical One-Transistor SRAM Cell


coolSRAM-1T

coolSRAM-6T

Technology Node (nm)

Den

sity

(M

bit

/ m

m2 )

Memory Density Scaling – Bulk CMOS

181



• Selection Tradeoffs • Selection of SRAM/ROM Bitcell Alternatives • Memory Repair

(1C, 2C, 2C2R, ..Optimum Tradeoff?)

182


Implementation Factors

183



• Silicon Characteristics vs Simulation Commercial, Medical, Military/ Aerospace

• Memory Compiler Deliverables• Datasheet Components• Testability/BIST/Reliability/ Routability/Margin

Control

184


coolSRAM-1TTM in Standard CMOS

• Measured cell retention time• For a chip containing 4 Mb, the yield is > 95%

without using redundancy or ECC

Silicon (ms)Simulated (ms)

Temperature OC

Cell R

ete

nti

on

Tim

e (

mS

)

185



• Silicon Characteristics vs Simulation • Memory Compiler Deliverables• Datasheet Components• Testability/BIST/Reliability/ Routability/Margin

Control

186



• Silicon Characteristics vs Simulation • Memory Compiler Deliverables

Datasheet Verilog model with SDF annotation support model Synopsys .LIB model (based on Spice characterization data) LEF, .NET files GDSII Documentations

o Application note & integration guideo Versions for design rules, command files, spice models & bitcells

• Datasheet Components• Testability/BIST/Reliability/ Routability/Margin Control

187



• Silicon Characteristics vs Simulation • Memory Compiler Deliverables• Datasheet Components• Testability/BIST/Reliability/ Routability/Margin

Control

188


Compiler Generated Data Sheet -1st Sheet

189


Datasheet ComponentsGeometry Dependent

• Target Process, Top level IP diagram, external pin definition, Timing diagram for IP functionality/ operation, AC/DC Specifications• Power Consumption

190

Min Nominal Max Unit

Active Power a b c uW/MHz

Read Power d e f uW/MHz

Write Power g h i uW/MHz

Idle Power j k l uW/MHz

Min Nominal Max Unit

Leakage Current (ACTIVE) - n p uA

Leakage Current (Sleep) - q r uA

* Write Power is defined as Writing: 50% 1, 50% 0 * Read power is defined as Reading: 50% 1, 50% 0



• Silicon Characteristics vs Simulation Commercial, Medical, Military/ Aerospace

• Memory Compiler Deliverables• Datasheet Components• Testability/BIST/Reliability/ Routability/Margin

Control

191


Multicore SoCs :Many SRAMs, ROMs, OTPs, Register Files, and CAMs

Instruction Cache L1

CPU

LCDDriver

&Interface

SRAM

802.11nDSP

+RF

GPSDSP + RF

DSPAudio

VideoMemory(SRAM)

Data Encryption Engine

SRAM

BluetoothDSP

+RF

Data Cache L1

CAM

ROM

SRAM

ROM

SRAM


CPUData Cache L1

CAM

RegisterFiles

RegisterFiles

ROM

SRAM

SRAM


Data Cache L2USBRegister

Files

ROM

RegisterFiles

ROMOTP

RegisterFiles

Glue Logic

GlueLogic

Glue LogicR

eg

iste

r F

iles

OTP

On-ChipBUS Controller

&Arbitration Logic

GPU

ROM

Re

gis

ter

File

s

I/O



CPU

LCDDriver

&Interface

SRAM

802.11nDSP

+RF

GPSDSP + RF

DSPAudio

VideoMemory(SRAM)

Data Encryption Engine

SRAM

BluetoothDSP

+RF

Data Cache L1

CAM

ROM

SRAM

ROM

SRAM


Data Cache L1

CAM

RegisterFiles

RegisterFiles

ROM

SRAM

SRAM


Data Cache L2USBRegister

Files

ROM

RegisterFiles

ROMOTP

RegisterFiles

Glue Logic

GlueLogic

Glue LogicR

eg

iste

r F

iles

Re

gis

ter

File

s

OTP

GPU

On-ChipBUS Controller

&Arbitration Logic

CPU

ROM

I/O

Multicore SoCs :Many SRAMs, ROMs, OTPs, Register Files, and CAMs


Business Related Factors

194



• Flexible Business Model & Global Support• Multiple Memory IPs in Single SOC• Full Node vs Half Node Support

195


Flexible Licensing Business Model

• Full Use of Compiler Licensing Individual or combined memory engines Per-project or multi-year (Enterprise)

• Instance Based Licensing Per-project or multi-year (Enterprise)

• Flexible Royalty• Global Sales & Technical Support

196



• Flexible Business Model & Global Support• Multiple Memory IPs in Single SOC

Single Business Proposal

• Full Node vs Half Node Support

197



• Flexible Business Model & Global Support• Multiple Memory IPs in Single SOC• Full Node vs Half Node Support (New Bitcell)

Availability of IPs to meet schedule Availability of technology files Availability of Yield & Characterization data Optimum Wafer Price Viable Fab Capacity

Full nodes: 180nm, 130nm, 90nm, 65nm, 40nm

Half nodes: 160nm, 152nm, 110nm, 55nm

198


Summary

• Successful Execution in 3 Aspects of Design• Selecting the correct memory & Advanced Compiler

for SOC Maximized system performance Minimized system power consumption & leakage Minimized system manufacturing cost

• Selecting the right memory IP and the right architecture will help you differentiate your products

199


Thank You!www.Novelics.com

200

Confidential

Posedge Inc.Posedge Inc.

The Role of Sub-System IP In Wired/Wireless ApplicationsThe Role of Sub-System IP In Wired/Wireless Applications

Confidential

Trends in Semi Industry

• Chip companies moved from providing point solutions to SoCs supporting multiple features/markets

• In the last decade how the chips have evolved?– Pure Hardware providers, Software done by the

customers (system houses)– Today the chip providers provide complete solutions

202

Confidential

Trends in Chip Industry

203

SYSPCIe

nPHY

BM

QoS

Class

AnalogPHY

HOST

ACCL

Confidential

Trends in IP Industry

• Started with providing point solutions (standard interfaces, processor, etc.)– UART /EMAC/DDR IP

204

Global IP

Market in B$

Confidential

Trends in Sub-System IP Industry

• Growing need for IP Providers to scale up and provide complete subsystem solutions (Networking, Security, Graphics)

• IP providers need to understand from the system perspective to be able to provide high value add

205

Confidential

Trends in IP Industry

206

Global IP Market in M$Years – 2006 - 2012

Confidential

Trends in Sub-System IP

• IP provides high levels of differentiation– End Products to various markets / segments

• IP influences the way the end system operates– Internal Memory / DDR BW

• Performance is key– At System Level. IP Level is of less significance.

• Significant interaction with System Software– Need for IP players to scale up and provide much more

than just the RTL

207

Confidential

Trends in Sub-System IP Industry

• Smaller Silicon Geometries and FPGA technologies demand more functionality and completeness

• Early and very close interaction with the Customer

• RTL, Firmware, Software, Reference platforms• Working w/ Customer’s Customer for specs• Interoperating End-to-End IP• Software API and Architectural Tools

208

Confidential

Challenges in Specialized IP

• IP as a Design Service• Maintenance

– Configurability– Options / Trade-Offs at Evaluation Stage

• System Perspective– Porting to Processors– System Level Interoperability / Standards work

• IP Product Cycles are large– Like what ASICs used to be.

• Differentiation to various Customers209

Confidential

Case 1: Switching / Routing

210

• Multi-Gigabit Switching / Routing

• Applications – STB, Wireless, Residential G/W

• Best Area/Power – (4) + 3sqmm/Gbps!!!

• 32K Table Entries / Sessions

• QoS and Traffic Management

• Software / Firmware / Hardware IP

IP Core in ASICFPGA Platform

Confidential


211

QoS MGMTQoS MGMT BUFF MGMTBUFF MGMT ETHERNETETHERNET FLOW CNTRLFLOW CNTRL

DHCPDHCP

SNMPSNMP

TELNETTELNET

DHCPDHCP

HTTPHTTP

FTPFTP

IGMPIGMP

RIPRIP

SNTPSNTP

SSHSSH

SFTPSFTP

PINGPING

SIGNALLINGSIGNALLING

CUSTOM APPSCUSTOM APPS

UDPUDP

IPV4IPV4

TCPTCP

IPV6IPV6DRIVERSDRIVERS

ICMPICMP

FLOW SETUPFLOW SETUP

IPV6/4 RTNGIPV6/4 RTNG NATNAT FIREWALLFIREWALL STATSSTATS

L2 BDGL2 BDG PPPoEPPPoE VLAN VLAN POLICINGPOLICING

CUSTOM APPLICATIONS UN-MODIFIED STACK FUNCTIONS (APPS)

HOST FUNCTIONS

CLASSIFIER (PE) FUNCTIONS

HW LEVEL FUNCTIONS

Confidential


212

ARBITERSARBITERS

USB HOST USB DEV

USB HOST USB DEV

DATA CACHEDATA CACHE

HOST PROCESSORHOST PROCESSOR

PROGRAM CACHEPROGRAM CACHE

UART, SPI, GPT, GPIO, SYSTEM CTRL,

SERIAL FLASH

UART, SPI, GPT, GPIO, SYSTEM CTRL,

SERIAL FLASH

PCI EXPRESSSATA

PCI EXPRESSSATA

Video ProcessorVideo Processor

DDRDDR

ARBITERSARBITERS

ETHERNET LAN/WANETHERNET LAN/WAN



QOSQOS

CLASSIFIER PARALLEL PROCESSING UNIT

FILTERS

CLASSIFIER PARALLEL PROCESSING UNIT

FILTERS

BUFFER MANAGERBUFFER MANAGER

LOCAL MEMORYLOCAL MEMORY

WSP IP

Confidential


213

Confidential


214

• Remarks– Complete S/W, F/W, H/W IP Solution– Best Performance– Architecture Analysis Tools – System Trade-offs

Confidential

Case 2: MACSEC / IPSEC

215

FPGA PlatformIP Core in ASIC

• 10 Gbps short packet performance

• Tight Integration to PHYs and Switches

• Fixed and Lowest Latency

• Full solution with Flow Control and MACs

Confidential


216

Confidential


217

• 802.1X-REV & 802.1AE

• Classification

• Beyond Crypto Engine, Standards

• Secure PHY Applications

Confidential

• Remarks– Working with System Vendors– Interoperability– System Perspective in Classification et al.

• New Applications


218

Confidential

Posedge IP Cores

219

Multi-Port Routing Engine

USB-SATA Offload Engine

Multi-Gigabit Switching Core

Hardware TCP Offload Engine

Power Line Comm IC

2K FFT

Error Coding FEC, Viterbi

LDPC

IPSEC Security Engine

MACSEC 802.1 AE

Public Key, RAND. Number

IP Compression GZIP, Deflate

Universal Flash SD3.0/MMC

SOC-GEN(Bus Gen)

UART, SPI, GPT, GPDMA, I2C

AXI,AHB, APB, Bridge, Master, Slave, Arbiters

Confidential 220

Thank You

Confidential

Back Up Slides...

221

Confidential

Case 3: NV Memory Interface

222

Area• Cut-Thro Buffers• Clock Stopping / Read Wait• Modular Approach

Reference Board

SD Memory SD Memory ControllerController

SD Memory SD Memory ControllerController

SDSD NAND Flash NAND Flash ControllerController

NAND Flash NAND Flash ControllerController NANDNAND FlashFlashNANDNAND FlashFlash

Highest Performance• SD 3.0 – 104MB/sec• ONFI 2.2 – 200MT/sec• Hardware ECC• On-the fly ECC Correction• Ping-Pong Mechanism• Interleaving Operations• Scatter Gather DMA

Others• ECC – BCH (up to 32 bits)• Bad Block, Wear Level, Garbage

Collection• Simple Plug and Play Interface• Low Power• HW/SW Bundle for High

Performance

HW/SW Development Kit

Confidential

Case 3: NV Memory Interface

223

• Remarks– Performance at SoC Level– Software + Hardware bundled IP

Confidential

TCP Load Engines

224

IP Core in ASIC

FPGA Platform

• Multi-Gigabit TCP Offload• Best Area/Power/Latency!!!

– < 10 us one way– 150K gates

• Fully Future Proof with Firmware.• 4K-64K Sessions• Clean S/W Hand-offs

Confidential

Compression Engines

225

• Wireless Base Stations

• Storage Switches (Live)

• Back-Up Servers

COMP OUT

DATA IN10 Gbps

COMP INP

AHB/AXI

Data Parser Engine

Memory

Host StatisticsDebug

DATA Pack

Huffman Encoder for Distance

Huffman Encoder Tree, Literals/

length

DATA UPack

Huffman Table and

Decoder

10 Gbps DATA OUT

Memory

LZ77 Find

Data Inflate Engine

LZ77 Decode

FPGA Platform

• Multi-Gigabit Compression Engine

• Best Area/Power/Latency!!!

– < 0.5 us one way

– 120K gates

• Novel LZ77 Architecture

• IPCOMP

Confidential 226

Thank You

ConfidentialConfidential

Slide 227Slide 227

Technical Panel Discussion

Constellations 2010 Silicon Valley - Complete Slide Set

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