Conquering Tomorrow’s Test Challenges

KEYNOTE: CAPEX TO OPEX ECONOMICS WITHIN THE INTERNET OF THINGSMichael MurrayGeneral Manager, Industrial Sensing Division, Analog Devices

We are approaching an exciting time of autonomy, ubiquitous connectivity and deep learning about the people and the things within an environment. During this discussion, we will explore both the technological and economical boundaries and potential within the greater IoT market with a distinct focus on intelligent factories and the system within them. Throughout our 50 year history of supplying analog to digital converters and sensors that are the start of the digital thread within the IoT to the largest industrial and instrumentation customers, Analog Devices embarked on our own intelligent factory experiment in Limerick, Ireland. This experiment will be used as the vehicle to educate the audience on the successes, learnings and failures of our attempt to instrument our own brown field (operating) plant along with the key learnings from green field installations. Furthermore, we have learned a significant amount about the economic balance of the value of instrumenting certain equipment or instruments inside an operating factory and the return on investment which is required. This return on investment analysis has become largely focused in the areas of predicative maintenance and asset control within a factory as there is a balance to be struck between the cost of commissioning the system and the data aggregation and storage required to make the implementation useful. Lastly, this technology and investment analysis is forcing firms to adapt their business models away from their current capital pricing models to more unique and besopke operational expense sharing models which has become disruptive to many firms that sell capital intensive equipment.

October 17-18*, 2016Hilton Hotel, Portland, OR* Welcome reception on October 16, 6:00-8:00 PM

Cascade Microtech and FormFactor invite you to COMPASS, our annual users’ group conference. Attend COMPASS 2016 and learn best practices and new techniques to address today’s test and measurement challenges. COMPASS 2016 offers a great lineup of speakers – your industry peers will be sharing their perspectives on meeting the emerging test challenges with innovative and practical ideas.

Don't miss COMPASS 2016! Register today at compass.cascademicrotech.com

COMPASS 2016 will offer six track sessions focused on the following subject areas:

• High-power applications• Calibration• Production test• RF/mmW probing• Advanced test challenges• Optoelectronics/photonics

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General Sessions

TRACK A: CALIBRATION

Near and Far Field E and H in Sub-mmWave On-wafer ProbesRick CampbellProfessor, Portland State University

We are familiar with mechanical challenges of sub-mmWave on-wafer probes because structures are so small. Thinking electromagnetically, the basic problem is that wafer probe tips and calibration/test structures are so large. This presentation begins by thinking in wavelengths instead of microns, and introduces the ancient antenna theory concept of the radiansphere. The seven E and H field components in free space around a small current source fall off as inverse R, inverse R squared, and inverse R cubed. The radiansphere at Ro = l/2p represents a mathematical boundary between stored energy and radiating fields. Structures larger than a radiansphere make good antennas, while structures smaller than a radiansphere have large stored E and H field energy. Sub-mmW begin at 300 GHz, with radiansphere about 300 µm diameter. Thus we expect all seven E and H components to be roughly the same magnitude near a probe tip and test structure contact. Design of on-wafer probe technology requires understanding stored energy and radiating E and H fields. Sub-mmWave wafer probes at Cascade Microtech were designed using a custom engineered near-field E and H measurement system on scale model probes and test structures. Intuitions developed during near-field laboratory measurements remain useful. It is particularly enlightening to consider the impact of contact and test structure asymmetry on E and H fields near the probe tip, coupling to propagating waves not present during calibration, and coupling between probe tip evanescent E and H fields to features on the test structure. This presentation will review basic E and H theory and the radiansphere, present a few near-field measurements of E and H components around a scale model wafer probe tip, and discuss how to use what we have learned to improve accuracy and reliability of on-wafer sub-mmWave calibration and measurements.

A Method for On-wafer Calibration of Power and ImpedanceSuren SinghApplication/Product Marketing Engineer, Keysight Technologies

This paper will discuss a novel method of power calibration at the probe tip for an on-wafer active device measurement. In this paper we will review briefly the system architecture and the method for power calibration using the Keysight PNA / PNA-X millimeter-wave solution with Cascade Microtech’s WinCal XE™ software. We will present different methods used in the calibration for the power using a millimeter-wave solution and how we can extend this correction to the probe tip. Each of the methods will be described briefly with their limitations. In addition, we will present a method that accounts for the power at the probe while allowing users to take advantage of the WinCal XE routines designed for the millimeter-wave frequencies. In conclusion, we will step through the process steps and present data that will support out measurements.

Comparison of Calibration Processes with a Precise On-wafer Measurement System in NMIJRyo SakamakiResearch Scientist, National Institute of Advanced Industrial Science and Technology (AIST)

This report presents that different verification results have relevance to operational variation in calibration process. We have investigated transmission and reflection characteristics of calibration standards providing to difference of measurement results obtained by a precise on-wafer measurement system in National Institute of Advanced Industrial Science and Technology (AIST). In the verification process, Keysight Verification Substrate (KVS) was used as the verification devices. Especially, we focused on effects of highly reflected calibration standards, i.e. open and short circuits, to measurement results of KVS. For careful investigation on the issue, firstly, error analysis for a measurement system was conducted to elucidate the source of dominant error factor in the system. Based on the analysis results, a measurement reproducibility in the system was improved by measurement procedure. Finally, the calibration and verification processes were undertaken with a developed measurement system. The higher transmissions characteristics were observed in short standards than those in open standards. It indicates existence of interaction between two-port short devices. This interaction may cause different calibration results between short and open calibrations. In this study, two kinds of TRL calibrations were conducted with using short and open standard as reflect standards. In the presentation, we will review the comparison results of calibration methods in evaluation of verifications devices.

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FEATURED SESSION: TEST CHALLENGES FOR INTEGRATED OPTICSNoam OphirDesign Verification Testing Team Lead, Coriant Advanced Technology

Integrated optics, and in particular silicon photonics, poses unique test challenges. As the industry moves toward building large-scale integrated photonic devices, a very rapid evolution of the relevant test platforms is going to be required. Noam Ophir, Design Verification Testing Team Lead, Coriant Advanced Technology, will discuss challenges associated with driving down test costs and improving yields, along with an overview of the state of photonic and optoelectronic testing today.

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TRACK B: HIGH-POWER APPLICATION

High Voltage, High Current - and Some Like it Hot Too…Rainer Gaggl, Ph.D.Managing Director, T.I.P.S. Messtechnik

High-power devices production probing has been usually limited to room temperature measurements. Recent developments in power semiconductor technology and numerous activities in the field of Si, SiC and GaN based devices have driven the need for power tests at high temperature. Some aspects of gas discharge physics with special attention to effects at elevated temperature will be highlighted as well as probe card configurations that address these requirements will be presented.

Unique Approach to Characterizing Power Devices at 3 kV over TemperatureBryan RootPresident, Celadon Systems

The automotive industry is driving the need for high-power semiconductor devices. This push has resulted in numerous high- current and high-voltage applications in the industry. To keep pace with these applications the ability to test up to 3kV and over wide temperature range is critical to properly test and characterize these devices. This paper will discuss the successful implementation of a versatile system using the industry-standard Celadon 45e and VC20 probe card coupled with the Keithley 2657A Sourcemeter SMU instrument.

Advancing the Frontiers in Automatized On-wafer Testing of Power SemiconductorsMehrdad Baghaie YazdiManager, Power Solution Center, Fairchild Semiconductor

The rapid development of power semiconductors, such as IGBTs and power MOSFETs, has been challenging the limits of testing and probing device properties, as they reach ever faster switching speeds and higher current and electric field densities. Furthermore the utilization of novel materials such as SiC and GaN are enabling devices that can operate at temperatures well beyond the critical 175°C of Si and switching frequencies in the tens MHz. These new challenges require both test equipment and device physics know-how, to enable new probing capabilities for the next generation of devices. Here we present the joint efforts of Fairchild Semiconductor and Cascade Microtech to develop on wafer methods for three future challenges, namely automatized high-temperature electric testing, dynamic on-wafer testing and high power on-wafer testing.

TRACK C: RF/mmW PROBING

High-speed and Wideband On-wafer Load Pull for Model Extraction, Validation and DesignGary SimpsonChief Technical Officer, Maury Microwave

Load pull is an essential tool in the large-signal characterization of high-frequency devices, in that it can be used to determine the optimal loading conditions of the device under test (DUT) for common large-signal parameters (e.g. gain, output power, power added efficiency…). However, common passive and active load pull techniques are highly demanding in measurement time, especially when it is desired to monitor and control multiple parameters simultaneously (fundamental and harmonic terminations, multiple input power levels, multiple biases…). This is usually reflected in extremely long measurement times and slows-down the PA design/optimization process. In addition, consumer demand for streaming content, video conferencing and nonstop cellular usage has led to the development of complex modulation schemes with progressively higher operating bandwidths. The latest technologies utilize handsets and base stations requiring tens or hundreds of MHz of instantaneous bandwidth. This bandwidth requirement puts a heavy stress on the power amplifiers which lie at the heart of both handsets and base stations. Amplifier designers must take special care when designing matching networks, shifting their design from CW or two-tone device characterization to realistic mobile communications (such as LTE) device characterization. Amplifiers must be simultaneously optimized for Power, Efficiency, ACPR and EVM. In this paper, we will demonstrate a mixed-signal active load pull approach that reduces hours of measurements to just minutes in single-tone CW and pulsed-CW operation, and enables instantaneous wideband impedance control up to 240 MHz for modulated load pull operation.

Landing Pads for Measuring PCBs up to mm-Wave Frequencies using a Probe StationDr. Michael GadringerUniversity Assistant, Institute of Microwave and Photonic Engineering, Graz University of Technology

In this presentation we discuss the challenges imposed by measuring PCBs using commercially available mm-wave probes, like Cascade Microtech’s ACP probes. To accomplish high-quality measurements the transition between the probe tips and the test vehicles on the PCB must show a low loss and good matching over the desired frequency range. In the field of on-wafer probing the design of such transitions is a well investigated topic. However these results cannot be applied directly for PCB measurements due to the limitations introduced by the RF laminates and the corresponding manufacturing processes. To overcome these limitations a new

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landing pad design for measurements from DC up to 100 GHz was derived. Using EM filed simulation, the structure was investigated and optimized. The different versions of the landing pad was manufactured to verify the results from the simulations. Additionally the impact of the manufacturing tolerances on the performance of the landing pad were investigated. The conditions imposed by the PCB results in lower planarity and harder surface finish compared to on-wafer probing. Therefore, we examined the mm-wave probes over different measurement campaigns and monitored their performance.

Optimizing On-wafer THz and Differential Measurement Accuracy with High DirectivityJeffrey HeslerChief Technical Officer, Virginia Diodes

As frequency of test increases, losses in waveguide sections and on-wafer probes can become a significant issue for on-wafer RF test systems. In particular a reduction of system directivity affects overall on wafer system performance, calibration repeatability and crucially system drift. Having the probe tip closer to module output flange but still able to contact the device under test is thus a desirable attribute. Virginia Diodes Inc. (VDI) has had a line of state-of-the-art vector network analyzer extenders available up to 1.1 THz since 2011. Given the importance of on-wafer probing VDI has been working to optimize these extenders to make them more compact. This reduction in volume allows for a broader range of on-wafer solutions ultimately to achieve the above goals. A series of compact VNA extenders from WR-15 (50-75 GHz) through WR-2.2 (325-500 GHz) has been developed. The performance of the mini modules is the same as the standard modules, but the reduced size (about a quarter the volume of the standard modules) and allows for reduced distance between the extender and the wafer, and also allows optimization of 4-port or differential on-wafer measurements. In addition recent work to improve wafer probing above 500 GHz will be described. Finally, a recently developed 1.1-1.5 THz extender with measured dynamic range of 75 dB (typ.) will be described.

Investigation of Line Length Effects in Multiline TRL Calibrations at 1.1 THzMatt BauwensSenior Engineer, Dominion MicroProbes

Recently advances in the development of terahertz device technologies have created a need for on-wafer probes operating at terahertz frequencies. To address this need, the 1.1 THz T-Wave™ probe was developed and introduced. At such high operating frequencies, spurious effects such as radiation have an increased effect on calibration and measurement quality. This presentation presents an investigation of into the effect of line lengths in Multi-line TRL calibrations at 1.1 THz. measurement results will be presented and compared with electromagnetic simulation models. In addition, line length recommendations will be given.

TRACK D: PRODUCTION TEST

Production-level On-wafer Probe of Multi-channel 77 GHz Radar Transceiver ChipsetJeffrey FinderADAS Product and Test Engineering Manager, NXP Semiconductor

Radar-based active safety systems are in the automotive market today, enabling key applications such as emergency braking, adaptive cruise control, blind-spot monitoring, and cross-traffic alert. The industry is heavily invested in removing the challenges of integrating these functional applications into a cohesive system that will enable Autonomous Driving. Adoption is increasing with research estimating the market to grow to more than 50 million radar sensors in 2021, a 23 percent year-on-year increase from today. NXP’s MR2001 is a high-performance 77 GHz radar transceiver chipset that is scalable for multi-channel operation enabling a single radar platform with electronic beam steering and wide field-of-view to for long, mid-, and short-range radar applications. The market acceptance of the MR2001 chipset is driving innovation in production-level on-wafer probe methodologies and hardware. This paper will describe the challenges and results of production-level on-wafer probe of 77 GHz devices using the Cascade Microtech’s Pyramid-MW Probe Card and RFIC membrane core. Impact of membrane core properties, membrane wear, contact resistance and probe pad surface on measuring critical RF parameters over the frequency band of 76 to 77 GHz will be described.

Verification of High-bandwidth-Memory (HBM) through Direct Probing on MicroBumpsMichael HuebnerSr. Director of Product Marketing, FormFactor

High-Bandwidth-Memory (HBM) is a new type of memory that promises low power consumption, and ultra-wide communication lanes to improve system-level performance. HBM also leverage innovative 2.5D and 3D stacking technologies which brings in many new possibilities and challenges from test perspectives. This means different test flow and insertion points, different structures to probe on, test quality required to ensure “known-good-stack”. This presentation will address the electrical challenges and simulation results associated with direct on MicroBump probing of wide data busses at up to 1 GHz. We will also review how MicroBumps will respond to the probe card under various probing conditions such as current, test temperature and test durations.

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Production Millimeter-wave Test Cell for Automotive Radar SoCsDevin MorrisRF Applications Engineer, Roos Instruments

Millimeter-wave automotive radar has emerged as one of the preeminent sensor technologies of the early warning and avoidance features of the Advanced Driver Assistance System (ADAS). Market growth for ADAS sensors over the next five years points to growth of over 20% (CAAGR), with automotive radar constituting over 40 million units. To facilitate the growth of millimeter-wave radar as a standard automotive safety feature, ICs and System on Chip (SoC) transceiver architectures are being developed in standard CMOS processes to deliver integrated, low-cost, high-volume 77 GHz radar. Demonstrated is a production millimeter-wave test cell to address the rigorous testing demands of SoC automotive radar chipsets at wafer level. The test cell is comprised of a Cassini 16 ATE system configured with multi-port millimeter wave source/measure port capability and a Cascade Microtech CM300 Probe Station with millimeter-wave Pyramid Probe® card. The test cell configuration demonstrates the industry’s first high-density, blind mate waveguide tester/probe card interface using the RI designed RR12 Micro Flange to support high-performance measurement capability from 71-86 GHz.

Achieving Higher Speeds for CMOS Image Sensor TestingLarry LevySenior Director, Strategic Sales, FormFactor

As CMOS Image Sensors continue to grow at ~10% CAGR, a part of that market is driven by the need for speed. Back in 2014, FormFactor and Advantest first presented the challenges of the test infrastructure keeping pace with the device speeds. Since that time new requirements relating to the incorporation on lens modules in the probe card, have increased the difficulty of meeting this challenge. Last year, FormFactor produced several card designs requiring 2.5 Gbps for the differential pair and clock speeds as called out by MIPI D-PHY V1.2. However, new M-PHY opportunities require 3 Gbps speeds for several differential pairs. In cooperation with Hitachi Chemical Co.,Ltd, using new PCB materials and design rules, we were able to achieve loss characteristics of the probe card that was comparable to traditional high-speed CIS probe card performance without a lens module. An Eye pattern simulation that used actual S-parameter data indicated we finally have enough signal quality to meet 3 Gbps. However, as we look toward the future our next target of 5 Gbps may require some structural changes.

TRACK E: ADVANCED TESTING CHALLENGES

Advanced Measurement and Processing Capability within WinCal XE

Gavin FisherSenior Application Engineer, Center of Expertise, Cascade Microtech

Cascade Microtech has been a technology leader in the on-wafer probing industry since our incorporation in 1983. We introduced our first version of WinCal XE calibration software in 1995, and since then, we have been adding more algorithms and more functions. For many of our customers, Wincal XE is their daily workhorse used to calibrate the VNA and more. However this core function merely scratches the surface of the feature set of this tool. During this presentation I will review how some of the advanced tools may help users in ways they may have not anticipated. These include allowing full-wafer RF test including DC bias and sending key metric data back to the WaferMap using the inbuilt sequencing functionality with its simple programming language. This will be shown using video of actual test and also virtual interaction with our Velox prober control software. The location manager will be shown enabling test of user defined substrates. An overview will be given with a virtual example of using .net to control WinCal XE and also Microsoft Excel allowing WinCal XE tests to be integrated into an existing user test executive code. Finally a demonstration will be given of using WinCal XE to create detailed post-processing functions such as modifying the calibration method of an entire set of data after measurement to view ramifications of error term variation.

Applications and Measurement Considerations on Low-frequency Noise AnalysisRaj SodhiApplications Developer, Keysight Technologies

Electrical noise is inherent in every circuit, ranging from current flowing through a resistor or transistor, to leakage current through a tantalum capacitor. To minimize its effects, it becomes necessary to measure and quantify the noise of the constituent parts, and then connect the constituent noise contributions to overall circuit performance. In this paper, we will discuss the basics of noise spectral density, noise measurement applications, practical considerations in noise measurements, and how the Advanced Low-Frequency Noise Analyzer (A-LFNA) in combination with WaferPro Express measurement software addresses these challenges. We will also review best practices that may help to reduce the typical problems encountered when doing wafer-level measurements of low-frequency noise, such as minimizing the likelihood or effects of device oscillation, power line spurs and excessive environmental noise.

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Challenges in Package-Level Reliability (PLR) Testing for EM, SM and HCINg Hong SengGroup Manager, Reliability Testing, X-FAB Semiconductor Foundries

In the level1 process reliability testing, wafer-level reliability test (WLR) is typically a preferred method because of faster turn-around time, quick reliability assessment at production phase. It also eliminates the time-consuming step of dicing and packaging test structures and of course the cost. Nevertheless, for process qualification, the packaged level (PLR) tests are still unavoidable, which is because it provides more accurate lifetime extrapolation through higher sampling rate and longer stress time. This paper show the challenges encountered for PLR EM, SM and HCI, with the solution found and improvement planned. Both WLR and PLR methods on different via and metal line structures on AlCu (0.5%) scheme were studied. The experimental result showed single via-terminated EM structure lifetime was comparable between WLR and PLR methods based on Black’s equation; while stack via terminated structure and metal line structure lifetime showed difference between the two methods. PLR SM was studied using Cascade Microtech 1164 system as well. The resistance degradation behavior observed was different from the conventional WLR SM. The detail would be discussed further. The correlation between WLR and PLR was studied also for MOSFET devices with standard LV NMOS and MV LDMOS device. The PLR showed higher HCI degradation compared to WLR for MV LDMOS device, whereas comparable for LV NMOS. This was very low level of device self-heating effect on LDMOS from characteristic curves. However, the heat dissipation from ceramic packages took time compared to large silicon wafer on probe chuck. The stress-induced heating impact on LDMOS is discussed in this paper.

TRACK F: OPTOELECTRONICS/PHOTONICS

An Approach to Wafer-level Characterization of a Planar Opto-electronic BiCMOS TechnologyMarcel KrohScientist, Technology/Si Photonics, IHP

To date optoelectronic components are manufactured based on a broad choice of materials. Among those materials silicon has gained particular interest due to the potential of monolithic integration of optics and high-speed electronics. In the talk a planar optoelectronic BiCMOS integration technology based on Silicon-on-Insulator will be presented including a brief description of its possibilities. Of key importance is the availability of a test- and measurement environment for a set of new parameters and test cases. Beginning with general requirements for such wafer characterization and monitoring the fundamental test cases are described. Furthermore, examples for the on-wafer investigation of optoelectronic devices will be presented reflecting the broad application space of this technology. Constrains and decision points for the set-up and operation of an optoelectronic wafer prober will be identified. We shall conclude with a summary of open questions that either could be served by new standards and products of manufacturers but rather still require individual solutions for each test lab.

Out of the Lab and into the Fab: Optical Probing as an Enabler for Silicon Photonics’ Next ChapterScott JordanSr. Director, NanoAutomation Technologies, Physik Instrumente (PI)

Silicon photonics technologies are approaching critical implementation phases for volume production. This poses significant fresh challenges for testing in the engineering and developmental stage and in planning for repetitive manufacturing. A key impediment has been the need for nanoscale-accurate physical alignment of optical fibers and devices in test and packaging processes. Alignment has a profound effect on optical throughput, and optical probes unlike electrical probes cannot be sufficiently aligned via passive approaches or using visual or fiducial referencing. Alignment must be active and for many tests must be capable of tracking device drift due to thermal and other disturbances. Prior approaches to this challenge have not been suitable for the multiple inputs and outputs commonly encountered in today’s SiP devices, nor was their speed sufficient for these applications. Now a novel, multichannel-capable active alignment solution has been integrated into wafer probers optimized for developmental and engineering test and measurement. These systems perform global optimization across the inputs and outputs of even the most complex SiP devices in one rapid step, facilitating functional and parametric testing with high throughput.

Silicon Photonics Market Trends and Cascade Microtech’s RoadmapDan Rishavy Director of Market Development, Cascade Microtech

The transition from photonic devices being manufactured in exotic semiconductor processes into standard silicon technologies is underway. This talk will take a look how the consumption of data is driving this transition and why this creates the need for wafer-level probing capability. There is significant work to be done in process development, model extraction and design/debug, where measuring test structures and photonic components at the wafer level is critical. An integrated solution that includes high accuracy automated fiber positioning coupled with a high rigidity and vibration isolating probe station ensures the fastest time to measurement. We will explore Cascade Microtech’s current and future endeavors on developing a standardized test methodology to lower the cost of test for wafer-level photonic measurements.

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Program At A Glance (As of September 2016)

COMPASS 2016 SPONSORS

SUNDAY, OCTOBER 1618:00 Welcome Reception

MONDAY, OCTOBER 178:00 Registration and Networking Breakfast

8:30 Welcome and Opening

9:00 Keynote: Capex to Opex Economics within the Internet of Things (Analog Devices)

TRACK A: CALIBRATION TRACK B: POWER

10:15 Near and Far Field E and H in Sub-mm-Wave On-wafer Probes (Portland State University) High Voltage, High Current - and Some Like it Hot Too… (T.I.P.S)

10:55 A Method for On-wafer Calibration of Power and Impedance (Keysight Technologies)

Unique Approach to Characterizing Power Devices at 3 kV Over Temperature (Celadon Systems)

11:35 Comparison of Calibration Processes with a Precise On-wafer Measurement System in NMIJ (AIST)

Advancing the Frontiers in Automatized On-wafer Testing of Power Semiconductors (Fairchild Semiconductor)

12:10 "Birds of a Feather“ Roundtable Lunch

TRACK C: RF/mmW PROBING TRACK D: PRODUCTION TEST

13:10 High-speed and Wideband On-wafer Load Pull for Model Extraction, Validation and Design (Maury Microwave)

Production-level On-wafer Probe of Multi-channel 77 GHz Radar Transceiver Chipset (NXP Semiconductors)

13:50 Optimize PCB Pad Design for mmW Measurements (Graz University of Technology)

Verification of High-Bandwidth-Memory (HBM) through Direct Probing on MicroBumps (FormFactor)

14:30 Optimizing On-wafer THz and Differential Measurement Accuracy with High Directivity (Virginia Diodes)

Production Millimeter-Wave Test Cell for Automotive Radar SoCs (Roos Instruments)

15:10 Investigation of Line Length Effects in Multiline TRL Calibrations at 1.1 THz (Dominion MicroProbes)

Achieving Higher Speeds for CMOS Image Sensor Testing (FormFactor)

16:00 CEO Insights from the Edge: What’s on the Horizon for FormFactor/Cascade Microtech? (Mike Slessor, President and CEO, FormFactor)

17:00 Off-site Event Followed by Networking Dinner

TUESDAY, OCTOBER 188:00 Networking Breakfast

8:30 Day 2 Agenda Preview

8:40 Featured Session: Test Challenges for Integrated Optics (Coriant)

TRACK E: ADVANCED TESTING CHALLENGES TRACK F: OPTOELECTRONCIS/PHOTONICS

10:00 Advanced Measurement and Processing Capability within WinCal XE (Cascade Microtech)

An Approach to Wafer-level Characterization of a Planar Opto-electronic BiCMOS Technology (IHP)

10:40 Applications and Measurement Considerations on Low-frequency Noise Analysis (Keysight Technologies)

Out of the Lab and into the Fab: Optical Probing as an Enabler for Silicon Photonics’ Next Chapter (Physik Instrumente)

11:20 Challenges in PLR Testing for EM, SM and HCI (X-FAB Semiconductor)

Silicon Photonics Market Trends and Cascade Microtech’s Roadmap (Cascade Microtech)

13:30

Interactive Equipment Demo at Cascade Microtech Office (Beaverton)

• 2-port measurement and calibration at 110 GHz• Automated multi-site wafer-level reliability test • Automated small-pad probing down to 30 µm with accurate PTPA

• Silicon photonics probing• Parametric probe card for automotive radar and SoCs

16:30 Happy Hour (Downtown)