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Application ReportSPRA968 - November 2003

1

Connecting TFT LCD Displays to the OMAP5910Gerald Coley DSPIEEE Catalog OMAP Applications

ABSTRACT

The OMAP5910 contains an integrated LCD controller. Utilizing internal memory anddedicated DMA channels, this architecture contains a very efficient LCD control interface.This appnote describes how to connect two different LCD displays to the OMAP5910. Whilethere are many sizes and types of LCD displays in the industry, this appnote focuses on two240 × 320 color thin film transistor (TFT) displays and how they interface to the OMAP5910processor.

Contents

1 OMAP5910 LCD Controller 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 LCD Interface Signals 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 NEC 240 y 320 QVGA Display 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Display Description 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 LCD Display 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Timing Controller 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 LCD Control Signals 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 OMAP5910 Interface 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 LCD Power 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Touchscreen 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 LCD Panel Front Light 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Sharp 240 y 320 Display 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Display Description 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 Timing Controller 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Control Signals 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 OMAP5910 Interface 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 LCD Panel Power 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 LED Frontlight Interface 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Touchscreen 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Summary 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 References 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A NEC Display Schematics 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix B Sharp Display Schematics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Trademarks are the property of their respective owners.

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2 Connecting TFT LCD Displays to the OMAP5910

List of Figures

Figure 1. OMAP5910 LCD Control Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2. NEC LCD Timing Controller 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. NEC LCD Power 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. NEC LCD Power 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5. NEC LCD LED Frontlight Power 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. Sharp LCD Timing Controller 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7. Sharp Power Supply 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 8. Sharp LCD Frontlight Controller 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table 1. LCD Interface Signals 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2. NEC LCD Specifications 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3. LCD Control Signals 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4. LCD Control Signals Connections 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5. LCD Control Signals Connections 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6. Sharp LCD Control Signals 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7. Sharp LCD OMA5910 Interface 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 OMAP5910 LCD Controller

This section provides a high-level description of the LCD controller as it pertains to the TFTmode of operation that is being used in this appnote.

1.1 Features

The following features are provided by the OMAP5910 LCD controller:

• Mono passive: 1 BPP, 2 BPP, 4 BPP, and 8 BPP

− 1 BPP: Two palette entries selecting one of 15 grayscale

− 2 BPP: Four palette entries selecting one of 15 grayscale

− 4 BPP: 16 palette entries selecting one of 15 grayscale

− 8 BPP: 256 palette entries selecting one of 15 grayscale

• Color passive: 2 BPP, 4 BPP, 8 BPP, 12, and 16 BPP

− 2 BPP: Four palette entries from 3375 possible colors

− 4 BPP: 16 palette entries from 3375 possible colors

− 8 BPP: 256 palette entries from 3375 possible colors

− 12 BPP: 3375 possible on-screen colors

− 16 BPP: 3375 possible on-screen colors

• Active: 2 BPP, 4BPP, 8BPP, 12 BPP, and 16BPP

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− 2 BPP: Four palette entries selecting from 4096 colors

− 4 BPP: 16 palette entries selecting from 4096 colors

− 8 BPP: 256 palette entries selecting from 4096 colors

− 12 BPP: Maximum 64K colors

− 16 BPP: Maximum 64K colors, depending on LCD panel

The TFT is the most commonly used display for hand-held type devices and offers the bestoverall quality in terms of color depth, clarity, and overall brightness.

The other modes listed above are not covered in this application note.

1.2 Block Diagram

Figure 1 shows the block diagram of the LCD controller on the OMAP5910.

Gray−scaler/serializer

PaletteRAM

OutputFIFO

MUX

12/16 bpp STN

16−bit TFT

LCD.P[15:0]

ControlLCD panel

timingsgenerator

Registers

LCD controller

LCD.PCLK

LCD.VS

LCD.HS

LCD.AC

Framebuffer

MPU privateperipheral bus

LCD_CK(from clock and

reset managementblock) DMA request

LCD interrupt (level 1 IRQ_31)

Figure 1. OMAP5910 LCD Control Block Diagram

In the TFT mode, the palette RAM, gray-scalar, and output FIFO are not used. The data is sentdirectly to the LCD display via the DMA controller from the internal frame buffer memory.

For more detailed information on the internal workings of the OMAP5910 LCD controller, refer tothe OMAP5910 datasheet or Technical Reference Manual.

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1.3 LCD Interface Signals

Table 1 defines the primary pins used by the OMAP5910 to control an external TFT LCD panel.

Table 1. LCD Interface Signals

NAME TYPE DESCRIPTION

LCD.P[15:0] OUT Pins used to transfer sixteen bit data values at a time to the LCD display.

LCD.PCLKOUT

Pixel clock used by the LCD display to clock the pixel data into the line shift register. Thepixel clock transitions continuously and the ac-bias pin is used as an output enable to signalwhen data is available on the LCD pins.

LCD.HS OUT Line clock used by the TFT displays as the horizontal synchronization signal.

LCD.VS OUT Frame clock used by the LCD displays to signal the start of a new frame of pixels. Used byTFT displays as the vertical synchronization signal.

LCD.AC OUT Used in TFT mode as the output enable to signal when data is latched from the data pinsusing the pixel clock.

Additional signals may be required from the OMAP5910. These signals are typically GPIO pinsand are used to control such things as:

• LCD power on/off

• Backlight on/off

• Brightness control

Depending on the system level design, several pins are available for these and similar functions.The designer of the board is free to choose if and how these functions are controlled by theOMAP5910 processor.

2 NEC 240 � 320 QVGA Display

The first display that we will discuss is the NEC NL2432DR22-11B LCD display. The features ofthis display include:

• 3.5” (8.9cm) diagonal

• 240 x 320 Resolution (QVGA)

• Reflective

• Portrait Mode

The remainder of this section describes how to interconnect the NEC LCD display and theOMAP5910.

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2.1 Display Description

The NEC display is actually comprised of two components:

• NL2432DR22-11B LCD display

• The S1L50282F23k100 timing controller

2.1.1 LCD Display

Table 2 lists the specifications of the NEC LCD.

Table 2. NEC LCD Specifications

Parameter Specification Units

Screen Diagonal 3.52”(8.9) in(cm)

Display Area 2.11(53.64)H × 2.82 (71.53)V in(mm)

Pixel Format 240 × 320

Colors 262,144

Pixel Configuration R,G,B Vertical Stripe

Outline Dimensions 2.56(65)W × 3.35(85)H × 18(4.5)D in(mm)

2.1.2 Timing Controller

The OMAP5910 actually connects to the S1L50282F23k100 timing controller provided by NEC.The timing controller converts the 16-bit LCD data into the row and column scan data to drivethe LCD panel itself. In some cases, the timing controller is integrated with the LCD panel. Thisis especially true of the larger size displays. However, in this case, the timing controller isseparate from the LCD panel. Figure 2 shows the pinout of the timing controller.

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U10S1L50282F23k100 31 21 14 1

26 24 20 747 38 286074 61 54 41

68 6480

565758596263

495051525355

4344454648

42

34

39

35

37

32

3633

65

67

66

232219181716

1513121110

9

865432

40

757671777372707969

25

27

302978

VD

DV

DD

VD

DV

DD

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DV

DD

VD

DV

DD

VD

D

GN

DG

ND

GN

D

RO0RO1RO2RO3RO4RO5

GO0GO1GO2GO3GO4GO5

BO1BO2BO3BO4BO5

BO0

INV

HCK

DLP

HSP

PC

INHHOE

VCK

VSP

VOE

RA10RA11RA12RA13RA14RA15

GA10GA11GA12GA13GA14GA15

BA10BA11BA12BA13BA14BA15

GN

D

INVSEHDRESPCIPCSEPANS0PANS1DSECKSHOEPW

DCK

DE

POCOENTSTEN

Figure 2. NEC LCD Timing Controller

The individual signals are discussed in the following sections.

2.2 LCD Control Signals

Table 3 describes the functions of the control signals on the S1L50282F23k100 timing controllerthat connects to the OMAP5910 LCD interface. The LCD side of the controller is not covered.Refer to the schematic in Appendix A for more details.

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Table 3. LCD Control Signals

Number Name I/O Freq Description

6,8,5−2 BI0-5 I 7.5 MHZ Input data for the color blue.

15,13−9 GI0-5 I 7.5 MHZ Input data for the color green.

23,22,19−16 RI0-5 I 7.5 MHZ Input data for the color red.

25 DCK I 15 MHZ Dot clock

27 DE I 18.75 KHZ Data enable

29 OEN I DC Gate driver output enable pin

30 POC I DC Power on clear

75 INVSE I DC Output data reverse (0:off,1:on)

76 HDRES DC Data reverse of Internal PC (0:off,1:on)

71 PCI I DC Polarity inversion (0:line reverse,1:frame reverse)

77 PCSE I DC PC switching (0:internal PC,1:Internal PC reverse)

73 PANS0 I DC Switching resolution setup 0

72 PANS1 I DC Switching resolution setup 1

70 DSE I DC Source driver switching

79 CKS I DC DCK reverse (0:no-reverse, 1:reversed)

69 HOEPW I DC HOE Pulse width selection.

78 TSTEN I DC Test terminal (0:non-reversed’1=reversed.

NOTE: Not all of these signals are controlled by the OMAP5910 processor.

2.3 OMAP5910 Interface

This section describes the interconnection of the LCD and timing controller into the OMAP5910processor. Table 4 maps the LCD controller pins to the OMAP595910. In addition, those signalsthat do not connect to the OMAP5910, but need to be terminated, are also covered.

Table 4. LCD Control Signals Connections

CONTROLLER SIGNAL OMAP5910 SIGNAL CONTROLLER SIGNAL OMAP5910 SIGNAL

BI0 LCD.P4 DCK LCD.PCLK

BI1 LCD.P0 DE LCD.AC

BI2 LCD.P1 OEN HIGH

BI3 LCD.P2 POC HIGH via RC

BI4 LCD.P3 INVSE Ground

BI5 LCD.P4 HDRES Open

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Table 4. LCD Control Signals Connections (Continued)

CONTROLLER SIGNAL OMAP5910 SIGNALCONTROLLER SIGNALOMAP5910 SIGNAL

GI0 LCD.P5 PCI Ground

GI1 LCD.P6 PCSE Open

GI2 LCD.P7 PANS0 High

GI3 LCD.P8 PANS1 High

GI4 LCD.P9 DSE Ground

GI5 LCD.P10 CKS Open

RI0 LCD.P15 HOEPW Ground

RI1 LCD.P11 TSTEN Ground

RI2 LCD.P10

RI3 LCD.P9

RI4 LCD.P8

RI5 LCD.P7

If you will note, BI0 and BI5 are connected to the same signal from the OMAP processor. This isbecause the timing controller is designed for 18-bit data, or R6:G6:B6, whereas OMAP5910supports 16-bit data, or R5:G6:B5. Tying these two signals together, BI0, being the leastsignificant bit, is an easy way of performing the conversion not only for the red component, butfor the blue component as well. Green on the other hand, uses all available bits which results ina 5:6:5 configuration for the data.

What is unique about the NEC timing controller is that it does not require the vertical orhorizontal sync data; only the pixel clock and the DE signal.

Refer to Appendix A for the complete schematic.

2.3.1 LCD Power

Figure 3 illustratess the design of the LCD power for the NEC display. The power does notnecessarily need to be designed in this manner, only the required power must be provided.

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F1DK/F1261CT−ND

5V_LCDVCC

5V_LCDVCC−1

5V_LCDVCC

D6DK/SS12G1CT−ND

+

C800 10.0UF 25V_(D)

LCDVCC_−15V

+ C5010.0UF

U13TPS79301DBV

123

654

INGNDEN

OUTFB

BYPASS

U34MAX633

17 8

4 5

263

LBIVFB COMP

LX VOUT

LBOCPGND

LCDVCC_−15V−3

LCDVCC_−15V−2

R15743.6K

+

C674.7uF

DO−214AC(SMA)

C700.01UF

LCDVCC_+15V−1

C690.1UF

+ C63

22uF_25V_(D)

C510.1uF

3V_LCDVCC

L7

10uH DK PCD1345CT−ND

LCDVCC_+15V

LCDVCC_−15V−1

+

C56

2.2UF 25V_(D)

D60DK/SS12G1CT−ND

3V_LCDVCC−1

C6615pf

C680.1UF

R15830.1K

Figure 3. NEC LCD Power

The NEC display requires a + 15 V and a −15 V supply to power the LCD panel. The logicsignals in the LCD panel are all at 3 VDC. In this design, all of the power is generated based ona 5 VDC supply. In the event the supply is different, Up converters can be used to create therequired voltages.

Pin 2 on the LCD connector (refer to Appendix A) is the contrast control for the LCD panel. Apotentiometer is used to adjust the voltage based on a 5v voltage source as needed.

2.3.2 Touchscreen

In addition to the LCD panel, the NEC display also has an integrated touch panel over thedisplay. This touch panel provides the ability to connect to a 4-wire touchscreen controller inorder to decode the x and Y coordinates and pressure on the display where a stylus is beingused. Any 4-wire touchscreen controller decodes this information. A good device is the TIADS7486 as depicted in Figure 4.

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C111

1000pF

C109

1000pF

TS_STATUS

R17910K

Y+

R18110K

VCC_I/O

+

C1071UF

I2S_DATA_OUT

U24SN74LVCH244APW

2468

1

18161412

11131517

9753

192010

A1A2A3A4

1OE

Y1Y2Y3Y4

A5A6A7A8

Y5Y6Y7Y8

2OEVCCGND

TS_CS

DOUT

J3

MOLEX 52207−0490

1 2 3 4

Y−

C112

1000pF

I2S_DATA_IN

DCLK

CAM_OPTSENS

TS_INT

BUSY

C110

1000pF

DINX−

TCS# C1080.1UF

C1130.1UF

I2S_CLK

ADS7846EU25

12345678 9

10111213141516

+VccX+Y+X−Y−GNDVbatIN Vref

+VccIRQ

DOUTBUSY

DINCS

DCLK

IRQ

X+

VCC_MAIN

Figure 4. NEC LCD Power

2.3.3 LCD Panel Front Light

The NEC display has an LED light source configured as a frontlight and integrated into the NECpanel. Figure 4 shows the frontlight power configuration. The LEDs require 7.9 V. In this case,however, a 15 V supply was used because it already existed for the LCD panel. The designermay choose to generate the required power differently.

GND

LCDVCC_+15V

7.9vmax

J400

04FLH−SM1−TB/J.S.T

1234

V2

V1

D400DK/MA8075CT−ND

R400392

Figure 5. NEC LCD LED Frontlight Power

3 Sharp 240 � 320 Display

This section describes connecting a Sharp LQ035Q7D color TFT display to the OMAP5910. Theschematic for this implementation can be found in Appendix B.

3.1 Display Description

The LQ035Q7D LCD display is a color reflective module based on TFT technology. It has anLCD panel, Driver ICs, back light, touch panel, and a back sealed casing.

The specifications of this display are included Table 5.

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Table 5. LCD Control Signals Connections

Parameter Specification Units

Screen diagonal 3.52”(8.9) in(cm)

Display area 2.11(53.64)H × 2.82 (71.53) V in(mm)

Pixel format 240 × 320

Colors 262,144

Pixel configuration R,G,B Vertical stripe

Outline dimensions 2.56(65)W × 3.35(85)H ×.18(4.5)D in(mm)

3.1.1 Timing Controller

The Sharp LCD also has a separate timing controller chip called the LZ9FC22. This chipconverts the 16bi RGB digital data into the row and column driver information to drive the LCDpanel. Figure 6 contains the pinout of the LCD timing controller.

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LZ9FC22

1267172

345678

111213141516

181920212223

25

66

6910274563

9 28 38 46 53 60 64

656261373635343332

444342414039525150494847595857565554

2

1724

70

6867

29

3031

DCLKENABHSYNCVSYNC

R0R1R2R3R4R5

G0G1G2G3G4G5

B0B1B2B3B4B5

HRVE

VRVE

TV/MODVDD0VDD1VDD2VDD3

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

UBRSPSCLSCLK

LPSPLLBRSPR

PS

DR0DR1DR2DR3DR4DR5DG0DG1DG2DG3DG4DG5DB0DB1DB2DB3DB4DB5

TEST0

TEST1TEST2

TEST4

NC1/SIZECONC0/TEST

RESET

REVREVV0

Figure 6. Sharp LCD Timing Controller

3.2 Control Signals

Table 6 defines the signals on the LCD timing controller that are used to connect to theOMAP5910 processor.

Table 6. Sharp LCD Control Signals

No. Name I/O Description

1 DCLK I Input terminal for data clock signal

2 SETR I Input terminal for control signal for PS (SIZEC0 = ”L” to the application)

3−8 R0-5 I Input data for the color red

11−16 G0-5 I Input data for the color green

18−23 B0-5 I Input data for the color blue

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Table 6. Sharp LCD Control Signals (Continued)

No. DescriptionI/OName

25 HREV I Input terminal for setting up right/left reverse scanningH level : Normal L level : Reverse scanning

26 ENAB I Input terminal for signal to settle the horizontal display position

66 VREV I Input terminal for setting up up/down reverse scannning(H:Normal L:Reverse scanning)

68 SIZECO I Input signal for drive condition changeSIZEC0 =H : Portrait QVGA(240RGB × 320)L : Landscape QVGA(320RGB × 240)

70 REM I Input terminal for reset signal

71 HS I Input terminal for horizontal sync. signal

72 VS I Input terminal for vertical sync. Signal

3.3 OMAP5910 Interface

Table 7 defines the mapping between the Sharp LCD timing controller chip and the OMAP5910processor LCD interface. It also shows the state of the pins that are not controlled directly by theOMAP5910 processor.

Table 7. Sharp LCD OMA5910 Interface

CONTROLLER SIGNAL OMAP5910 SIGNAL CONTROLLER SIGNAL OMAP5910 SIGNAL

B0 LCD.P4 DCK LCD.PCLK

B1 LCD.P0 DE LCD.AC

B2 LCD.P1 OEN HIGH

B3 LCD.P2 POC HIGH via RC

B4 LCD.P3 INVSE Ground

B5 LCD.P4 HDRES Open

G0 LCD.P5 PCI Ground

G1 LCD.P6 PCSE Open

G2 LCD.P7 PANS0 High

G3 LCD.P8 PANS1 High

G4 LCD.P9 DSE Ground

G5 LCD.P10 CKS Open

R0 LCD.P15 HOEPW Ground

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Table 7. Sharp LCD OMA5910 Interface (Continued)

CONTROLLER SIGNAL OMAP5910 SIGNALCONTROLLER SIGNALOMAP5910 SIGNAL

R1 LCD.P11 TSTEN Ground

R2 LCD.P12

R3 LCD.P13

R4 LCD.P14

R5 LCD.P15

3.4 LCD Panel Power

Figure 7 shows a possible design for the LCD power. The LCD requires a +15 V supply for theLCD panel itself. The logic section of the LCD requires a 3.3 V supply. The designer may choosea different way to supply the power to the LCD.

F1DK/F1261CT−ND

R15753.6K

LCDVCC_+15V

3V_LCDVCC−1

L710uH DK PCD1345CT−ND

U34MAX633

17 8

4 5

263

LBIVFB COMP

LX VOUT

LBOCPGND

5V_LCDVCC

5V_LCDVCC−1 LCDVCC_+15V−1

5V_LCDVCC

C690.1UF

C700.01UF

R15830.1K

+

C674.7uF

C680.1UF

DO−214AC(SMA)

U13TPS79301DBV

123

654

INGNDEN

OUTFB

BYPASS

3.3V_LCDVCC

+C5010.0UF

C6615pf

+ C63

22uF_25V_(D)

C510.1uF

Figure 7. Sharp Power Supply

Both of these circuits use a 5 V source to create the required voltages. The fuse is not requiredand is a part of this design, only as a precautionary measure.

SPRA968


3.5 LED Frontlight Interface

Figure 8 is the schematic for the control interface for the LED frontlight of the Sharp display.

J14

CONN MOLEX 54548−0590

12345

R382

D1

DK/10MQ040N−ND

R20 SOT−23 PACKAGE

5V

+ C1

4.7UF TANT 35V

+ C24.7UF TANT 35V

24V @ 15MA

L1

10UH

EN

U1

TPS61040DBV

5

4

1

3

2

Vin

EN

SW

FB

GND

R11K DNI

DO NOT INSTALL IFR2 IS INSTALLED

C PACKAGE

LED CONNECTOR

Figure 8. Sharp LCD Frontlight Controller

The power for the LED is supplied by U1, a 400-ma boost converter, which converts the 5 Vinput to the 24 V required by the LEDs. This design actually accepts and inputs a voltage rangefrom 1.8 V to 6 V. So, depending on the individual designs, there is some flexibility here. Refer tothe TPS61040 datasheet for more details.

The EN signal can be any GPIO pin on the OMAP5910. When it is Hi, U1 is active. As an option,R1 can be installed if the user wants the LCD to be on all the time.

3.6 Touchscreen

The requirements for the Touchscreen panel on the Sharp LCD are the same as found on theNEC Touchscreen interface.

4 Summary

The NEC LCD design was verified and produced in the form of the Innovator Development Kit.The NEC design was used in the production units of the Innovator platform and is still beingused.

A printed circuit board design was made, and 10 units were assembled and tested for the Sharpdesign. It was never produced in large quantities. It was intended as a backup in case the NECdisplays could not be obtained.

SPRA968


5 References1. OMAP1510 Dual-Core Processor Data Manual (literature number SPRS197)

2. OMAP1510 Dual-Core Processor Technical Reference Manual (literature numberSPRU602)

3. Sharp LCD Panel Datasheet LQ035Q7 B02 (LCY-02024, March 14, 2002)

4. NEC LCD Panel Datasheet NL2432DR22-11B (8th Edition, March 4, 2002)

5. Sharp Control IC for TFT-LCD Module LZ9FC22 (LCY-00136, June 26, 2001)

6. NEC LCD Controller S1L50282F23k100 (DOD-N-0192, 3rd Edition)

SPRA968


Appendix A NEC Display Schematics

R70 200

C460.1UF

G4

LCD_B_P6

R3

5V_LCDVCC

DATA ENABLE 18.75KHZ

R78 200

R85 200

R67 200

C430.1UF

LCD_B_P12

G1

LCD_B_PCLK

G0

C42150pF

15MHZ

LCD_B_P0

R64 200

R47 200

C450.1UF

B4

OUTPUT ENABLE

VCKR88 200

R45 200

R66 200

LCDVCC_+15V

R54 200

R91 200

LCD_B_P7

R76 200

R61 200

R83 200

R87 200

5V_LCDVCC

VCOMLCD_B_P13

R55 100

R42 200

C390.1UF

HCK

R2

R92 200

R53 200

TP61

J4JAE/IL−FMR−F455−−HF

123456789101112131415161718192021222324252627282930313233343536373839404142434445

R72 200

R48 200

R41 200

R58 200

C440.1UF

COM

R82 200

3V_LCDVCC

LCD_B_P1

R57 200

LCD_B_P[0..15]

R63 200

R90 100K

R5

C400.1UF

R43 200

R50 200

R62 200

R49 200

R69 200

R56 200

R75 200

R89 200

C380.1UF

3V_LCDVCC

LCD_B_P14

VSP

3V_LCDVCC

LCD_B_P8

B3

G3

R52 200

R60 200

R44 200

R68 200

LCD_B_P2

U10S1L50282F23k100 31 21 14 1

26 24 20 747 38 286074 61 54 41

68 6480

565758596263

495051525355

4344454648

42

34

39

35

37

32

3633

65

67

66

232219181716

15131211109

865432

40

757671777372707969

25

27

302978

VD

DV

DD

VD

DV

DD

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

DV

DD

VD

DV

DD

VD

D

GN

DG

ND

GN

D

RO0RO1RO2RO3RO4RO5

GO0GO1GO2GO3GO4GO5

BO1BO2BO3BO4BO5

BO0

INV

HCK

DLP

HSP

PC

INHHOE

VCK

VSP

VOE

RA10RA11RA12RA13RA14RA15

GA10GA11GA12GA13GA14GA15

BA10BA11BA12BA13BA14BA15

GN

D

INVSEHDRESPCIPCSEPANS0PANS1DSECKSHOEPW

DCK

DE

POCOENTSTEN

HSP

R1

VGON

DLP−STB

LCDVCC_−15V

LCD_B_P15

LCD_B_AC

B1

AP

R0

R4

LCD_B_P3

INV

R51 200

R73 200

+C414.7UF

LCD_B_P9

B5

VOE

R80 200

R36120K

R65 200

R86 200

R46 200

TP51

VGOFF

LCD_B_P11

3V_LCDVCC

LCD_B_P5

B2

POL

G2

R37VAR 100K P5C104CT−ND

B0

LCD_B_P4

G5

PIXEL CLK

LCD_B_P10

TP71

R59 200

POWER ON CLEAR

SPRA968


GND

LCDVCC_+15V

7.9vmax

J400

04FLH−SM1−TB/J.S.T

1234V

2

V1

D400DK/MA8075CT−ND

R400392

C1111000pF

C1091000pF

TS_STATUS

R17910K

Y+

R18110K

VCC_I/O

+C1071UF

I2S_DATA_OUT

U24SN74LVCH244APW

2468

1

18161412

11131517

9753

192010

A1A2A3A4

1OE

Y1Y2Y3Y4

A5A6A7A8

Y5Y6Y7Y8

2OEVCCGND

TS_CS

DOUT

J3 MOLEX 52207−0490

1 2 3 4

Y−

C1121000pF

I2S_DATA_IN

DCLK

CAM_OPTSENS

TS_INT

BUSY

C1101000pF

DINX−

TCS# C1080.1UF

C1130.1UF

I2S_CLK

ADS7846EU25

12345678 9

10111213141516

+VccX+Y+X−Y−GNDVbatIN Vref

+VccIRQ

DOUTBUSY

DINCS

DCLK

IRQ

X+

VCC_MAIN

SPRA968


F1DK/F1261CT−ND

5V_LCDVCC

5V_LCDVCC−1

5V_LCDVCC

D6DK/SS12G1CT−ND

+

C800 10.0UF 25V_(D)

LCDVCC_−15V

+C5010.0UF

U13TPS79301DBV

123

654

INGNDEN

OUTFB

BYPASS

U34MAX633

17 8

4 5

263

LBIVFB COMP

LX VOUT

LBOCPGND

LCDVCC_−15V−3

LCDVCC_−15V−2

R15743.6K

+

C674.7uF

DO−214AC(SMA)

C700.01UF

LCDVCC_+15V−1

C690.1UF

+ C63

22uF_25V_(D)

C510.1uF

3V_LCDVCC

L710uH DK PCD1345CT−ND

LCDVCC_+15V

LCDVCC_−15V−1

+

C56

2.2UF 25V_(D)

D60DK/SS12G1CT−ND

3V_LCDVCC−1

C6615pf

C680.1UF

R15830.1K

SPRA968


Appendix B Sharp Display Schematics

C380.1UF

R2

USE WITH LED B/L ONLY.

DNI IF U10 INSTALLED.

MOD

C430.1UF

LCDVCC_VCOM

LCD_B_P8R51 10

R54 10

R3

USE WITH LED B/L ONLY.

DNI IF U10 INSTALLED.

R56 10

LCD_COM

−15.0V

3.3V

UBR

R65 10

+15.0V

R4

LCD_B_P9

SPS

LCDVCC_−11.7V

LCD_B_P7

C4030.1UF

R5

LCD_B_P1

C460.1UF

CLS

LCD_B_VSYNC

R47 10G1

R44 10

R4022.7K

R401

1.5K

LCD_B_AC

G0

3.3V_LCDVCC

3.3V

R59 10

3.3V_LCDVCC3.3V_LCDVCC

LCD_B_P13

G2

V2

G3

LCD_B_P[0..15]PS

LCD_B_P5

LCD_B_P10

VEE

V3

J4

CONN Hirose FH12−50S−0.5SH

123456789

1011121314151617181920212223242526272829303132333435363738394041424344454647484950

G4

C450.1UF

LP

LCD_B_P11

LCD_B_P0

+ C41

4.7UF DNI

R53 10

V5

LCD_B_P15

G5

R69 10

R45 10

CLK

U405

LZ9FC22

1267172

345678

111213141516

181920212223

25

66

6910274563

9 28 38 46 53 60 64

656261373635343332

444342414039525150494847595857565554

2

1724

70

6867

29

3031

DCLKENABHSYNCVSYNC

R0R1R2R3R4R5

G0G1G2G3G4G5

B0B1B2B3B4B5

HRVE

VRVE

TV/MODVDD0VDD1VDD2VDD3

GND

GND

GND

GND

GND

GND

GND

UBRSPSCLSCLK

LPSPLLBRSPR

PS

DR0DR1DR2DR3DR4DR5DG0DG1DG2DG3DG4DG5DB0DB1DB2DB3DB4DB5

TEST0

TEST1TEST2

TEST4

NC1/SIZECONC0/TEST

RESET

REVREVV0

LCD_B_P14

LBR

R90 10

LCD_B_P4

5.0V

V8

−11.7V

LCD_B_P3

SPR

B0

LCD_B_P12

C440.1UF

V9

R70 0

V0

R88 10

B1

LCD_B_P2

R68 10

R67 10

VCOM

R41 10

BOTTOM CONTACTS

V1

POWER ON RESET

B2

R63 10

LCDVCC_VEE

LCD_B_HSYNC

U401

SN74LVC1G17DBVR

2 4

5

31

R0

LCDVCC_−15V

DNI

5V_LCDVCC

R42 10

C390.1UF

PIXEL CLK

B3

3.3V_LCDVCC

LCDVCC_+15V

LCD_B_PCLK

R1

LCD_B_P6

R43 10

R49 10

DATA ENABLE 18.75KHZ

B4

C4400.1UF

U10

IR3E3044 DNI

1112

16

7

16

458910

3

VCCVDD

SW

GND

NCNC

V0V1V2V3V4

COM

R710

R87 10

R403

100K

B5

5V_LCDVCC

U400

SN74LVC1G17DBVR

2 4

5

31

+ C410

4.7UF DNI

R61 10

R73 10

SPRA968


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