Conformal Computing Program July 26, 2007 NDSU Center for Nanoscale Science & Engineering Center for...

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Conformal Computing Program July 26, 2007 NDSU Center for Nanoscale Science & Engineering Center for Bits and Atoms MIT Media Lab

Transcript of Conformal Computing Program July 26, 2007 NDSU Center for Nanoscale Science & Engineering Center for...

Conformal Computing ProgramJuly 26, 2007

NDSU Center for Nanoscale Science & Engineering

Center for Bits and AtomsMIT Media Lab

CNSE CC Team

(not pictured: Ahana Gosh and Jordan Dahl)

Wallpaper Computing Display

• Extensible Medium

• Integrated Computation and Display

• Flexible Substrate

• Similarities to Wallpaper

WCD Prototypes

• Rigid 2x2 and 8x8 Prototypes

• Strip Concept

• Strip Prototypes

2x2 Prototype

Each processor scans 48 LEDs …

Processor + R’s + C

4 x 4 RGB Pixels

… and connects to 4 neighbors.

8x8 Prototype (1 processor and 16 pixels / cm2)

computing side display side

Chassis

Strip Concept

• Uses only two metal layers Lower cost, thinner, more flexible

• Strips combine to form sheets Extensible

1x8 Strip Layout

Layer 1 (display side)

Layer 2 (computing side)

2nd Strip Prototype

computing side display side

Flat Strip Display

• Top: thin 2-layer boards• Bottom: thick multi-layer boards• Must include processor-to-display cxns• No vias in strip-to-strip power distribution

Applications

• Application Services

• CA Emulation

• Distributed Graphics

• Interactive I/O

• Tactile Array

• LED Camera

Application Services

• Provides common application functions

• Functions include:– Initial program loading (IPL)– Display setting and refreshing– Inter-processor communication (IPC)– Message passing– Thread management– Subsequent program loading

CA Emulation

• Each cell has 8 configuration bits and 1 state bit• A text file format has been defined to specify the

configurations and initial states of an array of cells

• The text file is used to define the program to be loaded into a wallpaper computing display

• A message passing sequence is used to exchange data between the subarrays emulated by individual processors

Distributed Graphics

• Purpose

– Explore distributed applications capabilities using the 2x2 and 8x8 prototypes

• Objective

– Render a single graphics primitive (a quadrilateral) in a distributed fashion

Approach

• Load all processors with same program

• Inject a message into the array via one of the peripheral processors; the message describes the primitive to be rendered

• Each processor renders a sub-image and passes a copy of the message to two of its neighbors

• Duplicate messages are discarded

Algorithm

A (a1, a2)

B (b1, b2)

C (c1, c2)

D (d1, d2)

FAB = (a2-b2)x + (a1-b1)y + (a1*b2-a2*b1) FBC = (b2-c2)x + (b1-c1)y + (b1*c2-b2*c1)FCD = (c2-d2)x + (c1-d1)y + (c1*d2-c2*d1) FDA = (d2-a2)x + (d1-a1)y + (d1*d2-d2*a1)

border border pixelpixel

inside inside pixelpixel

outside outside pixelpixel

Controller and 8x8 WCD

Tactile Array

• Purpose– Produce an example of actuation

integrated with a conformal computer

• Objective– Tactile array for sensory substitution

Tactile Display Prototype

• Testbed for tactile transduction on forehead; uses biofeedback

• Sensor system– Ultrasound range finders in fly’s

eye configuration– Accurate 3.5 meter range

sensing

• Display system– Electromechanical actuators

• Processing– 3 microcontrollers in master-

slave configuration

Tactile Display Schematic

Master MCU

Slave MCU 1

Slave MCU 2

Ultrasound Range Finder

Ultrasound Range Finder

Ultrasound Range Finder

TactileActuator

TactileActuator

TactileActuator

Ultrasound

Pulses

Ultr

asou

nd

Pul

ses

Ultras

ound

Pul

ses

Tactile

Stim

ulation

Tactile

Stim

ulation

Tactile

Stim

ulation

• Transduction produced by brush on plastic disk

• Stepper motor driven by– Pulse-width modulation– Short envelope duty cycle

• Performance– No audible noise– Relatively low power

Stepper Motor & Brush

LED Camera

Programmable Cellular Arrays

• (Larger Arrays of Microcontrollers)

• Programmable Cellular Array ASIC

• Assembling Large Arrays of ASICs

• (Using the 3rd Dimension)

CA Processors

• Purpose

– Scale processors down in size (and complexity) and up in number

• Objectives– Design CMOS ASICs with arrays of

simple computational cells

– Consider sync & async approaches

Single CA Cell

Assembly Methods

• Via-to-Pad

• Roll-to-place (Part Printer)

• FSA

• R2R Flip-Chip on Flex

• Selective Device Transfer

Via-to-Pad

Roll-to-Place

• Parts are “printed” from dispensers

• Dispensers are at fixed locations relative to the roll

• (See MIT-CBA for dispenser mock-up)

Nanoblocks

FSA Process

R2R Flip-Chip on Flex Automated Assembly Corporation

Selective Device TransferFigure from www.zurich.ibm.com/st/server/selectivetrans.html