Computer Science: An Overview Tenth Edition by J. Glenn...

Copyright © 2008 Pearson Education, Inc. Publishing as Pearson Addison-Wesley

Computer Science: An Overview

Tenth Edition

by

J. Glenn Brookshear

Chapter 2:

Data Manipulation

Presentation files modified by Farn Wang

Copyright © 2008 Pearson Education, Inc. Publishing as Pearson Addison-Wesley 2-2

Chapter 2: Data Manipulation

• 2.1 Computer Architecture

• 2.2 Machine Language

• 2.3 Program Execution

• 2.4 Arithmetic/Logic Instructions

• 2.5 Communicating with Other Devices

• 2.6 Other Architectures


Von Neumann’s computer model

John von Neumann

1903-1957


Computer Architecture

• Central Processing Unit (CPU) or processor

– Arithmetic/Logic unit

– Control unit

– Registers

• General purpose - data

• Special purpose – instructions, addresses

• Bus

• Memory

• Motherboard


CPU and main memory connected

via a bus


Stored Program Concept

• A program can be encoded as bit patterns

and stored in main memory.

• From the main memory, the CPU can then

extract the instructions and execute them.

• In turn, the program to be executed can be

altered easily.


Terminology

• Machine instruction: An instruction (or

command) encoded as a bit pattern

recognizable by the CPU

• Machine language: The set of all machine

instructions recognized by a machine

– also called instruction set


Machine Language Philosophies

• Reduced Instruction Set Computing

(RISC)

– Few, simple, efficient, and fast instructions

– Examples: PowerPC from Apple/IBM/Motorola

and SPARK from Sun Microsystems

• Complex Instruction Set Computing

(CISC)

– Many, convenient, and powerful instructions

– Example: Pentium from Intel

Copyright © 2008 Pearson Education, Inc. Publishing as Pearson Addison-Wesley2-9

Machine Instruction Types

• Data Transfer: copy data from one location

to another

– I/O instructions as a special case

• Arithmetic/Logic: use existing bit patterns to

compute a new bit patterns

• Control: direct the execution of the program

– conditional ?

– indirect ?


Arithmetic/Logic Operations

• Logic: AND, OR, XOR

– Masking

• Rotate and Shift: circular shift, logical shift,

arithmetic shift

• Arithmetic: add, subtract, multiply, divide

– Precise action depends on how the values are

encoded (two’s complement versus floating-

point).


Logic operations

- Bit-wise Boolean operations

10011010

AND 11001001

10001000

2-11

10011010

OR 11001001

11011011

10011010

XOR 11001001

01010011


Rotating the bit pattern 65

(hexadecimal) one bit to the right


2015/03/17 stopped here

2-13


Adding values stored in memory


Dividing values stored in memory


The architecture of the machine

described in Appendix C

- an 8-bit CPU

8-bit bus and 8-bit data registers


Parts of a Machine Instruction

• Op-code: Specifies which operation to

execute

• Operand: Gives more detailed information

about the operation

– Interpretation of operand varies depending on

op-code

Copyright © 2008 Pearson Education, Inc. Publishing as Pearson Addison-Wesley A-18

A Simple Machine Language (I/II)

12 machine instructions

Op-code Operand Description

1 RXY LOAD reg. R from cell XY.

2 RXY LOAD reg. R with XY.

3 RXY STORE reg. R at XY.

4 0RS MOVE R to S.

5 RST ADD S and T into R. (2’s comp.)

6 RST ADD S and T into R. (floating pt.)

Copyright © 2008 Pearson Education, Inc. Publishing as Pearson Addison-Wesley A-19

A Simple Machine Language (II/II)

12 machine instructions

Op-code Operand Description

7 RST OR S and T into R.

8 RST AND S and T into R.

9 RST XOR S and T into R.

A R0X ROTATE reg. R X times.

B RXY JUMP to XY if R = reg. 0.

C 000 HALT.


The composition of an instruction for

the machine


Decoding the instruction 35A7


Microprograms in the 8-bit CPU

executing a microprogram to interpret

instructions

A tiny

processor


High-level programs

Microprogramming – hardware layers

(

• in ROM or PLA

– sometimes in flash

memory

– IBM’ers call it

firmware.

• no more ad-hoc

circuitry

2-23

circuits

microcode

CPU

machine code

nanocode

Compilers

CPU

control unit

Maurice

Wilkes

(1951-2010)

http://en.wikipedia.org/wiki/Maurice_Wilkes

http://en.wikipedia.org/wiki/Maurice_Wilkes


An encoded version of the

instructions THE ADD program ( )


Program Execution (

• Controlled by two special-purpose registers

– Program counter: address of next instruction

– Instruction register: current instruction

• Machine Cycle

– Fetch

– Decode

– Execute


The machine cycle (


Multiplexer & demultiplexer(

2-27


Decoding the instruction B258


Figure 2.10 The program from Figure 2.7

stored in main memory ready for execution


Performing the fetch step of the

machine cycle


Performing the fetch step of the

machine cycle (cont’d)


Machine cycles

- running examples

2-32

ALU

:

:

:

:

RF

R2

R1

R0

A0PC

IR

do x = x-1; while (x!=0) ; 11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus


Machine cycles running examples

- A0:fetch1

2-33

ALU

:

:

:

:

RF

R2

R1

R0

A0PC

IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A0:fetch2

2-34

ALU

:

:

:

:

RF

R2

R1

R0

A1PC

20IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A0:fetch3

2-35

ALU

:

:

:

:

RF

R2

R1

R0

A1PC

20IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A0:fetch4

2-36

ALU

:

:

:

:

RF

R2

R1

R0

A2PC

2000IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A0:decode

2-37

ALU

:

:

:

:

RF

R2

R1

R0

A2PC

2000IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A0:execute

2-38

ALU

00

:

:

:

:

RF

R2

R1

R0

A2PC

2000IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A2:fetch1

2-39

ALU

00

:

:

:

:

RF

R2

R1

R0

A2PC

2000IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A2:fetch2

2-40

ALU

00

:

:

:

:

RF

R2

R1

R0

A3PC

1100IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A2:fetch3

2-41

ALU

00

:

:

:

:

RF

R2

R1

R0

A3PC

1100IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A2:fetch4

2-42

ALU

00

:

:

:

:

RF

R2

R1

R0

A4PC

11AEIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A2:decode

2-43

ALU

00

:

:

:

:

RF

R2

R1

R0

A4PC

11AEIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A2:execute

2-44

ALU

00

:

:

:

:

RF

R2

R1

R0

A4PC

11AEIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A2:execute

2-45

ALU

00

03

:

:

:

:

RF

R2

R1

R0

A4PC

11AEIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A4:fetch1

2-46

ALU

00

03

:

:

:

:

RF

R2

R1

R0

A4PC

11AEIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A4:fetch2

2-47

ALU

00

03

:

:

:

:

RF

R2

R1

R0

A5PC

22AEIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A4:fetch3

2-48

ALU

00

03

:

:

:

:

RF

R2

R1

R0

A5PC

22AEIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A4:fetch4

2-49

ALU

00

03

:

:

:

:

RF

R2

R1

R0

A6PC

22FFIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A4:decode

2-50

ALU

00

03

:

:

:

:

RF

R2

R1

R0

A6PC

22FFIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A4:execute

2-51

ALU

00

FF

03

:

:

:

:

RF

R2

R1

R0

A6PC

22FFIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A6:fetch1

2-52

ALU

00

FF

03

:

:

:

:

RF

R2

R1

R0

A6PC

22FFIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A6:fetch2

2-53

ALU

00

FF

03

:

:

:

:

RF

R2

R1

R0

A7PC

51FFIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A6:fetch3

2-54

ALU

00

FF

03

:

:

:

:

RF

R2

R1

R0

A7PC

51FFIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A6:fetch4

2-55

ALU

00

FF

03

:

:

:

:

RF

R2

R1

R0

A8PC

5112IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A6:decode

2-56

ALU

00

FF

03

:

:

:

:

RF

R2

R1

R0

A8PC

5112IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A6:execute

2-57

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

A8PC

5112IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A8:fetch1

2-58

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

A8PC

5112IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A8:fetch2

2-59

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

A9PC

B112IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A8:fetch3

2-60

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

A9PC

B112IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A8:fetch4

2-61

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

AAPC

B1ACIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A8:decode

2-62

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

AAPC

B1ACIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- A8:execute

2-63

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

AAPC

B1ACIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- AA:fetch1

2-64

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

AAPC

B1ACIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- AA:fetch2

2-65

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

ABPC

B0ACIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- AA:fetch3

2-66

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

ABPC

B0ACIR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- AA:fetch4

2-67

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

ACPC

B0A6IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- AA:decode

2-68

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

ACPC

B0A6IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;



- AA:execute

2-69

ALU

00

FF

02

:

:

:

:

RF

R2

R1

R0

A6PC

B0A6IR

11

A6

B0

AC

B1

12

51

FF

22

AE

C0

03

00

00

20 A0: mvc R0, ‘0’

A9:

A8: br R1, AC

A7:

A6: add R1, R1, R2

A5:

A4: mvc R2, ‘-1’

A3:

A2: mov R1, AE

A1:

AA: br R0, A6

AB:

AC: halt

AD:

AE:

bus

do x = x-1; while (x!=0) ;


Communicating with Other Devices

• Controller: An intermediary apparatus that handles communication between the computer and a device

– Specialized controllers for each type of device

– General purpose controllers • USB and FireWire for PC

• Port: The point at which a device connects to a computer

• Memory-mapped I/O: CPU communicates with peripheral devices as though they were memory cells


Controllers attached to a machine’s

bus


A conceptual representation of memory-

mapped I/O


Computer-System Operation

• I/O devices and the CPU can execute

concurrently.

• Each device controller is in charge of a

particular device type.

• Each device controller has a local buffer.


Computer-System Operation

• CPU moves data from/to main memory

to/from local buffers

• I/O is from the device to local buffer of

controller.

• Device controller informs CPU that it has

finished its operation by causing an

interrupt.


Interaction of CPU with I/O devices

• I/O can be from devices, environment,

networks

• Two ways to check if an I/O event happens

– Polling

• Periodically check if the signal (bit patterns in a

memory cell or register) for an event has raised.

– Interrupt

2-75


Interaction of CPU with I/O devices

• Two ways to check if an I/O event happens

– Polling

– Interrupt

• Through a few interrupt signal lines to CPU

• can be disabled by a mask register to disable some

interrupt signal lines.

• At the decoding cycle of each machine instruction

execution, check if some unmasked interrupt lines

are 1’s.

• If some are, branch to an address (interrupt vector)

already stored for the corresponding interrupt lines.

2-76


Interrupt checking in machine cycles

2-77

CPUMemory

1

0

1mask register


Interrupts

• Interrupt transfers control to the interrupt

service routine generally, through the

interrupt vector, which contains the

addresses of all the service routines.

• Interrupt architecture must save the

address of the interrupted instruction.

• Incoming interrupts are disabled while

another interrupt is being processed to

prevent a lost interrupt.


Interrupt Handling

• The operating system preserves the state

of the CPU by storing registers and the

program counter.

• Determines which type of interrupt has

occurred:

– polling

– vectored interrupt system

• Separate segments of code determine

what action should be taken for each type

of interrupt


Interrupt Timeline


I/O Structure

• Synchronous: After I/O starts, control returns to user program only upon I/O completion.

– Wait instruction idles the CPU until the next interrupt

– Wait loop (contention for memory access).

– At most one I/O request is outstanding at a time, no simultaneous I/O processing.

• Asynchronous:


I/O Structure

• Synchronous:

• Asynchronous: After I/O starts, control returns to user program without waiting for I/O completion.

– System call – request to the operating system to allow user to wait for I/O completion.

– Device-status table contains entry for each I/O device indicating its type, address, and state.

– Operating system indexes into I/O device table to determine device status and to modify table entry to include interrupt.


Communicating with Other Devices (continued)

• Direct memory access (DMA): Main memory access by a controller over the bus

• Von Neumann Bottleneck: Insufficient bus speed impedes performance

• Handshaking: The process of coordinating the transfer of data between components



• Parallel Communication: Several

communication paths transfer bits

simultaneously.

• Serial Communication:



• Parallel Communication:

• Serial Communication: Bits are

transferred one after the other over a

single communication path.


Data Communication Rates

• Measurement units

– Bps: Bits per second

– Kbps: Kilo-bps (1,000 bps)

– Mbps: Mega-bps (1,000,000 bps)

– Gbps: Giga-bps (1,000,000,000 bps)

• Bandwidth: Maximum available rate

• Multiplexing + data-compression for

performance


Other Architectures

• Technologies to increase throughput:

– Pipelining: Overlap steps of the machine cycle

– Parallel Processing: Use multiple processors

simultaneously

• SISD: No parallel processing

• MIMD: Different programs, different data– Multi-core CPU: multiple CPU in the same chip

• SIMD: Same program, different data


Parallel computing

• bit-level:

8-bit CPU 16-bit CPU 32-bit CPU …

• instruction level – pipelining (superscalar)

2-88


Parallel computing

- memory and communications

2-89

Non-Uniform Memory Access (NUMA)

architecture

Access time to

different addresses is

different.

http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access


Parallel computing

- Classes

• Multi-core

• Symmetric multiprocessing

• Distributed computing

• Cluster computing

2-90


Parallel computing

- Classes

• Massive parallel processing

Cray 1 ILLIAC 4

2-91


Parallel computing

- Classes

• Grid computing

– distributed computing

– loose-coupled

– hetreogeneous

– geographically dispersed

– non-interactive workload

– through middleware

• Cloud computing ?

– 3rd party services of infrastructure, platform,

software from the internet 2-92


Parallel computing

- hyper-threading

• Two logical processor sharing one core.

• Intel Pentium 4

2-93

Computer Science: An Overview Tenth Edition by J. Glenn...

Documents

Transcript of Computer Science: An Overview Tenth Edition by J. Glenn...