Computer ArchitectureLecture 2

Abhinav Agarwal

Veeramani V.

Quick Recap

Various metrics in design of processor The interface & internal structure Instruction Set Architecture

Assembly instructions Instruction encoding

add r1, r2, r3

000111 00001 00010 00011

Outline

RISC Multi-cycle execution Pipelining

Reduced Instruction Set Computer (RISC) Limited no. of instructions Fixed Length Simple to decode Easier to implement in hardware Prevalent in all commercial processors at the core

level Counterpart – C(omplex)ISC

Intel processors Multi-operation instructions Still Intel processors have switched to RISC at second level

Execution Cycle of a RISC InstructionFive main phases of Instruction Lifecycle

1. IF: Instruction Fetch Read Instruction Memory at PC Bring the instruction into the CPU

2. ID/RF: Instruction Decode/Register Fetch Translate the opcode of the instruction to appropriate control

signals No. of operands Registers clearly specified in instruction code Fetch operand values from the registers

Execution Cycle of a RISC Instruction3. EX: ALU computation

Activate appropriate functional unit – Adder, Multiplier, Divider, Logical Unit

Why no Subtracter?

4. MEM: Memory Operation Load/Store data from/to Data Memory

5. WR: Register Write Write the final result value into register

A Picture speaks a thousand words

Multi Cycle Execution

Cycle Per Instruction (CPI) Kinds of Implementation:

1. One cycle for each stage Cycle time determined by longest stage CPI = ?

2. Combine all stages into a single cycle Cycle time determined by worst case instruction CPI = 1

Execution Snapshot: Cycle 1IF

00010

PC

Address Instr

00000 Mov r2, 2A

00001 Mov r3, 12

00010 Add r1,r2,r3

00011 Store r1,0(r4)

00100 XXXX

00101 XXXX

000111 00001 00010 00011

Execution Snapshot: Cycle 2ID/RF

Add

r1, r2, r3

00011

PC

Address Instr

00000 Mov

00001 Mov

00010 add

00011 Store

00100 XXXX

00101 XXXX

000111 00001 00010 00011

Reg Data

r1 12 H

r2 2A H

r3 12 H

r4 00 H

r5 01 H

Execution Snapshot: Cycle 3EX

Reg Data

r1 12 H

r2 2A H

r3 12 H

r4 00 H

r5 01 H

00011

PC

Address Instr

00000 Mov

00001 Mov

00010 add

00011 Store

00100 XXXX

00101 XXXX

000111 00001 00010 00011

Adder

12 2A

Add

r1, r2, r3

Execution Snapshot: Cycle 4MEM

00011

PC

Address Instr

00000 Mov

00001 Mov

00010 add

00011 Store

00100 XXXX

00101 XXXX

000111 00001 00010 00011

Adder

12 2A

??

Reg Data

r1 12 H

r2 2A H

r3 12 H

r4 00 H

r5 01 H

Add

r1, r2, r3

Execution Snapshot: Cycle 5WB

00011

PC

Address Instr

00000 Mov

00001 Mov

00010 add

00011 Store

00100 XXXX

00101 XXXX

000111 00001 00010 00011

Adder

Reg Data

r1 3C H

r2 2A H

r3 12 H

r4 00 H

r5 01 H

Add

r1, r2, r3

Execution Snapshot: Cycle 1IF

00011

PC

Address Instr

00000 Mov

00001 Mov

00010 add

00011 Store

00100 XXXX

00101 XXXX

111001 00001 00100 00000store

r1, 0(r4)

Instruction Execution Timeline Sequential Execution Low utilization of functional units Alternative ?

IF ID/RF

EX MEM

WB IF ID/RF

EX MEM

IF ID/RF

EX MEM

WB

Instruction Execution Timeline

add r1, r2, r3 store r1, 0(r4)

Pipelining: Concept and Example Washing machine, Dryer, Iron

source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/

Pipelining Concept

Remarkable Insight or Common Sense

source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/

Time Savings:

Per person 0%

Overall 42%

Implementation of Pipelining in RISC Parallelism in all 5 stages New instruction every cycle Best case scenario

IF ID/RF EX MEM WB

IF ID/RF EX MEM WB

IF ID/RF EX MEM WB

IF ID/RF EX MEM WB

IF ID/RF EX MEM WB

Inst

Time

Hardware Requirements

source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/

Problems

Data hazards Dependent Instructions

add r1, r2, r3 store r1, 0(r4)

Control Hazards Branches resolution

bnz r1, label add r1, r2, r3 label: sub r1, r2, r3

Structural Hazards

IF ID/RF EX MEM WB

IF ID/RF EX MEM WB

IF ID/RF EX MEM WB

IF ID/RF EX MEM WB

IF ID/RF EX MEM WB

References

Wikipedia: CPU Parallelism http://en.wikipedia.org/wiki/Central_processing_unit#Parallelism

http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/pipe_title.html