Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique...
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Transcript of Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique...
![Page 1: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/1.jpg)
Compiling ESTEREL circuitsinto finite states machines
BRES YannisStage de DEA d’Informatique 1998/1999
![Page 2: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/2.jpg)
Esterel constructive semantics
Gives, for each statement p
pE
A new environment E’
E’
A completion code k (terminated, paused or trap exit level)
k,
A derivative statement p’, to be executed on next step
p’
, provided an initial environment E :
![Page 3: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/3.jpg)
Circuit compilation
pE
E’ k,p’
Thus, each statement p of the language can be compiled into a circuit :
E are wires indicating present signals
E’ are wires indicating emitted signals
k indicates which completing code wire will be on
p’ is a another circuit activated by k wire
![Page 4: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/4.jpg)
Generated circuits
Directed graphs :
logical gates (and, or, not, …)
registers (memory elements)
wires
![Page 5: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/5.jpg)
Example of circuit
abort sustain Owhen I
I!O
K 1
K 0
0
1
0
![Page 6: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/6.jpg)
Circuits vs. automata
Circuits are roughly linear while automata are exponential
No automata for big circuits
Up to medium-sized circuits :
Only input/test dependent stuff remain at run-time
Automata are faster (run-time minimal)
Ex : Motorola measures maximal application speed
Control flow computed at compile-time
![Page 7: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/7.jpg)
Current compilation chain
strlic strlic strlic
iclc
lcsc
sscoc
.strl .strl .strlEsterel source
.ic .ic .icintermediate code
.lclinked code
.sccircuit code
.ocautomaton code
.sscsorted circuit code
scssc sccausal
![Page 8: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/8.jpg)
Future compilation chain
strlic strlic strlic
iclc
lcsc
.strl .strl .strlEsterel source
.ic .ic .icintermediate code
.lclinked code
.sccircuit code
.ocautomaton code
sscoc
.sscsorted circuit code
scssc sccausal
scoc
![Page 9: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/9.jpg)
SSCOC automaton generation
Circuit is seen like a set of boolean equations
To be evaluated, equations must be sorted (.ssc)
Sorting fails on several kind of cyclic circuits !
Code unmaintained...
![Page 10: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/10.jpg)
SCOC automaton compilation
Algorithm follows electrical current
new informations (hot)propagated informations (cold)
I!O
K 1
K 0
0
1
0
![Page 11: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/11.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Building initial statePropagating registers
1
0
I!O
K 1
K 0
0
1
0
![Page 12: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/12.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Building initial statePropagating registers
1
0
I!O
K 1
K 0
0
1
0
![Page 13: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/13.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Building initial statePropagating registers
1
0
0
I!O
K 1
K 0
0
1
0
![Page 14: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/14.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Building initial statePropagating registers
1
0
0
0
I!O
K 1
K 0
0
1
0
![Page 15: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/15.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Building initial statePropagating registers
1
0
0
0
0
I!O
K 1
K 0
0
1
0
![Page 16: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/16.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Building initial statePropagating registers
1
0
0
0
0
I!O
K 1
K 0
0
1
0
![Page 17: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/17.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Building initial statePropagating registers
1
0
0
0
0
I!O
K 1
K 0
0
1
0
![Page 18: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/18.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Building initial statePropagating registers
1
0
0
0
0
I!O
K 1
K 0
0
1
0
![Page 19: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/19.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Building initial statePropagating registers
11
0
0
0
0
I!O
K 1
K 0
0
1
0
![Page 20: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/20.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Building initial statePropagating registers
11
0
0
0
0
I!O
K 1
K 0
0
1
0
![Page 21: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/21.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state built
11
0
0
0
0
I!O
K 1
K 0
0
1
0
!O
![Page 22: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/22.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
11
0
0
0
0
I!O
K 1
K 0
0
1
0
!O
![Page 23: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/23.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers values
0
1
I!O
K 1
K 0
0
1
0
!O
![Page 24: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/24.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registers
0
1
I!O
K 1
K 0
0
1
0
!O
![Page 25: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/25.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registers
0
1
I!O
K 1
K 0
0
1
0
!O
![Page 26: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/26.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registers
0
1
I!O
K 1
K 0
0
1
0
!O
![Page 27: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/27.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registers
0
1
I!O
K 1
K 0
0
1
0
!O
![Page 28: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/28.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
0
1
I!O
K 1
K 0
0
1
0
!O
![Page 29: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/29.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is present
0
1
?I!O
K 1
K 0
0
1
0
!O
![Page 30: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/30.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is present
0
1
1
?I!O
K 1
K 0
0
1
0
!O
![Page 31: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/31.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is present
0
1
0
1
?I!O
K 1
K 0
0
1
0
!O
![Page 32: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/32.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is present
0
1
0
1
?I!O
K 1
K 0
0
1
0
!O
![Page 33: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/33.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is present
0
0
1
0
1
?I!O
K 1
K 0
0
1
0
!O
![Page 34: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/34.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is present
0
0
1
0
1
?I!O
K 1
K 0
0
1
0
!O
![Page 35: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/35.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is present
00
0
1
0
1
?I!O
K 1
K 0
0
1
0
!O
![Page 36: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/36.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is present
00
0
1
0
1
?I!O
K 1
K 0
0
1
0
!O
![Page 37: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/37.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Final state reachedBuilding branch where I is present
00
0
1
0
1
?I!O
K 1
K 0
0
1
0
!O
?I
![Page 38: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/38.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is presentBuilding branch where I is absent
0
1
#I!O
K 1
K 0
0
1
0
!O
?I
![Page 39: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/39.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is presentBuilding branch where I is absent
0
1
0
#I!O
K 1
K 0
0
1
0
!O
?I
![Page 40: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/40.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is presentBuilding branch where I is absent
0
1
1
0
#I!O
K 1
K 0
0
1
0
!O
?I
![Page 41: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/41.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is presentBuilding branch where I is absent
0
1
1
0
#I!O
K 1
K 0
0
1
0
!O
?I
![Page 42: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/42.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is presentBuilding branch where I is absent
0
1
1
1
0
#I!O
K 1
K 0
0
1
0
!O
?I
![Page 43: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/43.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is presentBuilding branch where I is absent
0
1
1
1
0
#I!O
K 1
K 0
0
1
0
!O
?I
![Page 44: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/44.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is presentBuilding branch where I is absent
01
1
1
1
0
#I!O
K 1
K 0
0
1
0
!O
?I
![Page 45: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/45.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is presentBuilding branch where I is absent
01
1
1
1
0
#I!O
K 1
K 0
0
1
0
!O
?I
![Page 46: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/46.jpg)
SCOC automaton compilation
new informations (hot)propagated informations (cold)
Initial state builtBuilding state 1
Loading registers valuesPropagating registersForking on input signal I
Building branch where I is presentBuilding branch where I is absent
State 1 reached again
01
1
1
1
0
#I!O
K 1
K 0
0
1
0
!O
?I
# I.!O
![Page 47: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/47.jpg)
Circuit saving and restoring
To avoid saving the whole circuit at each step of automata building :
Restoration data are stored in a stack of stacks
![Page 48: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/48.jpg)
Circuit saving and restoring
To avoid saving the whole circuit at each step of automata building :
Restoration data are stored in a stack of stacks
![Page 49: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/49.jpg)
Circuit saving and restoring
To avoid saving the whole circuit at each step of automata building :
Restoration data are stored in a stack of stacks
![Page 50: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/50.jpg)
Circuit saving and restoring
To avoid saving the whole circuit at each step of automata building :
Restoration data are stored in a stack of stacks
![Page 51: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/51.jpg)
Circuit saving and restoring
To avoid saving the whole circuit at each step of automata building :
Restoration data are stored in a stack of stacks
![Page 52: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/52.jpg)
Circuit saving and restoring
To avoid saving the whole circuit at each step of automata building :
Restoration data are stored in a stack of stacks
![Page 53: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/53.jpg)
Circuit saving and restoring
To avoid saving the whole circuit at each step of automata building :
Restoration data are stored in a stack of stacks
![Page 54: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/54.jpg)
Circuit saving and restoring
To avoid saving the whole circuit at each step of automata building :
Restoration data are stored in a stack of stacks
![Page 55: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/55.jpg)
Signal relations processing
Stored in a directed graph
Example :3 22 11 # 4 # 5
3
21
4 5
: present absentabsent present
: present present
: absent absent
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Signal relations processing
Stored in a directed graph
Example :3 22 11 # 4 # 5
3
21
4 5
: present absentabsent present
: present present
: absent absent
![Page 57: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/57.jpg)
Signal relations processing
Stored in a directed graph
Example :3 22 11 # 4 # 5
3
21
4 5
: present absentabsent present
: present present
: absent absent
![Page 58: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/58.jpg)
Signal relations processing
Stored in a directed graph
Example :3 22 11 # 4 # 5
3
21
4 5
: present absentabsent present
: present present
: absent absent
![Page 59: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/59.jpg)
Signal relations processing
Stored in a directed graph
Example :3 22 11 # 4 # 5
3
21
4 5
: present absentabsent present
: present present
: absent absent
![Page 60: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/60.jpg)
Signal relations processing
Stored in a directed graph
Example :3 22 11 # 4 # 5
3
21
4 5
: present absentabsent present
: present present
: absent absent
![Page 61: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/61.jpg)
Signal relations processing
Stored in a directed graph
Example :3 22 11 # 4 # 5
3
21
4 5
: present absentabsent present
: present present
: absent absent
![Page 62: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/62.jpg)
Signal relations processing
Stored in a directed graph
Example :3 22 11 # 4 # 5
3
21
4 5
: present absentabsent present
: present present
: absent absent
![Page 63: Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.](https://reader030.fdocuments.us/reader030/viewer/2022032803/56649e245503460f94b133c0/html5/thumbnails/63.jpg)
Smart circuit evaluation
Circuit evaluation algorithm stops as soon as all required nets are stabilized :
Registers (determine next state)
K0/K1 (determine whether automaton has terminated)
Output signals
Action nets (side-effects operating on values)
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Input partitionning
After registers propagation :
Inputs reachable from required nets will be processed first
Other inputs will probably not be processed at all
Depending on current state, parts of the circuit are disabled
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Input sorting
Example : bus arbiter
Set of cells requesting the access to a data bus
Cells have rotating priorities
bus
Cell #1
Cell #2
Cell #3
Cell #4
Cell #5
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Input sorting
Inputs are sorted upon the number of reachable registers
This turns transitions from full trees (2n-sized) to combs (n-sized):
2
?R eq1!A ck1
#R eq1
?R eq2!A ck2
?R eq3!A ck3
#R eq3
1
#R eq2
3
?R eq2!A ck2
#R eq2
?R eq3!A ck3
?R eq1!A ck1
#R eq1
#R eq3
?R eq3!A ck3
#R eq3
?R eq1!A ck1
?R eq2!A ck2
#R eq2
#R eq1
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DAG sharing
present A emit A' end present
||
present B emit B' end present
Goals :
Saving memory
Emphazing semantic aspects
?A . !A ' #A
?B . !B '
#B ?B . !B '
#B
?A . !A ' #A
?B . !B ' #B
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Performance comparison