Multi-Clock Domain Analysis and Modeling ofAll-Digital Frequency Synthesizers

Ioannis L. Syllaios and Poras T. BalsaraDepartment of Electrical Engineering

University of Texas at DallasRichardson, Texas 75083–0688

Email: syllaios@ieee.org and poras@utdallas.edu

Abstract— All-digital phase-locked loops (ADPLLs) are inher-ently multi-rate systems with time-varying behavior. In supportto this statement accurate multi-clock domain models of ADPLLfrequency synthesizers are presented. Their analytically derivedphase transfer characteristics accurately predict second ordereffects (such as spectral aliasing) that are not captured usingconventional modeling approaches. The results are validatedthrough simulations using well accepted time-domain modelingtechniques of an RF ADPLL.

I. INTRODUCTION

Advanced low-voltage nanometer-scale CMOS processesallow for a large degree of scalability and integration of digitalcircuitry but greatly increase the design cycle of pure analog ormixed-signal components due to poor process characterizationand parameter spread. High-performance frequency synthesiscircuits are traditionally implemented using a charge-pumpphase-locked loop (PLL) with a voltage-controlled oscillator(VCO). In the effort to migrate such analog-centric circuitsin the digital-centric regime, recent all-digital PLL (ADPLL)developments explore the fast switching characteristics ofMOS transistors of CMOS processes to replace the charge-pump with a time-to-digital converter (TDC) and the VCOwith a digitally-controlled oscillator (DCO) [1]-[4]. The blockdiagram of a phase-domain ADPLL frequency synthesizer isshown in Fig. 1 [5].

The quantized bit-to-frequency and time-to-bit conversionsin the DCO and the TDC, respectively, result in the generationof synthesized clock signals with reduced spectral purity (highspurious content) compared to the synthesized clock signalsof high-performance analog-centric counterpart topologies [6].However, fine bit-to-frequency resolution is typically achievedby means of high-speed Σ∆ dithering of the DCO tuningvaractors, at the cost of increased far-out digital noise floor,by exercising flexible-rate clock signals that are derived fromthe DCO itself using frequency division [7] (see Fig. 1).Similarly, the time-to-bit resolution is typically improved bynoise-shaping [8], time amplification [2], or by introducinglow-level noise-shaped randomization of the reference clockby means of a digital-to-time converter (DTC) [9].

Attributed to the multi-clock domain operation of ADPLLs,aliasing effects due to the phase multiple down-samplingand interpolation operations result in excessive in-band phasenoise that is not predicted using conventional linearized

Linear phase detector

Loop filter

dco

Fractional phase

estimation

RFfFCW

REFf

ref

REFf

e

DCXO

REFf

1

TDC

KDCO(Hz/LSB)

R

ITW

FTW

RF Rf

DCO

refT

refT

Fig. 1. Phase-domain ADPLL frequency synthesizer.

time-invariant ADPLL models. These are based on either acontinuous-time s-domain model or a reference-rate discrete-time z-domain model [5], [10]-[13]. Such models have limitedaccuracy because they neglect the actual down-sampling andinterpolation processes that the phase signals undergo as theypropagate from the DCO clock domain to the reference clockdomain and the opposite, respectively [14]-[16].

Contrary to the conventional modeling approach, a mixed-type discrete/continuous-time domain model was recently pro-posed for the study of ADPLL phase/frequency modulators[16] (see Fig. 2). The down-sampling of the RF DCO phase tothe reference clock-domain was modeled as the multiplicationwith a reference-rate periodic impulse train and the transitionfrom the digital to the RF continuous-time domain with thezero-order-hold (ZOH) operator that mimics the flip-flop regis-ter that applies the tuning data to the DCO. For the first time itwas revealed that the output phase of the ADPLL is effectivelythe result of a time-varying recursive filtering operation onthe output phase signal that is normally predicted using theconventional linear time-invariant modeling techniques.

In this paper it is analytically shown that such time-varying filtering operation, inherent in the ADPLL structure,is responsible for the secondary effects pertaining to its multi-clock domain operation such as the excessive in-band phasenoise power due to the Σ∆ dithering of the DCO varactors,

978-1-4244-9474-3/11/$26.00 ©2011 IEEE 153

Vf

DCOK

TW[k]

dco [k]

refT

1s

refT

dco (t)

Discrete-time domain

Continuous-time domain

ZOH

e[k]ref [k]

DCO

Loop filter

REFf

dco refkT

Fig. 2. Mixed-type (i.e., z-domain/s-domain) model of the ADPLL frequencysynthesizer in Fig. 1 (adapted from [16]).

an effect that was intuitively predicted in [17]. To this end,the mixed-type model of Fig. 2 is extended to a discrete-timemulti-rate model in order to capture the multi-rate operation atthe boundaries of the DCO from the tuning word (TW) to thedigital regeneration of the DCO phase φdco. The analysis ofthe presented multi-rate model highlights the time-varying be-havior of ADPLLs and accurately predicts their phase transfercharacteristics across all internal operating clock domains.

II. OVERVIEW OF THE ADPLL OPERATION

With reference to the ADPLL frequency synthesizer in Fig.1, in tracking mode the center frequency of the DCO frf (RFcarrier) is related to the reference frequency fref of a digitally-controlled crystal oscillator (DCXO) through the frequencycommand word (FCW) according to frf = FCWfref (in Hz).The linear phase detection is based on digital accumulationof clock cycles (i.e., phase). The reference phase φref isgenerated by accumulating FCW RF-clock cycles at fREF -rate and the composite DCO phase φdco is generated using thecombination of digital accumulation of unit RF-clock cyclesand the TDC. The latter is employed for the estimation ofthe fractional phase of the DCO. The resulting digital phaserepresentation of the DCO is synchronously handed-over to thereference-clock domain in order to be compared with φref .The generated phase error data φe are filtered through thedigital loop filter in order to produce the tuning word (TW)that controls the frequency of the DCO.

III. MULTI-RATE MODELING OF A DCO

In order to extend the mixed-type model of Fig. 2 to adiscrete-time multi-rate model that closely captures the multi-rate operation of the ADPLL in Fig. 1, the continuous-timephase of the DCO is sampled at the RF-rate as shown in Fig. 3-(a). In this way the continuous-time model of the DCO in Fig.2 can be converted to a discrete-time multi-rate model withup-sampling/interpolation and decimation operation interfaces(see Fig. 3-[b]) on the basis of the following Z-transformapplied from the input of the ZOH filter to the RF-sampledphase of the DCO ϕdco(nTrf )

Z

L−1

Hzoh(s)

1

s

∣∣∣∣t=nTrf

= Hzoh(z)

Trfz − 1

(1)

where, Hzoh(s) is the s-domain transfer function of theZOH filter with Hzoh(s)=(1 − e−sTref )/s and Hzoh(z) is

Vf

DCOK

TW[k]

dco [k]

refT

1s

refT

dco (t)

ZOH

DCO

rfT

dco [n]

Vf

DCOK

TW[k]

dco [k]

1N- 1rfT

z dco [n]

ZOH

DCO

N

N0

(a)

(b)

Fig. 3. Multi-rate DCO modeling. (a) Mixed-type discrete/continuous-timemodel with RF-sampling. (b) Discrete-time multi-rate model.

the RF-rate z-domain transfer function of a discrete-timeZOH interpolation filter with Hzoh(z)=(1− z−N )/(1− z−1),z=ejωTrf =ejΩrf , Ωrf ∈ [−π, π] (in rad) and N=FCW .

It is noted that for the purposes of this paper the DCOoperates on an integer channel, i.e., frf = FCWfref (inHz), where, FCW is integer. Also, all the digital phase signalspertaining to the ADPLL operation assume floating pointrepresentation.

IV. MULTI-RATE MODELING OF ADPLL FREQUENCYSYNTHESIZERS

The mixed-type (continuous/discrete-time) model shown inFig. 2 of the ADPLL frequency synthesizer in Fig. 1 is readilyconverted to a discrete-time multi-rate model after replacingthe s-domain model of the DCO with its corresponding multi-rate model in Fig. 3-(b). The resulting linear time-variantmodel is shown in Fig. 4. It also includes the primary noisesources that affect the phase noise of the RF DCO clock.These are the reference-rate phase noise source ϕn,ref , whichreflects the phase noise of the DCXO and the phase noise thatis induced due to the limited resolution of the TDC, the RF-rate phase noise of the DCO itself ϕn,dco and the RF/R-ratequantization noise qn,σδ that is induced due to the frequencyresolution enhancement mechanism of the DCO (here, fRF/R-rate Σ∆ dithering with normally integer division factor R).The phase noise sources of the DCXO and DCO are eachmodeled as a discrete-time random sequence that reflects theabsolute-jitter of the corresponding clock signal [18], [19].

For the derivation of the output phase spectrum of theDCO due to the various noise sources in the ADPLL thesuperposition principle applies based on the linearity of themodel. The output phase spectrum Φout(Ωrf ) due to the phasenoise of the DCO ϕn,dco is found as follows

Φout(Ωrf ) = Φn,dco(Ωrf ) (2)

− F (NΩrf )HR1(Ωrf )HI(Ωrf )Φout(NΩrf )

154

Vf

DCOK

out

1N- 1rfT

z ZOH-1

DCO

N

N0

1R-

ZOH-2

R0

F(z)

DH (z)

n,ref

n,Q n,dco

oute

Fig. 4. Multi-rate model of the ADPLL frequency synthesizer in Fig. 1.

where, F (NΩrf ) is the transfer function of the loop filter,HR1(Ωrf ) is the transfer function of the ZOH filter thatinterpolates the reference-rate TW to the RF-rate, HI(Ωrf )is the transfer function of the RF-rate DCO integrator andΦout(NΩrf ) is the spectrum of the down-sampled RF outputphase to the reference rate. The latter is given as [20], [21]

Φout(NΩrf ) =1

N

N−1∑n=0

Φout(Ωrf − n2π

N) (3)

=1

NΦout(Ωrf ) +

1

N

N−1∑n=1

Φout(Ωrf − n2π

N)

After placing (3) in (2) and solving with respect toΦout(Ωrf ) it is found that

Φout(Ωrf ) = Hn,dco(Ωrf )Φn,dco(Ωrf ) (4)

− Halias(Ωrf )N−1∑n=1

Φout(Ωrf − n2π

N)

where, Hn,dco(Ωrf ) is a high-pass transfer function seenby the DCO phase noise and Halias(Ωrf ) is a low-passtransfer function, inherent in the ADPLL structure, seen bythe generated images of the output phase spectrum Φout(Ωrf )due to the sampling of the RF output phase with the referenceclock. They are described by the following equations

Hn,dco(Ωrf ) =N

N + F (NΩrf )HR1(Ωrf )HI(Ωrf )(5)

and

Halias(Ωrf ) =F (NΩrf )HR1(Ωrf )HI(Ωrf )

N + F (NΩrf )HR1(Ωrf )HI(Ωrf )(6)

Following a similar procedure for the remaining noisesources, the interpolative transfer functions seen by thereference-rate phase noise source ϕn,ref and the fRF/R-rateΣ∆ quantization noise source qn,σδ are given as

Hn,ref (Ωrf ) =NF (NΩrf )HR1(Ωrf )HI(Ωrf )

N + F (NΩrf )HR1(Ωrf )HI(Ωrf )(7)

and

Hn,σδ(Ωrf ) =NHD(RΩrf )HR2(Ωrf )HI(Ωrf )

N + F (NΩrf )HR1(Ωrf )HI(Ωrf )(8)

out rf

n,dcoH z

n,refH z

n,H zR

N n,ref ref

n,Q

n,dco rf

aliasH z

2j nNe

2j N 1 nNe

...

in rf

out rfnT

Fig. 5. Multi-rate model equivalent to the model in Fig. 4, as per (9).

where, HD(RΩrf ) is the Σ∆ noise-shaping transfer functionwith HD(z)=(1−z−1)m, m is the order of the Σ∆ modulator(typically a MASH structure [22], [23]) and HR2(Ωrf ) is thetransfer function of the ZOH filter that interpolates the fRF/R-rate quantization noise qn,σδ to the RF-rate.

By applying the superposition principle the composite out-put phase spectrum of the ADPLL is obtained as

Φout(Ωrf ) = Φin(Ωrf ) (9)

− Halias(Ωrf )N−1∑n=1

Φout(Ωrf − n2π

N)

where, Φin(Ωrf ) = Hn,dco(Ωrf ) Φn,dco(Ωrf ) + Hn,ref (Ωrf )Φn,ref (NΩrf ) + Hn,σδ(Ωrf ) Qn,σδ(RΩrf ).

Equation (9) forms the basis for the multi-rate model shownin Fig. 5, which is equivalent to the multi-rate model in Fig.4. This model clearly reflects the time-varying behavior ofthe ADPLL frequency synthesizer. Specifically, it indicatesthat the phase of the synthesized RF clock is effectively theresult of a time-varying recursive filtering operation on theoutput phase (here, denoted as ϕin) that is typically predictedusing conventional linear time-invariant modeling techniques.These techniques neglect the frequency translations of theoutput phase spectrum Φout(Ωrf ), which, here, are accuratelycaptured in the second term of (9). It can be shown that

Φout(Ωrf ) ' Φin(Ωrf ) (10)

− Halias(Ωrf )N−1∑n=1

A(Ωrf − n2π

N)Φin(Ωrf − n

2π

N)

where, A=1/(1−Halias).

V. SIMULATIONS

The presented analysis has been validated using well ac-cepted time-domain simulation techniques of an RF ADPLLfrequency synthesizer [24] with the following parameters:type-II second-order configuration with proportional-plus-integral (P+I) loop filter F (z)=2−3 +2−8/(z−1), fREF=40MHz, FCW=25, fRF=1 GHz and Kdco=10 kHz/LSB. Theanalytically derived output phase-noise spectrums using (10)are shown in Fig. 6 and Fig. 7 superimposed on the simulatedphase-noise spectrums. They accurately track the simulationsproving the validity of the presented multi-clock domainanalysis and modeling of all-digital frequency synthesizers.

155

104 105 106 107 108170

160

150

140

130

120

110

100

L(

f) (d

Bc/H

z)

f (Hz)

SimulationConventional methodAnalytical method (10)DCO PN profile

Fig. 6. Output phase-noise spectrum of the ADPLL due to the phase noiseof the DCO. DCO phase noise profile with -162 dBc/Hz thermal noise floorand -130 dBc/Hz at 1 MHz upconverted thermal noise.

104 105 106 107 108200

190

180

170

160

150

140

L(

f) (d

Bc/

Hz)

f (Hz)

SimulationConventional methodAnalytical method (10)

Fig. 7. Output phase-noise spectrum of the ADPLL due to the Σ∆dithering of the DCO varactors. Third-order MASH 1-1-1 Σ∆ modulatorwith fRF/4=250 MHz.

VI. CONLCUSION

All-digital frequency synthesizers are inherently multi-ratesystems with time-varying behavior. Conventional modelingtechniques of such systems are based on linear time-invariantmodels that fail to capture second order effects (such as spec-tral aliasing) pertaining to their multi-clock domain operation.In this paper, accurate linear time-variant multi-rate models ofADPLL frequency synthesizers have been presented. It wasanalytically shown that the phase of their synthesized RF clockis effectively the result of a time-varying recursive filteringoperation on the output phase that is typically predicted usingconventional linear time-invariant models. The results havebeen validated through simulations using well accepted time-domain simulation techniques of an RF ADPLL.

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