1132 IEEE TRANSACTIONS ON COMPUTERS, VOL. c-23, NO. 11, NOVEMBER 1974

F(xo) = {1 + ((rDrT) )2}12 < {1 + ((rD))2((rr))2112.

Q.E.D.

REFERENCES[1] L. A. Pipes, "Matrix theory of multiconductor transmission

lines," Phil. Mag., 7th ser., vol. 24, pp. 97-113, July 1937.[21 , "Steady-state analysis of multiconductor transmission

lines," J. Appl. Phys., vol. 12, pp. 782-799, Nov. 1941.[3] D. B. Jarvis, "The effects of interconnections on high-speed

logic circuits," IEEE Trans. Electron. Comput., vol. EC-12,pp. 476-487 Oct. 1963.

[4] A. Feller, H. R. Kaupp, and J. J. Digiacomo, "Crosstalk andreflections in high-speed digital systems," in AFIPS Proc.,1966 Fall Joint Computer Conf., vol. 27, Pt. 1. Washington,D. C.: Spartan 1965, pp. 511-525.

[5] S. Hayashi, Surges on Transmission System (in English).Tokyo, Japan: Denki Shoin, 1955.

[6] I. Catt, "Crosstalk (noise) in digital systems," IEEE Trans.Electron. Comput., vol. EC-16, pp. 743-763, Dec. 1967.

[7] M. A. Murray-Lasso, "Unified matrix theory of lumped anddistributed directional couplers," Bell Syst. Tech. J., vol. 47,pp. 39-71, Jan. 1968.

[8] J. A. DeFalco, "Reflection tnd crosstalk in logic circuit inter-connections," IEEE Spectrum, vol. 7, pp. 44-50, July 1970.

[9] S. Matsushita, "Propagation modes on the multiwire transnis-sion line with inhomogeneous medium," Trans. Inst. Electron.Commun. Eng. Jap., vol. 53-A, pp. 515-522, Oct. 1970. (Transl.:Washington, D. C.: Scripta.)

[10] -, "Transmission characteristics of the multiwire line,"Trans. Inst. Electron. Commun. Eng. Jap. (in English), Vol.53-A, pp. 671-678, Dec. 1970 (Transl.: Washington, D. C.:Scripta).

[11] "Estimation of the induced noise on the multiwire tran-missions line," Trans. Inst. Electron. Commun. Eng. Jap. vol.54-C, pp. 257-265, Mar. 1971 (Transl.: Washington, D. C.:Scripta).

[12] R. S. Varga, Matrix Iterative Analysis. Englewood Cliffs,N. J.: Prentice-Hall, 1962. (Asian ed.: Tokyo, Japan: Maruzen,1964.)

[13] A. Ostrowski, "tjber die Determinanten mit uberwiegenderHauptdiagonale," Comment. Math. Helvetici, vol. 10, pp. 69-96,1937.

[14] K. Fan, "Note on M-matrices," Quart. J. Math. Oxford, 2ndSeries, vol. 11, pp. 43-49, 1960.

[15] 0. Perron, "Zur Theorie der Matrizes," Math. Ann., vol. 64,pp. 248-263, 1907.

Shigenori Matsushita was born in Tokyo,Japan, on March 11, 1936. He received theB.E.E. degree from the University of Tokyo,

C Tokyo, Japan and the M.S. degree from the

University of Illinois, Urbana, in 1959 and1963, respectively.Since 1959, he has been with the Electronic

Computer Division, Tokyo Shibaura Electric____A Company, Ltd., Tokyo, Japan. Meanwhile,

he studied and worked at the Department ofElectrical Engineering and the Digital Com-

puter Laboratory, University of Illinois, Urbana, from 1962 to 1963,as a Fulbright Exchange Student. His works have been in develop-ment and design of computer systems, especially in digital circuits,microprogramming, and computer organization.Mr. Matsushita is a member of the Institute of Electronics and

Communication Engineers of Japan and the Information ProcessingSociety of Japan.

Tohru Moto-Oka (M'62) was born in Tokyo,Japan, on April 7, 1929. He received theB.E.E. and Dr. Eng. degrees from the Uni-versity of Tokyo, Tokyo, Japan, in 1952 and1958, respectively.

Since 1957, he has been with the Depart-ment of Electrical Engineering, Universityof Tokyo, as an Assistant Professor and as aProfessor. From 1961 to 1962, he was withthe Digital Computer Laboratory, Uni-versity of Illinois, Urbana, as a Visiting

Assistant Professor, and from 1968 to 1969, he was a Visiting Pro-fessor at Washington University, St. Louis, Mo. His researchinterests have been in digital circuits, computer organizations,numerical controls, design automation of computers, and formal,language structures.

Dr. Moto-Oka is a member of the Institute of Electronics andCommunication Engineers of Japan, the Information ProcessingSociety of Japan, and the Institute of Electrical Engineers of Japan

Comparison of Parallel and Deductive Fault Simulation MethodsHERBERT YU-PANG CHANG, SENIOR MEMBER, IEEE, STEPHEN G. CHAPPELL, MEMBER, IEEE,

CHARLES H. ELMENDORF, AND LONNIE D. SCHMIDT

Abstract-A comparison of the central processing unit (CPU)time and storage requirements for the parallel and deductive faultsimulation techniques is presented. Versions of a parallel anddeductive simulator were implemented and the comparison per-

formed on an IBM System/360 Model 67 by simulating representa-tive circuits including shift registers, sequencers, counters, twomemory units, and a processor. The results indicate that the deduc-tive technique requires less CPU time for "loosely sequential"circuits or circuits having large numbers of simulated faults (e.g.,>1000). The paraUel technique is faster for small (e.g., < 500 gates)"highly sequential" circuits or for small numbers of simulated faults.

Manuscript received November 9, 1973; revised May 7, 1974.H. Y. Chang, S. G. Chappell, and C. H. Elmendorf are with Bell

Laboratories, Naperville, Ill. 60540.L. D. Schmidt was with Bell Laboratories, Naperville, Ill. 60640.

He is now with McDonnell Douglas Automation Company, St. Louis,Mo. 63166.

The storage required for a parallel simulator, however, can alwaysbe less than that required for a deductive simulator. In general, ifsufficient memory is available, the deductive simulator is the morecost-effective simulator when a wide range of circuits is to be simu-lated and only one type of simulator is available. A substantialsavings in logic circuit development cost can be realized when theproper simulation technique is used for logic design verification,fault analysis, and the generation of diagnostic data.

Index Terms-Deductive simulation method, fault diagnosis, faultsimulation, logic design verification, parallel simulation method.

I. INTRODUCTIONTHE USE of digital fault simulation has been widelyTaccepted in computer and telephone industries for

CHANG et al.: PARALLEL AND DEDUCTIVE FAULT SIMULATION METHODS

logic design verification, fault analysis, and the generationof diagnostics. Most of the fault simulators that havebeen implemented to date can be classified into threecategories. The first category employs the single faultinjection technique which simulates either the fault-freecircuit or one of the faulty circuits. T'he second categoryemploys the parallel technique whereby the true value(the "good" machine) and a small set of faults aresimtlated concurrently. Representative of this approachare the Sequential Analyzer [1], the IBM Simulatorused for Saturn computer design [2], and the TEGASsimulator [3]. The third category employs the deductivetechnique whereby all faults are considered in one simula-tion pass and a list of fault symptoms are propagatedfrom the site (s) of failure to circuit outputs by the useof fault list manipulations. One implementation of thedeductive technique has been reported by Armstrong[4]. In comparing the three techniques, the single faultinjection technique can be considered a degeneratecase of the parallel technique and will therefore not bediscussed as a separate type.

Since simulation is an essential step of the computer-aided design process for digital systems, the efficiencyof particular simulator implementation becomes a majorconcern. Because simulator behavior cannot be readilydetermined analytically, an experimental study wasperformed (on the IBM System/360 Model 67) to deter-mine the relative efficiencies of the parallel and thedeductive techniques, so as to yield some guidelines toselect the most cost-effective fault simulation techniquefor a particular application. The deductive simulator wasimplemented first, for simulating large circuits with manyfaults. The parallel simulator was later implemented toprovide a cost-effective way of simulating small circuit[5], [6]. The purpose of this paper is to report the resultsof comparing the two implementations of parallel anddeductive fault simulation techniques.A study of this type is rather difficult to perform

because the comparison must somehow account for dif-ferences in circuit complexity, input tests applied to thecircuit, algorithms used to implement the simulationtechnique, as well as actual coding efficiency. However,many of these circuit differences can be accounted forby considering the relationship between the number offaults detectable at each gate output and the total numberof faults in the circuit. In Section II, a brief review ofthe parallel and the deductive simulation techniques ispresented. The results of central processing unit -(CPU)time comparison and storage usage comparison arepresented in Section III.

II. SIMULATION TECHNIQUES

The following definitions and assumptions apply toboth the parallel and the deductive approaches. Thesimulators allow both unit and zero-delay gate modelsand simulate using a 3-valued logic (0, 1, and x) for thefault-free circuit and a 2-valued logic for the faulty circuit.Only single stuck-at type faults are considered. Thetrue value of a logic gate is the output value (0, 1, or x)

GATE TRUE VALUE FAULT WORDA ! 0ooQB ,.o Ejo,oiJG E1110

A

Fig. 1. Parallel fault simulation for a fault-free gate.

,of the fault-free gate. A fault is detectable on the outputof a gate G if the presence of the fault will complementthe true value on the output of G. This definition ismeaningful only if the true value of G is logical 0 or 1.Therefore, no faults are detectable on the output of anygate whose true value is x (unknown). Furthermore,any fault(s) which will cause any gate output value tobe unknown are not propagated.Both the parallel and deductive simulators were run

on the IBM System/360 Model 67 computer. Thealgorithm used for parallel simulation is described in[1]; the algorithm used for deductive simulation isdescribed in [6]. Both simulators are table driven anduse selective trace.

A. Parallel TechniqueIn parallel simulation, a fault word is associated with

each gate in the circuit and contains 1 bit for each faultbeing simulated. If the fault word contains N bits andF faults must be simulated, then [F/N]' passes must bemade with N faults being simulated during each pass.Faults are chosen for each pass at random with no con-sideration given to the effect that a particular fault setwill have on circuit activity. The advantage of the paralleltechnique is that a gate's output fault word is computedby simple logical operations on the input fault words.An example of parallel simulation for a fault-free

NAND gate and five faults is shown in Fig. 1. The faultsare numbered 1-5 from left to right in the fault word.On the output of gate G, only fault 5 is detectable sincethe bit corresponding to that fault is 0 and the true valueis 1. To allow proper handling of x's (don't know values),the true value is not computed as a part of the fault wordbut is computed in a separated operation.

B. Deductive TechniqueDeductive fault simulation involves allocating a fault

list to each gate. The fault list contains one entry foreach fault which is detectable on the output of that gateplus one entry containing the number of faults in thelist. The fault list on a gate's output can be computedfrom fault lists associated with its inputs as described in[4].The same example presented in Fig. 1 for parallel

simulation is shown in Fig. 2 using deductive simulation.The true values (TVAL) of inputs A and B are, respec-tively, 1 and 0. Faults 1, 3, and 4 appear in the list as-sociated with input A because (singly) their presence

1 [M] denotes the smallest integer equal to or greater than M.

1133

IEEE TRANSACTIONS ON COMPUTERS, NOVEMBER 1974

A

B

Fig. 2. Deductive fault simulation for a fault-free gate.

complements the true value of A. A similar argumentapplies to input B. According to the fault list algebra[4], only those faults which will change the value of B,but not change the value of A, will complement theoutput true value of G. Fault 5 is the only fault thatsatisfies this criterion and, therefore, is detected at theoutput of G. Fault 1 will change B to 1, but will alsochange A to 0 so that the faulty output remains logical 1.

Fault 1 is, thus, not detected at the output of G. Deductivesimulation requires only one pass to simulate all thefaults in a circuit if there is sufficient storage to hold thefault lists.

C. Parallel Versus Deductive Simulators

Both the parallel and the deductive simulators discussedhere have the same basic structure [6]. For each simulator,the time spent in calculating the next state of the circuitis divided into two components. One component cal-culates the new output of a gate from its given inputs(as explained in the previous sections). The second com-

ponent includes scheduling of gate output calculations,updating the new state of the circuit, and resolvingoscillation conditions and flip-flop races. The latter com-

ponent is essentially the same for both simulators al-though in some instances routines were coded differentlyto accommodate the differences in fault storage for paralleland deductive simulation.

Given the number of faults simulated per pass andthe number of inputs on a gate, the time to calculate a

gate's output value is fixed for a parallel simulation.However, the time depends on the speed of the particularinstructions used for the logical operations. For example,in the case of IBM 360/370 machines [7], if the numberof faults simulated in one pass is small, then register-to-register (RR) and register-to-storage (RS) operationsare used. If the number of faults to be simulated per

pass is such that the slower storage-to-storage (SS)instructions are required, this will increase the CPU timeper gate calculation.Two parallel simulators were available for this study.

One simulates up to a maximum of 2048 faults per pass

using the SS instructions. With this implementation thefault word is only large enough to accommodate thenumber of simulated faults (rounded up to the nearestmultiple of 8 and with a maximum of 2048 faults). Thusif 123 faults are simulated, the simulator uses a 128-bit

(16 bytes) fault word and executes the SS instructionsover 16 bytes. This is the principal parallel simulatorused in this comparison and is referred to as the 2048-faultsimulator. The second parallel simulator available usesthe faster RX and RR instructions but simulates only amaximum of 64 faults per pass. With this simulator thefault word is always 8-bytes wide. The simulator is referredto as the 64-fault simulator.

For a deductive simulator the time required to cal-culate a gate's output depends on the number of faultsin the fault lists on its inputs. The length of the faultlists is a function of the circuit topology,, the fault set,and the test vectors. This relationship will be discussedin Section III-A.The basic table sizes, excluding fault storage and the

size of the simulator programs themselves, are nearlyidentical; the difference in core requirements for the twosimulators is due to the fault storage. For a 2048-faultparallel simulator, the maximum fault storage needed fora gate depends only on the number of faults simulatedduring a pass. Thus, if 128 faults are simulated per pass,128 bits or 16 bytes of storage are needed for each gate.For a deductive simulator, the fault list for a gate containsone entry for the length plus one entry per fault detectableat that gate's output. The length of these lists varieswidely requiring dynamic storage allocation for the faultlists.

Conceptually, the fault numbers in the deductivesimulator's fault list record the position in the parallelsimulator's fault word of those bits (faults) which comple-ment the true value. If the fault words are sparselypopulated (i.e., most of the faulted machines have thesame value as the good machine), the deductive techniqueprovides a saving in CPU time and fault storage. Asthe fault words become more densely populated theparallel technique requires less CPU time and faultstorage.

II. COMPARISON OF TECHNIQUES

The comparison of the parallel and the deductivesimulation techniques was performed using several actuallogic circuits ranging in size from 300 to 46 000 gates(NAND, AND, OR, etc.). The sample of circuits containsshift registers, sequencers and counters, memory units,and a processor, with complexity varying from combi-national to very tightly interconnected sequential circuits.These circuit types, along with corresponding statisticson size and complexity, are listed in Table I. Since theredoes not exist a convenient measure to indicate circuit"complexity," two ad hoc indices are used here. Oneis the number of flip-flops in a circuit. This is meantto indicate the "local sequentialness." The other indexis the ratio of the number of gates in the maximallystrongly connected (MSC) sets to the total number ofgates in the circuit. A maximally strongly connected setof gates is a maximum set of gates with the propertythat each gate in the set can reach, and be reached, byevery other gate in the set (see [8]). This ratio provides

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CHANG et al.: PARALLEL AND DEDUICTIVE FAULT SIMULATION METHODS

TABLE I

No. of Gates in MSC'sNo. of No. of Gates in

Circuit Gatesa Flip-Flops MSC's Total Gates

A) Serial-to-Parallel Converter 349 90 224 0.64B) Error Corrector 340 68 178 0.52C) Parallel-to-Serial Converter 387 78 184 0.47D) Decoder and Order Sequencer 311 15 82 0,26E) Dial Pulse Sequencer 336 22 112 0.33F) Decoder and Match Circuit 383 8 44 0.12G) Arithmetic Unit 6602 234 4378 0.66H) Core Store Unit II 9359 320 3517 0.37I) Core Store Unit I 2476 167 1182 0.48J) Processor 46 012 2149 b

a T'L NAND'S are used throughout. Average number of inputs per gate for the circuits listed is two.b Data not available.

a heuristic measure of the sequentialness of a circuit ona "global" basis.The input sequences in all simulation runs were gen-

erated by the diagnostic engineers. For the small circuits(< 500 gates) the tests were designed to exercise theentire circuit as thoroughly as possible and all faults inthe circuit were simulated. For the larger circuits, thetests were designed to exercise some portion of the circuitand the faults simulated were restricted to this portionof the circuit.

A. CPU Time ComparisonsThe total CPU time is one criterion for comparing the

parallel and deductive simulation techniques. The totalCPU time for a simulation can be broken into two factors:1) the CPU time per gate calculation and 2) the numberof gate calculations. The time per gate calculation, whichincludes the time required to compute either the out-put fault word or the fault list, schedule events in thesimulation, resolve flip-flop races, and inject faults intothe simulation, depends on the circuit topology, inputtests, and the fault set simulated. The number of gatecalculations for both parallel and deductive simulation isalso dependent on the circuit topology, input tests, andfault set simulated.To characterize the simulation time of the 2048-fault

parallel simulator, the simulator was used to simulatesome of the circuits listed in Table I using fault setsranging up to 2048 faults. For each simulation the totalCPU time Tp, the number of gate calculations Gp, andthe number of faults simulated F, were recorded. Theaverage CPU time per gate calculation tp = Tp/Gp, andthe number of faults simulated were plotted as shown inFig. 3. Some circuits 'were simulated using more thanone fault set and are recorded as multiple points on thefigure. From these data, for fault sets less than 2048,the time per gate calculation for the 2048-fault simulatorcan be approximated by

tp = 400 + 0.83F uss.All of the circuits shown in Table I were again simulatedto characterize the simulation time for a deductivesimulator. The computation time was found to be a

1200.

z0

4 1000-

4

w- 800-4-CDZ

CL -

a 600-

r

CD

w4 400-

200-

8 fEA

EB/

BAI

D

200 460 600 800 1000 120NUMBER OF FAULTS SIMULATED, F

Fig. 3. Time per gate calculation, 2048-fault parallel simulator.

function of the average number of faults in the faultlists. These data were derived by running a faulted simula-tion and recording the CPU time Td, the total number ofgate calculations Gd, and the sum of the lengths of allthe fault lists on every excited gate L. This was donefor all the circuits listed in Table I. The average CPU timeper gate calculation td = Td/Gd and the average fault listlength, Lave = L/Gd were calculated and plotted asshown in Fig. 4. The result is a surprisingly linear rela-tionship described by the straight line

td = 300 + 3OLave j.

To compare the simulation times of the parallel andthe deductive simulators, for fault sets less than 2048,one can compare only the relative magnitudes of thetime per gate calculation. The number of gate calcula-tions performed by the two simulators is identical inthis case.The relative magnitude of the deductive time per

gate calculation, for a particular simulation depends onLave. Lavey in turn, depends on the circuit complexity,

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IEEE TRANSACTIONS ON COMPUTERS, NOVEMBER 1974

009-

I-0 0~~~~~~~~~~~~~~~~~~~

20 40 60 80 100 120 140

AVERAGE FAULT LIST LENGTH, LAVE

F;g. 4. Time per gate calculation, deductive siulator.

fault set, and test vectors. Large values of Lave are usually

found in highly complex circultry (i.e., circuitry with a

high ratio of the number of gates in MSC's to the total

number of gates) because a particular fault has a high

prbbability of "reaching" many gates in a MSC. Also,

the larger the fault set being simulated, the higher the

probability that a particular gate will have a nonempty

fault list, thereby yielding a larger overall Lave. These

two factors usually occur when small highly sequential

circultry is simulated.

WVhen more than 2048 faults are simulated, the parallel

simulator must make multiple passes through the test

vectors until all the faults are simulated. This increases

the number of gate calculations when compared to that

required by the deductive method. The reason for this

is that for each gate calculation the deductive simulator

considers the effect of all the simulated faults while

parallel considers the effect of only those faults simulated

on the particular pass. For comparison purposes, this

has the effect of increasing parallel's "effective average

time per gate calculation," where effective average time per

gate calculation is defined as tpe= Tv/Gd. The effective

time tpe will always be greater than 400 + 0.83F, how

much greater is difficult to predict.

For fault sets less than 2048, a break-evren average

fault list length can be calculated by setting the time per

gate calculation of the two techniques equal

td =tp

300)+ 3OLave = 400 + 0.83F

Lave = 3.3 + 0.027F.

Similarly, for fault sets greater than 2048

td = tp6 > tp

Lave > 3.3 + 0.027F.

Thus, given the number of number of faults, the average

fault list length

Lave = 3.3 + 0.027F

is a lower bound where the parallel technique becomes

more; efficient.

Fig. 5 is a scatter plot of the circuits listed in Table Iusing their average fault list length and number of faultssimulated. Superimposed on the data is the CPU time

break-even curve between the 2048-fault parallel anddeductive simulators. Table II characterizes a few of thesimulation points in Fig. 5, along with the simulationtimes of the deductive and 2048-fault parallel. Usingthe ratio of the number of gates in the MSC's to thenumber of gates in the circuit as a measure of sequential-ness, simulations of small and usually highly sequentialcircuits with a large percentage of faults simulated,(e.g., circuits A, B, C, and D) favored the parallel simu-lator. Deductive simulation is better for mildly sequentialcircuits (e.g., circuit F) and for large circuits having 2000or more gates since they generally have small averagefault list lengths.

In parallel simulation, the size of the fault word canhave an adverse effect on simulation CPUtime. In simulat-ing a given fault set, if a small fault-word size (e.g., 64 bit)is used, the number of passes increases. Consequently,the total number of gate calculations, and thus the totalCPU time also increases. As an illustration, CPU timesof several simulation runs using the 64-fault parallelsimulator are included in Table II.

B. Storage ConsiderationsOne of the problems in using any simulator is predicting

the amount of storage required for a simulation run.This is especially critical if software or hardware pagingis not available on the host computer and the entiresimulation resides in main memory. For both paralleland deductive simulators, the storage required by thetables which describe the circuit's topology is predictable.Between the two simulators the difference in storagerequirements is in the simulator's fault storage. Themaximum fault storage required for a parallel simula-tion is a function of the number of faults simulated perpass and is therefore well-defined before simulation. Fora deductive simulator, the fault list lengths vary fordifferent gates and for the same gate at different times.This variation necessitates the availability of a storagepool from which fault list storage can be allocated whenneeded. The size, use and maintenance of the storagepool depends on the particular storage allocation schemeused. The variations in fault list length make deter-mination of the storage pool's maximum size difficult.When paging (either hardware or software) techniques

are available, the "unlimited" slow speed storage canbe used, and predicting fault list storage becomes lesscirtical. With paging, it is still desirable to minimize thestorage requirements and have the simulation coreresident because the time required to page often dominatesthe time required to perform the actual computation.Paging has the advantage of allowing the available poolof fault list storage to be large enough so that temporarypeaks in storage requirements result in paging and notsimulation termination.For the simulators discussed here, the 2048-fault

parallel simulator uses a maximum of 1 byte per eightfaults simulated per gate for storing fault information.The deductive simulator requires 2 bytes per entry inthe fault list plus 2 bytes for the length of the fault list.Experience has shown that deductive simulation requires

1136

CHANG et at.: PARALLEL AND DEDUCTIVE FAULT SIMULATION METHODS

I

1000NUMBER OF FAULTS, F

Fig. a. Parallel-deductive CPU time break-even line.

TABLE IISIMULATION TIME FOR THREE SIMUIIATORS

Simulation CPU Time(seconds)

No. of No. ofFaults Vectors 2048-Fault 64-Fault

Circuit Simulated Simulated Deductive Parallel Parallel

A) Serial-to-Parallel Converter 572 427 433 180 321B) Error Corrector 894 412 642 201 313C) Parallel-to-Serial Converter 559 348 253 145 245D) Decoder and Order Sequencer 886 893 352 135 360E) Dial Pulse Sequencer 395 254 32 39 aF) Decoder and Match Circuit 1065 161 43 52 97G) Arithmetic Unit 2147 377 510 926 aH) Core Store Unit II 2582 200 8361 a aI) Core Store Unit I 2361 16 326 495 790J) Processor 9469 134 8673 a a

a Data not available.

at least twice this amount per fault list for efficient hand-ling of the storage pool. Using Lave as an indication ofstorage requirements, the break-even point between thetwo techniques is obtained by setting the storage per

gate equal for the two methods. For the number of faultsless than 2048

F/8 = (2Lave + 2)*2

Lave = F/32- 1 faults.

For more than 2048 simulated faults

Lave = 63 faults.

For the 64-bit parallel simulator 8 bytes per gate are

needed for storing fault information, yielding a break-even Lave of 1.

Fig. 6 superimposes the storage break-even line, on

the simulation scatter plot. Comparing the deductivesimulator with the 2048-fault parallel, deductive requiresless storage for large circuits (e.g., > 1000 gates), andfor some small mildly sequential circuits. But parallel'sstorage requirements can always be made less thandeductive's storage requirements by going to a smallermaximum fault word. Thus, considering only storagecosts, parallel simulation has an advantage over deductivesimulation. Finally, parallel simulation provides the

ability to predict the maximum total storage require-ments of a particular circuit given the number of gates in

the circuit.

IV. CONCLUSIONA comparison of the CPU time and storage require-

ments for the parallel and deductive fault simulationtechniques was performed by using several representativecircuits (ranging in size from 300 to 46 000 gates) thatare generally found in a computing system. The CPUtime comparison indicates the deductive technique isbetter for the simulation of a wide range of circuit sizesand complexities. The parallel technique is better onlyin simulating small (e.g., < 500 gates) highly sequentialcircuits. The storage requirement comparison indicatesthat a parallel simulator can be designed to use lessstorage than the deductive simulator.

If the storage is limited so that paging (hardware-assisted paging or software paging) becomes a considera-tion, one must weigh the time spent in paging overheadin comparing the two techniques. The tradeoff point ishighly dependent on the storage allocation scheme used.The technique to be used depends on the relative

importance of storage and CPU time for a particularapplication. If storage requirements are an overriding

I-

z

I-

C,w

41iAJ

I

B

5000

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a G

A

A CDD

BA CDC JI ~~~~~~J

1000 2000

2048- FLT PARALLELDEDUCTIVE

3000NUMBER OF FAULTS, F

Fig. 6. Parallel-deductive storage break-even line.

consideration and CPU time is unimportant, then theparallel technique will be more efficient. Where sufficientstorage is available, the deductive technique will bemore efficient for a wider range of circuits and fault sets.

REFERENCES[1] S. Seshu, "On an improved diagnosis program," IEEE Trans.

Electron. Comput. (Short Notes), vol. EC-14, pp. 76-79, Feb.1965.

[2] F. H. Hardie and R. J. Suhocki, "Design and use of fault simula-tion for saturn computer design," IEEE Trans. Electron. Comput.,vol. EC-16, pp. 412-429, Aug. 1967.

[3] S. A. Szvgenda, D. M. Rouse, and E. W. Thompson, "A modeland implementation of a universal time delay simulator for largedigital vets," in 1970 Spring Joint Comput. Conf., AFIPS Conf.Proc., vol. 36. Montvale, N. J.: AFIPS Press, pp. 207-216.

[4] D. B. Armstrong, "A deductive method for simulating faults inlogic circuits," TEEE Trans. Comput., vol. C-21, pp. 464-471,May 1972.

[5] H. Y. Chang, G. W. Smith, and R. B. Walford, "Lamp systemdescription," Bell. Syst. Tech. J., vol. 53, Oct. 1974.

[6] S. G. Chappell, C. H. Elmendorf, and L. D. Schmidt, "Lamplogic simulators," BeU Sy8t. Tech. J., vol. 53, Oct. 1974.

[7] International Business Machines Corporation, "IBM system/360principles of operation," IBM Syst. Ref. Library, Form A22-6821-6.

[8] C. V. Ramamoorthy, "Analysis of graphs by connectivity con-

siderations," J. Ass. Comput. Mach., vol. 13, pp. 211-222, Apr.1966.

Herbert Yu-Pang Chang (S'62-M'65-SM'74)received the B.S., M.S., and Ph.D. degreesin electrical engineering from the Universityof Ilinois, Urbana, in 1960, 1962, and 1964,respectively.

Since 1964 he has been employed by BellLaboratories, Inc., Naperville, Ill., where he

is presently a Supervisor in the AdvancedSwitching Technology Laboratory respon-sible for the development of design automa-tion systems for electronic switching systems.

His work has dealt primarily with the automatic maintenance tech-niques of large-scale real-time switching systems, design techniquesforself-checking processors, and computer fault-simulation tech-^^.He has published a number of papers in these areas andci5whore d the book, Fault Diagnosis of Digital Systems (NewYo'rk: Wliey-Interscience, 1970).

Pr. Chang is a member of Eta Kappa Nu, Tau Beta Pi, andSigma Xi.

Stephen G. Chappell (M'71) received the

tB.E.E. degree from the Georgia Instituteof Technology, Atlanta, in 1969, and the

| M.S. and Ph.D. degrees from Northwestern

l University, Evanston, Ill., in 1971 and 1973,respectively.

| _ Since 1969 he has been employed by BellLaboratories, Inc., Naperville, Ill., where he

presently Supervisor of the Advanced

Logic Design Automation Group. He is re-

sponsible for the development of design auto-mation systems for electronic switching systems. His work hasdealt primarily with fault simulation and automatic test generationfor large digital circuits.

Dr. Chappell is a member of Eta Kappa Nu and Tau Beta Pi.

Charles H. Elmendorf received the B.S.degree in engineering physics from CornellUniversity, Ithaca, N. Y., in 1969 and the

M.S. degree in electrical engineering fromNorthwestern University, Evanston, Ill., in

_ _ _ ~~~~1971.Since 1969, he has been employed by Bell

Laboratories, Inc., Naperville, Illinois, wherehe is involved in the design of processor

operating systems and their support soft-ware. His work has dealt with the design

and implementation of software systems for automatic routing andinteractive logic verification and fault simulation.

Mr. Elmendorf is a member of Tau Beta Pi.

Lonnie D. Schmidt received the B.S. degreein computer science from the University ofMissouri at Rolla, Rolla, in 1969 and the

M.S. degree, also in computer science, from

_ Northwestern University, Evanston, III. iny g g _ ~~~1971.

From 1969 to 1973 he was with Bell Labo-ratories, Inc., Naperville, Ill. During this

time he worked on large-scale interactivelogic fault simulators. Since 1973 he hasbeen with McDonnell Douglas Automation

Company in St. Louis, Mo., where he is working with a graphicssystem in computer aided design. His other interests include com-puter aided instruction systems, time-sharing systems, performanceevaluation and virtual memory systems.Mr. Schmidt is a member of the Association of Computing

Machinery, Kappa Mu Epsilon and Phi Kappa Phi.

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