Compal La-3151p Hcw50 Schematics

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Compal ConfidentialHCW50 Schematics DocumentAMD/Sempron/ATI RX485/SB460 W/s M52/54/56P 2006 / 02 / 28 Rev:0.3 (For PVT)

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Security Classification Issued Date 2005/05/09

Compal Secret DataDeciphered Date 2006/03/08Title

Compal Electronics, inc.SCHEMATIC, M/B LA-3151PRev B SheetE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C D

Size Document Number Custom 401412 Date: , 09, 2006 1 of 55

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Compal confidentialProject Code: HCW50 File Name : LA-3151PD

Thermal Sensor ADM1032ARMpage 7

Clock Generator ICS951462page 15

AMD Turion/Sempron CPU Socket S1 638Ppage 5,6,7,8 H_A#(3..31) H_D#(0..63) HT 16x16 800MHZ

DDRIIDual Channel DDR-II

DDRII-SO-DIMM X2page 9,10

D

DVI-D Conn.page 30

LCD CONNpage 29

CRT & TV-OUTpage 28

ATI-RX485M465 BGApage 11,12,13,14

A-Link Express PCI-ExpressATI M52PG/M54P/M56P2 x PCIE

with 64/128/256MB VRAMC

USB 2.0

USB conn x 2 / New cardpage 39C

page 16,17,18,19,20,21

ATI-SB460PCI BUS Realtek RTL8100CL RTL8110SCLpage 31

USB 2.0

BT Conn

page 34

549 BGAAC-LINKpage 22,23,24,25,26

Audio CKT ALC883page 44

AMP & Audio Jackpage 45

Mini PCI Socket Mini card / CAMpage 36

ENE ControllerCB714page 37

1394 Controller VT6311Spage 40

MDC Conn.

page 34

SATA

SATA HDD Conn.page 27

RJ45 CONNB

Slot 0page 38

page 32

6in1 CardReader page 38 Slot

1394 Conn.

LPC BUS

page 40

B

PATA One Channel HDD Conn. CDROM Conn.page 27

Power On/Off CKT / LID switch / Power OK CKTpage 42

SMsC LPC47N207CIR/LEDpage 43

ENE KB910page 33

DC/DC Interface CKT.page 46

RTC CKT.page 22

page 41

Power Circuit DC/DCpage 46~

FIR modulepage 41

Int. KBDpage 34

Touch Pad CONN.page 34

BIOSpage 35A

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Compal Electronics, inc.SCHEMATIC, M/B LA-3151PR ev B Sheet1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2


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STATE

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# HIGH LOW LOW LOW LOW HIGH HIGH LOW LOW LOW HIGH HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH LOW

+VALW ON ON ON ON ON

+V ON ON ON OFF OFF

+VS ON ON OFF OFF OFF

Clock ON LOW OFFD

Voltage RailsPower Plane VIND

Full ONDescription Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU 0.9V switched power rail for DDRII terminator 1.2V switched power rail 1.5V switched power rail 1.8V power rail for DDRII 1.8V switched power rail 2.5V switched power rail 3.3V always on power rail 3.3V switched power rail 5V always on power rail 5V switched power rail VSB always on power rail RTC power 1.2V switched power rail for PCIE 0.9V switched power rail for VRAM terminator 1.8V switched power rail 1.0~1.2V switched power rail for VGA S0 N/A N/A ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON S3 N/A N/A OFF ON OFF OFF ON OFF OFF ON OFF ON OFF ON ON OFF OFF ON OFF S5 N/A N/A OFF OFF OFF OFF OFF OFF OFF ON* OFF ON* OFF ON* ON* OFF OFF ON* OFF

S1(Power On Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)

B+ +CPU_CORE +0.9V +1.2V_HT +1.5VS +1.8V +1.8VS +2.5VS +3VALW +3VS +5VALW +5VS +VSB +RTCVCC +1.2VS

OFF OFF

Board ID / SKU ID Table for AD channelVcc Ra/Rc/ReBoard ID

C

+0.9VS +1.8VALW +VDD_CORE

0 1 2 3 4 5 6 7

3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC

V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V

V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V

V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V

C

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOARD ID TableBoard ID 0 1 2 3 4 5 6 7 PCB Revision 0.1

BTO Option TableBTO Item VGA UMA UMA's DVI LAN(10/100) LAN(GIGA) MINI CARD1 MINI CARD2 SATA-to-IDE PATA GRAPEVINE G72MV Only G73 Only VRAM VRAM 64M VRAM 128M VRAM 256M MEDIA/B CIR FIR GENEVA LCM Sub-woofer BOM Structure

External PCI DevicesDevice Ca rdBus(SD) 1 394 LAN(10/100) IDSEL#AD20 AD16 AD17

REQ#/GNT#2 0 3 1

Interrupts PIRQE/PIRQH PIRQE PIRQF PIRQG/PORQH

Mini-PCI(WLAN/TV-Tuner) AD18

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B

EC SM Bus1 addressDeviceSmart Battery EEPROM(24C16/02) GMT G781-1

EC SM Bus2 addressDeviceFintek F75383M

SKU ID TableSKU ID 0 1 2 3 4 5 6 7 SKU PM GM

Address0001 011X b 1010 000X b 1001 101X b

Address1001 100X b

SB460 SM Bus addressDeviceClock Generator (ICS9LPRS325AKLFT_MLF72)A

Address1101 001Xb 1001 000Xb 1001 010Xb

DDR DIMM0 DDR DIMM2

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+5V +3.3VALW_NTBBATTERY

1.5V SW REGULATOR

CPU_VDDA_RUN (S0, S1) AMD CPU VCCA 2.5V CPU_VDD_RUN (S0, S1)

+3.3VSUS_NTBBATTERY CHARGER

+VIN +5V +VIN +5V +3.3V_NTBSWITCH VLDT 1.2V SW REGULATOR NB CORE SW REGULATOR PCIE&SB SW REGULATOR 1.8V SW REGULATOR SW REGULATOR

+VDC

MAIN PWR SW REGULATOR

+5VALW_NTB +5VSUS_NTB

VDDCORE 0.375-1.500V 30A VLDT 1.2V 3AD

VLDT_RUN (S0, S1)

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NB RS485HT VLDT 1.2V 1A NB CORE 10A PCI-E CORE &PCI-E IO 3.5A HTPLL (1.8V) 200mA PLL & DAC-Q(1.8V) 200mA TRANSFORMER 400mA DAC 300mA

SWITCH

POWER SWITCH

CPU PWR 12V +/-5%

+3.3VALW

+VIN +5V

+5V_NTB

VCC_NB (S0, S1)

12V +/-5%

SW

+VIN_MEM +5VSUS +5VALW_ATXSW

+3.3VSUS

+VIN +5V

VDDA_1V2(S0, S1)

+3.3V +5V +5VALW +3.3V +1.8V(S0, S1) AVDD (S0, S1)

ATX POWER SUPPLY

5VSB +/-5%

+5VDUAL_ATX +5V_ATX +5VSUS +VIN +5V +5VSUS1.8V VDD&VTT SW REGULATOR

5V +/-5%

DDRII SODIMMX2 CPU_VDDIO_SUS (S0, S1, S3)VDD MEM 4A

+3.3VALW LDO REGULATOR SW

+3.3VALW_ATX +3.3VDUAL_ATX +3.3V_ATX

3.3V +/-5%

CPU_VTT_SUS (S0, S1,S3) VCC_SB (S0, S1)VTT_MEM 0.5AC

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-12V +/-5%

SB SB600X4 PCI-E 0.8A ATA I/O 0.2A ATA PLL 0.01A PCI-E PVDD 80mA SB CORE 0.6A

CONTROL SIGNAL: MOBILE: BATTERY DESKTOP: ATX

+3.3VALW +3.3V +3.3VALW +5V

1.2V LDO REGULATOR

+1.2VALW

1.2V S5 PW 0.22A 3.3V I/O 0.45A 3.3V S5 PW 0.01A USB CORE I/O 0.2A

MINI PCI SLOT +3.3VB

GBIT ENTHENET3.3V 0.5A (S0, S1, S3, S4, S5)B

3.3V(S0, S1)1.5A 5V (S0, S1) 0.1A 3.3V(S3, S5) 0.2A

+5V +3.3VALW +VIN

PCI-E CARD1.5V (S0, S1) 0.7A 3.3V (S3, S5) 0.3A

+3.3V +5V PCI Slot (per slot) 5V 3.3V 12V 3.3Vaux -12VA

3.3V (S0, S1) 1.3A

X1 PCIE per 3.3V 12V 3.0A 0.5A

X16 PCIE 3.3V 12V 3.0A 5.5A

CNR CONNECTOR 5V 3.3V 12V 3.3Vaux -12V 5VDual 1.0A 1.0A 0.5A 1.0A 0.1A 0.5A

+5VALW

SUPER I/O+3.3VDUAL (S3) 0.01A +3.3V (S0, S1) 0.01A +5V (S0, S1) 0.1A

5.0A 7.6A 0.5A 0.375A 0.1A

USB X7 FR VDD 5VDual 3.5A

USB X2 RL VDD 5VDual 1.0A

2XPS/2 5VDual 1.0A

3.3Vaux 0.1A

HD CODEC3.3V CORE 0.3A 5V ANALOG 0.1AA






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H_CADIP[0..15] H_CADIN[0..15]


H_CADOP[0..15] H_CADON[0..15]


PROCESSOR HYPERTRANSPORT INTERFACED

VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

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+1.2V_HT JP72A D4 D3 D2 D1 H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0 H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 H_CTLIP1 H_CTLIN1 H_CTLIP0 H_CTLIN0 N5 P5 M3 M4 L5 M5 K3 K4 H3 H4 G5 H5 F3 F4 E5 F5 N3 N2 L1 M1 L3 L2 J1 K1 G1 H1 G3 G2 E1 F1 E3 E2 J5 K5 J3 J2 P3 P4 N1 P1 VLDT_A3 VLDT_A2 VLDT_A1 VLDT_A0 L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0 VLDT_B3 VLDT_B2 VLDT_B1 VLDT_B0 L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 L0_CTLOUT_H0 L0_CTLOUT_L0 AE5 AE4 AE3 AE2 T4 T3 V5 U5 V4 V3 Y5 W5 AB5 AA5 AB4 AB3 AD5 AC5 AD4 AD3 T1 R1 U2 U3 V1 U1 W2 W3 AA2 AA3 AB1 AA1 AC2 AC3 AD1 AC1 Y4 Y3 Y1 W1 T5 R5 R2 R3 H_CTLOP0 H_CTLON0 H_CTLOP0 H_CTLON0 1 2 C1 4.7U_0805_10V4Z +5VS C2 1 H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0 U2 +VCC_FAN1 EN_DFAN1 1 2 3 4 VEN VIN VO VSET GND GND GND GND

FAN1 Conn10U_0805_10V4Z 2 +5VS 1 8 7 6 5 D1 1SS355_SOD323 D2 1N4148_SOT23 1 2 C3 10U_0805_10V4Z 1 2 +3VS 1 C4 1000P_0402_50V7K 1 2C

EN_DFAN1

G993P1UF_SOP8

HTT Interfa ce

C

R1 10K_0402_5%

40mil2 +VCC_FAN1 FAN_SPEED1 1 C5 1000P_0402_50V7K

2

JP73 1 2 3 ACES_85205-03001

2

+1.2V_HT R2 1 R3 1

2 51_0402_1% 2 51_0402_1% H_CTLIP0 H_CTLIN0

B

Athlon 64 S1 Processor Socket

B

+1.2V_HT

1

C6 10U_0805_10V4Z

C8

1

C9

1

C10

1

C11

1 180P_0402_50V8J

2

2 2 2 0.22U_0603_10V7K 180P_0402_50V8J 0.22U_0603_10V7K

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LAYOUT: Place bypass cap on topside of boardA

NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY TO OTHER HT POWER PINS PLACE CLOSE TO VLDT0 POWER PINS

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B

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DDR_A_MA[0..15]

DDR_A_MA[0..15] DDR_B_DQS[0..7] DDR_B_DQS#[0..7] DDR_B_D[0..63]

Processor DDR2 Memory InterfaceJP72C DDR_B_D63 DDR_B_D62 DDR_B_D61 DDR_B_D60 DDR_B_D59 DDR_B_D58 DDR_B_D57 DDR_B_D56 DDR_B_D55 DDR_B_D54 DDR_B_D53 DDR_B_D52 DDR_B_D51 DDR_B_D50 DDR_B_D49 DDR_B_D48 DDR_B_D47 DDR_B_D46 DDR_B_D45 DDR_B_D44 DDR_B_D43 DDR_B_D42 DDR_B_D41 DDR_B_D40 DDR_B_D39 DDR_B_D38 DDR_B_D37 DDR_B_D36 DDR_B_D35 DDR_B_D34 DDR_B_D33 DDR_B_D32 DDR_B_D31 DDR_B_D30 DDR_B_D29 DDR_B_D28 DDR_B_D27 DDR_B_D26 DDR_B_D25 DDR_B_D24 DDR_B_D23 DDR_B_D22 DDR_B_D21 DDR_B_D20 DDR_B_D19 DDR_B_D18 DDR_B_D17 DDR_B_D16 DDR_B_D15 DDR_B_D14 DDR_B_D13 DDR_B_D12 DDR_B_D11 DDR_B_D10 DDR_B_D9 DDR_B_D8 DDR_B_D7 DDR_B_D6 DDR_B_D5 DDR_B_D4 DDR_B_D3 DDR_B_D2 DDR_B_D1 DDR_B_D0 DDR_B_DM7 DDR_B_DM6 DDR_B_DM5 DDR_B_DM4 DDR_B_DM3 DDR_B_DM2 DDR_B_DM1 DDR_B_DM0 DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0 AD11 AF11 AF14 AE14 Y11 AB11 AC12 AF13 AF15 AF16 AC18 AF19 AD14 AC14 AE18 AD18 AD20 AC20 AF23 AF24 AF20 AE20 AD22 AC22 AE25 AD26 AA25 AA26 AE24 AD24 AA23 AA24 G24 G23 D26 C26 G26 G25 E24 E23 C24 B24 C20 B20 C25 D24 A21 D20 D18 C18 D14 C14 A20 A19 A16 A15 A13 D12 E11 G11 B14 A14 A11 C11 AD12 AC16 AE22 AB26 E25 A22 B16 A12 AF12 AE12 AE16 AD16 AF21 AF22 AC25 AC26 F26 E26 A24 A23 D16 C16 C12 B12 MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10 MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0 MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0 MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0 MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10 MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0 MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0 MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0 DDR: DATAAthlon 64 S1 Processor Socket

DDR_A_DQS[0..7] DDR_A_DQS#[0..7] DDR_A_D[0..63]

DDR_A_DQS[0..7] DDR_A_DQS#[0..7]

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

DDR_B_DQS[0..7] DDR_B_DQS#[0..7]

+1.8V +0.9VREF_CPU4

JP72B 1 W17 R4 39.2_0402_1%~D 2 M_ZN M_ZP R5 39.2_0402_1%~D DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# V19 J22 V22 T19 MA0_CS_L3 MA0_CS_L2 MA0_CS_L1 MA0_CS_L0 MB0_CS_L3 MB0_CS_L2 MB0_CS_L1 MB0_CS_L0 MB_CKE1 MB_CKE0 MA_CKE1 MA_CKE0 MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0 MA_BANK2 MA_BANK1 MA_BANK0 MA_RAS_L MA_CAS_L MA_WE_L Athlon 64 S1 Processor Socket Y10 AE10 AF10 M_VREF VTT_SENSE M_ZN M_ZP VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 MA0_CLK_H2 MA0_CLK_L2 MA0_CLK_H1 MA0_CLK_L1 MB0_CLK_H2 MB0_CLK_L2 MB0_CLK_H1 MB0_CLK_L1 MB0_ODT1 MB0_ODT0 MA0_ODT1 MA0_ODT0 MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10 MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0 MB_BANK2 MB_BANK1 MB_BANK0 MB_RAS_L MB_CAS_L MB_WE_L D10 C10 B10 AD10 W10 AC10 AB10 AA10 A10 Y16 AA16 E16 F16

+0.9V

2

DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1

DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_ODT1 DDR_B_ODT0 DDR_A_ODT1 DDR_A_ODT0 DDR_B_MA[0..15]

PLACE THEM CLOSE TO DDR_CS0_DIMMB# CPU WITHIN 1" DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA

DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB#

DDR_CS3_DIMMB# Y26 DDR_CS2_DIMMB# J24 DDR_CS1_DIMMB# W24 DDR_CS0_DIMMB# U23 DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0 H26 J23 J20 J21 K19 K20 V24 K24 L20 R19 L19 L22 L21 M19 M20 M24 M22 N22 N21 R21 K22 R20 T22 T20 U20 U21

AF18 DDR_B_CLK2 AF17 DDR_B_CLK#2 A17 DDR_B_CLK1 A18 DDR_B_CLK#1 W23 W26 V20 U19 J25 J26 W25 L23 L25 U25 L24 M26 L26 N23 N24 N25 N26 P24 P26 T24 DDR_B_ODT1 DDR_B_ODT0 DDR_A_ODT1 DDR_A_ODT0 DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0

3

DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

K26 DDR_B_BS#2 T26 DDR_B_BS#1 U26 DDR_B_BS#0 U24 DDR_B_RAS# V26 DDR_B_CAS# U22 DDR_B_WE#

DDR_B_BS#2 DDR_B_BS#1 DDR_B_BS#0 DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

AA12 AB12 AA14 AB14 W11 Y12 AD13 AB13 AD15 AB15 AB17 Y17 Y14 W14 W16 AD17 Y18 AD19 AD21 AB21 AB18 AA18 AA20 Y20 AA22 Y22 W21 W22 AA21 AB22 AB24 Y24 H22 H20 E22 E21 J19 H24 F22 F20 C23 B22 F18 E18 E20 D22 C19 G18 G17 C17 F14 E14 H17 E17 E15 H15 E13 C13 H12 H11 G14 H14 F12 G12 Y13 AB16 Y19 AC24 F24 E19 C15 E12 W12 W13 Y15 W15 AB19 AB20 AD23 AC23 G22 G21 C22 C21 G16 G15 G13 H13

DDR_A_D63 DDR_A_D62 DDR_A_D61 DDR_A_D60 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D55 DDR_A_D54 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D49 DDR_A_D48 DDR_A_D47 DDR_A_D46 DDR_A_D45 DDR_A_D44 DDR_A_D43 DDR_A_D42 DDR_A_D41 DDR_A_D40 DDR_A_D39 DDR_A_D38 DDR_A_D37 DDR_A_D36 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D32 DDR_A_D31 DDR_A_D30 DDR_A_D29 DDR_A_D28 DDR_A_D27 DDR_A_D26 DDR_A_D25 DDR_A_D24 DDR_A_D23 DDR_A_D22 DDR_A_D21 DDR_A_D20 DDR_A_D19 DDR_A_D18 DDR_A_D17 DDR_A_D16 DDR_A_D15 DDR_A_D14 DDR_A_D13 DDR_A_D12 DDR_A_D11 DDR_A_D10 DDR_A_D9 DDR_A_D8 DDR_A_D7 DDR_A_D6 DDR_A_D5 DDR_A_D4 DDR_A_D3 DDR_A_D2 DDR_A_D1 DDR_A_D0 DDR_A_DM7 DDR_A_DM6 DDR_A_DM5 DDR_A_DM4 DDR_A_DM3 DDR_A_DM2 DDR_A_DM1 DDR_A_DM0 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0

4

DDRII Cmd/Ctrl//Clk

1

To reverse SODIMM socket

To normal SODIMM socket

DD RII Data

3

DDR_B_DM[0..7]

DDR_A_DM[0..7]

DDR_A_CLK2 1 C12 1.5P_0402_50V8C

DDR_B_CLK2 1 C13 1.5P_0402_50V8C

DDR_A_CLK#2 DDR_A_CLK1

2

DDR_B_CLK#2 DDR_B_CLK1

2

1 C14 1.5P_0402_50V8C DDR_B_CLK#1

1 C15 1.5P_0402_50V8C

DDR_A_CLK#1

2

2

2

PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH

PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH

2

ATI check ,Use +0.9V PWR , can delete or not

A1+1.8V

A26

Athlon 64 S1g1+0.9VREF_CPU

R6 1K_0402_1% 2 +0.9VREF_CPU 1 1 C16 C18 0.1U_0402_16V4Z 1 1 C19 1 C20 1U_0402_6.3V4Z

1

uPGA638 Top View

1

R7 1K_0402_1% 2 2 1000P_0402_50V7K 2 2 2

AF1

1

1000P_0402_50V7K

VDD_VREF_SUS_CPU

LAYOUT:PLACE CLOSE TO CPU



Compal Electronics, inc.SCHEMATIC, M/B LA-3151PRev B SheetE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C D


5

4

3

2

1

ATHLON Control and DebugLAYOUT: ROUTE VDDA TRACE APPROX. 50 mils WIDE (USE 2x25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.+2.5VS L1 2 1 1 +VDDA_25V C22 1 C23 1 C24 3300P_0402_50V7K CPU_HT_RESET# CPU_ALL_PWROK CPU_LDTSTOP# R10 1 2 300_0402_5% 1 1 2 44.2_0603_1% 2 44.2_0603_1% CPU_SIC_R CPU_HTREF1 CPU_HTREF0 CPU_VCC_SENSE CPU_VSS_SENSE PAD PAD C26 1 2 R14 300_0402_5% 2 4.7K_0402_5% U49 @ 2 B 1 A 5 2 0.1U_0402_16V4Z Y G 3 4 CPU_ALL_PWROK CPUCLK# NC7SZ08P5X_NL_SC70-5 C27 1 2 3900P_0402_50V7K CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 PAD PAD PAD PAD PAD CPU_LDTSTOP# CPU_THERMDC CPU_THERMDA PAD PAD T28 T30 PAD PAD T13 T15 T17 T19 T20 T23 T25 E9 E8 G9 H10 AA7 C2 D7 E7 F7 C7 AC8 C3 AA6 W7 W8 Y6 AB6 P20 P19 N20 N19 CPUCLK C25 1 2 1 T1 T2 VDDIOFB_H VDDIOFB_L FBM-L11-321611-260-LMT_1206

+1.8V

1

R8 300_0402_5% 2 F8 F9 B7 A7 F10 AF4 AF5 P6 R6 F6 E6 W9 Y9 A9 A8 G10 AA9 AC9 AD9 AF9 VDDA2 VDDA1 RESET_L PWROK LDTSTOP_L SIC SID HTREF1 HTREF0 VDD_FB_H VDD_FB_L VDDIO_FB_H VDDIO_FB_L CLKIN_H CLKIN_L DBRDY TMS TCK TRST_L TDI TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9 TEST17 TEST16 TEST15 TEST14 TEST12 TEST7 TEST6 THERMDC THERMDA TEST3 TEST2 RSVD0 RSVD1 RSVD2 RSVD3 DBREQ_L TDO E10 AE9 CPU_DBREQ# CPU_TDO VID5 VID4 VID3 VID2 VID1 VID0 CPU_PRESENT_L PSI_L THERMTRIP_L PROCHOT_L AF6 H_THERMTRIP_S# AC7 CPU_PROCHOT#_1.8 2 JP72D

1 R9 300_0402_5%

50mil width(600mA)

D

2 4.7U_0805_10V4Z

2

2 0.22U_0603_10V7K

SB460 ONLY

+1.2V_HT

R12 R13

A5 C6 A6 A4 C5 B5 AC6 A3

VID5 VID4 VID3 VID2 VID1 VID0 CPU_PRESENT# PSI# PSI#

VID5 VID4 VID3 VID2 VID1 VID0

D

place them to CPU within 1"+3VS 1 +1.8VS 1 +1.8V

CPU_VCC_SENSE CPU_VSS_SENSE

R15

CPU_CLKIN_SC_P CPU_CLKIN_SC_N C PU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI

3900P_0402_50V7K R16 169_0402_1%

P

2

CPU_PWRGD

Place within 0.5" from CPU 25mil/6mil/6mil/6mil/25mil CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N R17 1 2 80.6_0402_1%

TEST29_H TEST29_L

C9 C8

+1.8VS +1.8V 1 C28 1 R18 300_0402_5% 2 2C

MISC

R806 1

2 @ 0_0402_5%

ROUTE AS 80 Ohm DIFFERENTIAL PAIR PLACE IT CLOSE TO CPU WITHIN 1"

2

U50 B A

0.1U_0402_16V4Z Y 4

P

TEST24 TEST23 TEST22 TEST21 TEST20 TEST28_H TEST28_L TEST27 TEST26 TEST10 TEST8 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20

AE7 AD7 AE8 AB8 AF7 J7 H8 AF8 AE6 K8 C4 H16 B18 B3 C1 H6 G6 D5 R24 W18 R23 AA8 H18 H19

5

T14 PAD T16 PAD T18 PAD CPU_TEST21_SCANEN T21 PAD T24 PAD T26 PAD T27 PAD CPU_TEST26_BURNIN# T29 PAD T31 PAD

G

LDT_STOP#

1

C

3

NC7SZ08P5X_NL_SC70-5

Modify 11/22R807 1 +1.8VS 1 +1.8V C29 1 2 U51 2 1 B A 5 2 R844 @ 10K_0402_5% 2 CPU_HT_RESET# Q47 NC7SZ08P5X_NL_SC70-5 LDT_RST# E 0.1U_0402_16V4Z Y G 3 4 2 @ 0_0402_5% +1.8VS +3VS 1 R845 @ 4.7K_0402_5% 2

R19 300_0402_5% R804 1 0_0402_5% SB_PWROK_R

1

SB_PWRGD

2

LDT_RST#

R26 R25 P22 R22

P

RSVD4 RSVD5 RSVD6 RSVD7

2

3 1 @ MMBT3904_SOT23 C

B

3V_LDT_RST#AMD NPT S1 SOCKET Processor Socket

R808 1 +1.8V R24 1@ 220_0402_5% R25 1@ 220_0402_5% R26 1@ 220_0402_5% R27 1@ 220_0402_5% R28 1@ 220_0402_5%

2 @ 0_0402_5%

+1.8V

R20 1 +1.8V JP74 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 26 300_0402_5% 2 Q1 3 1H_THERMTRIP# MMBT3904_SOT23 H_THERMTRIP_S# 1K_0402_5% 2 R22 1 R23 10K_0402_5% 2

1 R21 @ 1K_0402_5%B

HDT Connector

+3VALW +1.8V 1 +3VALW

B

2 2

2

1 R30 4.7K_0402_5% 2

3V_LDT_RST#

NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.

@ SAMTEC_ASP-68200-07

Q3 E CPU_TEST26_BURNIN# R32 1 1 1 2 300_0402_5% 2 1K_0402_5% 2 510_0402_5% CPU_PROCHOT#_1.8

3 1 MMBT3904_SOT23 C

2

+1.8V

CPU_PH_G 2

CPU_DBREQ# C PU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO

3

Q2 @ MMBT3904_SOT23 1 MAINPWON R29 10K_0402_5%

2

2

2

2

2

+1.8V 1

H_THERMTRIP#

+3VS

B

EC_THERM#

CPU_PRESENT# R33 CPU_TEST25_H_BYPASSCLK_H R34 +3VS C30 0.1U_0402_16V4Z 1 2

C31 2200P_0402_50V7KA

1 1 2 CPU_THERMDA CPU_THERMDC 2 3 4

U4 VDD D+ DTHERM# SCLK SDATA ALERT# GND 8 7 6 5 EC_SMB_CK2 EC_SMB_DA2

CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 CPU_TEST21_SCANEN

R42 R43 R44 R35

1 1 1 1

2 2 2 2

510_0402_5% 300_0402_5% 300_0402_5% 300_0402_5%A

ADM1032ARMZ-2REEL_MSOP8 F75383M_MSOP8

SMBus Address: 1001110X (b)


Compal Secret DataDeciphered Date 2006/03/08Title Size C Date:

Compal Electronics, inc.SCHEMATIC, M/B LA-3151PDocument Number


401412, 09, 20061

Rev B Sheet 7 of 55

5

4

3

2

1

D

D

BOTTOMSIDE DECOUPLING+CPU_CORE

1 JP72F +CPU_CORE JP72E AC4 VDD1 AD2 VDD2 G4 VDD3 H2 VDD4 J9 VDD5 J11 VDD6 J13 VDD7 K6 VDD8 K10 VDD9 K12 VDD10 K14 VDD11 L4 VDD12 L7 VDD13 L9 VDD14 L11 VDD15 L13 VDD16 M2 VDD17 M6 VDD18 M8 VDD19 M10 VDD20 N7 VDD21 N9 VDD22 N11 VDD23 P8 VDD24 P10 VDD25 R4 VDD26 R7 VDD27 R9 VDD28 R11 VDD29 T2 VDD30 T6 VDD31 T8 VDD32 T10 VDD33 T12 VDD34 T14 VDD35 U7 VDD36 U9 VDD37 U11 VDD38 U13 VDD39 V6 VDD40 V8 VDD41 V10 VDD42 +CPU_CORE VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 V12 V14 W4 Y2 J15 K16 L15 M16 P16 T16 U15 V16 H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 P18 P21 P23 P25 R17 T18 T21 T23 T25 U17 V18 V21 V23 V25 Y25 AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 M11 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6

C32 10U_0805_10V4Z

1

C33 10U_0805_10V4Z

1

C34 10U_0805_10V4Z

1

C35 10U_0805_10V4Z

1

C36 10U_0805_10V4Z

1

C37 22U_0805_6.3V6M

1

C38 22U_0805_6.3V6M

1

C39 22U_0805_6.3V6M

1

C40 22U_0805_6.3V6M

2

2

2

2

2

2

2

2

2

+CPU_CORE

+1.8V

1

C41 0.22U_0603_10V7K

1

C42 0.22U_0603_10V7K

1

C43 0.22U_0603_10V7K

1

C44 0.22U_0603_10V7K

1 C45 22U_0805_6.3V6M

1 C46 22U_0805_6.3V6M

1

C47 0.22U_0603_10V7K

1

C48 0.22U_0603_10V7K

2

2

2

2

2

2

2

2

+1.8V

1

C923 0.01U_0402_16V7K

1

C924 180P_0402_50V8JC

C

2

2

Power

Ground

DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE+1.8V

1

C49 4.7U_0805_10V4Z

1

C50 4.7U_0805_10V4Z

1

C51 4.7U_0805_10V4Z

1

C52 4.7U_0805_10V4Z

1

C53 0.22U_0603_10V7K

1

C54 0.22U_0603_10V7K

1

C55 0.22U_0603_10V7K

2

2

2

2

2

2

2

1 1 C56 0.22U_0603_10V7K 1 C57 0.01U_0402_16V7K 1 C58 0.01U_0402_16V7K 1 C59 180P_0402_50V8J 1 C60 180P_0402_50V8J + C795 2 220U_D2_4VM

Athlon 64 S1 Processor Socket

2

2

2

2

2

CPU

left-hand side

CPU right-hand side+0.9VB

+0.9V

B

1

C61 4.7U_0805_10V4Z

1

C68 0.22U_0603_10V7K

1

C63 4.7U_0805_10V4Z

1

C65 0.22U_0603_10V7K

2

2

2

2

+CPU_COREAthlon 64 S1 Processor Socket

1 + C796 45@ 2 820U_E9_2.5V_M_R7 45@

1 + C797 2 820U_E9_2.5V_M_R7

1 + C798 2 330U_D2E_2.5VM_R9

1 + C799 2 330U_D2E_2.5VM_R9

1

C69 1000P_0402_50V7K

1

C74 180P_0402_50V8J

1

C71 1000P_0402_50V7K

1

C76 180P_0402_50V8J

2

2

2

2

A1

A26

PROCESSOR POWER AND GROUNDAthlon 64 S1g1 uPGA638 Top ViewA A

AF1


Compal Secret DataDeciphered Date 2006/03/08Title Size C Date:

Compal Electronics, inc.SCHEMATIC, M/B LA-3151PDocument Number


401412, 09, 20061

Rev B Sheet 8 of 55

5

4

3

2

1

+1.8V

+1.8V

+DIMM_VREF

+1.8V DDR_A_D[0..63] R45 1K_0402_1% DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] DDR_A_DQS#[0..7] 1 1 DDR_A_D[0..63] DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] DDR_A_DQS#[0..7]D

0.1U_0402_16V4Z

JP1 DDR_A_D0 DDR_A_D1D

C77 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 4.7U_0805_10V4Z DDR_A_D4 DDR_A_D5 DDR_A_DM0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR_A_DM1 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_D14 DDR_A_D15 1

DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199

VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD

1 C78 2

2

2

R46 1K_0402_1%

2

DDR_A_CLK1 DDR_A_CLK#1

+1.8V

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1 1 C88 + C802 2 220U_D2_4VM

1 C79

1 C80

1 C81

1 C82

1 C83

1 C84

1 C85

1 C86

1 C87

DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25C

DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDR_CKE1_DIMMA DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# DDR_A_ODT0 DDR_A_MA13 DDR_CS3_DIMMA# DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_CLK2 DDR_A_CLK#2 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 R77 R78 1 1 2 10K_0402_5% 2 10K_0402_5% DDR_A_CLK2 DDR_A_CLK#2 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# DDR_A_ODT0 DDR_CKE1_DIMMA

2

2

2

2

2

2

2

2

2

2

DDR_A_DM3 DDR_A_D26 DDR_A_D27 DDR_CKE0_DIMMA DDR_CS2_DIMMA# DDR_A_BS#2 DDR_CKE0_DIMMA DDR_CS2_DIMMA# DDR_A_BS#2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_ODT1 DDR_A_D32 DDR_A_D33

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V+0.9V 11/01 modify 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 + 2 C925 150U_D2_6.3VM

C

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2 C89

2 C90

2 C91

2 C92

2 C93

2 C94

2 C95

2 C96

2 C97

2 C98

2 C99

2 C100

2 C101

2 C102

2 C103

DDR_A_BS#0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_ODT1

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V+0.9V

DDR_CS3_DIMMA# DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0 DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0 DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_CKE1_DIMMA DDR_CKE0_DIMMA DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# DDR_A_ODT1 DDR_A_ODT0 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5%

B

B

DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49

11/3 Modify0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1

+1.8V

2 C926

2 C927

2 C928

2 C929

2 C930

2 C931

2 C932

2 C933

+0.9V

2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 2 2 2 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5%

DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7A

Layout Note: Place one 0.1uF cap close to every 2 pullup resistors terminated to +0.9V

A

DDR_A_D58 DDR_A_D59 SB_CK_SDAT SB_CK_SCLK SB_CK_SDAT SB_CK_SCLK +3VS 1 C104

2 47_0402_5% 2 47_0402_5%



Compal Electronics, inc.SCHEMATIC, M/B LA-3151PRev B Sheet1

P-TWO_A5692C-A0G16 2 0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.4 3 2


5

5

4

3

2

1

+1.8V

+1.8V

+DIMM_VREF DDR_B_D[0..63] 0.1U_0402_16V4Z DDR_B_D[0..63] DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_MA[0..15] DDR_B_DQS#[0..7]D

JP2 DDR_B_D0 DDR_B_D1D

DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_MA[0..15]

4.7U_0805_10V4Z

C105

C106

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199

VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DDR_B_D4 DDR_B_D5 DDR_B_DM0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 DDR_B_DM1 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_D14 DDR_B_D15

1

1

2

2 DDR_B_DQS#[0..7]

DDR_B_CLK1 DDR_B_CLK#1

+1.8V

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1 C107

1 C108

1 C109

1 C110

1 C111

1 C112

1 C113

1 C114

1 C115

1 C116

DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25C

DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 DDR_CKE1_DIMMB DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# DDR_B_ODT0 DDR_B_MA13 DDR_CS3_DIMMB# DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 R109 1 R110 1 2 10K_0402_5% 2 10K_0402_5% +3VS DDR_B_CLK2 DDR_B_CLK#2 DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# DDR_B_ODT0 DDR_CS3_DIMMB# DDR_CKE1_DIMMB

2

2

2

2

2

2

2

2

2

2

DDR_B_DM3 DDR_B_D26 DDR_B_D27 DDR_CKE0_DIMMB DDR_CS2_DIMMB# DDR_B_BS#2 DDR_CKE0_DIMMB DDR_CS2_DIMMB# DDR_B_BS#2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_D32 DDR_B_D33

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V+0.9V

C

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2 C117

2 C118

2 C119

2 C120

2 C121

2 C122

2 C123

2 C124

2 C125

2 C126

2 C127

2 C128

2 C129

2 C130

2 C131

DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_ODT1

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V+0.9V DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0 DDR_B_BS#2 DDR_B_BS#1 DDR_B_BS#0 DDR_B_CAS# DDR_B_WE# DDR_B_RAS# DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS0_DIMMB# DDR_B_ODT1 DDR_B_ODT0 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% +0.9V

B

DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

B

11/3 Modify0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1

+1.8V

2 C934

2 C935

2 C936

2 C937

2 C938

2 C939

2 C940

2 C941

2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 47_0402_5% 2 2 2 2 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5%

DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7A

R98 1 R99 1 R100 1 R101 1 R102 1 R103 R104 R105 R106 1 1 1 1

Layout Note: Place one 0.1uF cap close to every 2 pullup resistors terminated to +0.9V

DDR_B_D58 DDR_B_D59 SB_CK_SDAT SB_CK_SCLK SB_CK_SDAT SB_CK_SCLK +3VS 1 C132

R107 1 R108 1

2 47_0402_5% 2 47_0402_5%

A



Compal Electronics, inc.SCHEMATIC, M/B LA-3151PRev B Sheet1

P-TWO_A5652C-A0G16 2 0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.4 3 2


5

5

4

3

2

1

D

D





U58A H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0B

C

HYPER TRANSPORT CPU I/F

R19 R18 R21 R22 U22 U21 U18 U19 W19 W20 AC21 AB22 AB20 AA20 AA19 Y19 T24 R25 U25 U24 V23 U23 V24 V25 AA25 AA24 AB23 AA23 AB24 AB25 AC24 AC25 W21 W22 Y24 W25 P24 P25 HT_RXCALP HT_RXCALN A24 C24

HT_RXCAD15P HT_RXCAD15N HT_RXCAD14P HT_RXCAD14N HT_RXCAD13P HT_RXCAD13N HT_RXCAD12P HT_RXCAD12N HT_RXCAD11P HT_RXCAD11N HT_RXCAD10P HT_RXCAD10N HT_RXCAD9P HT_RXCAD9N HT_RXCAD8P HT_RXCAD8N HT_RXCAD7P HT_RXCAD7N HT_RXCAD6P HT_RXCAD6N HT_RXCAD5P HT_RXCAD5N HT_RXCAD4P HT_RXCAD4N HT_RXCAD3P HT_RXCAD3N HT_RXCAD2P HT_RXCAD2N HT_RXCAD1P HT_RXCAD1N HT_RXCAD0P HT_RXCAD0N HT_RXCLK1P HT_RXCLK1N HT_RXCLK0P HT_RXCLK0N HT_RXCTLP HT_RXCTLN HT_RXCALP HT_RXCALN

PART 1 OF 5

HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N HT_TXCLK1P HT_TXCLK1N HT_TXCLK0P HT_TXCLK0N HT_TXCTLP HT_TXCTLN HT_TXCALP HT_TXCALN

P21 P22 P18 P19 M22 M21 M18 M19 L18 L19 G22 G21 J20 J21 F21 F22 N24 N25 L25 M24 K25 K24 J23 K23 G25 H24 F25 F24 E23 F23 E24 E25 L21 L22 J24 J25 N23 P23 C25 D24

H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0 H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 H_CTLIP0 H_CTLIN0 HT_TXCALP HT_TXCALN 1 R112 2 100_0402_1% H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 H_CTLIP0 H_CTLIN0

C

H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0 H_CTLOP0 H_CTLON0 2 49.9_0402_1% 2 49.9_0402_1%

H_CTLOP0 H_CTLON0 +1.2V_HT R111 1 R113 1

B

215NSA4ALA11FG RS485M_BGA465

A

A






5

4

3

2

1

PCIE_GTX_C_MRX_P[0..15]D

PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_N[0..15]D

PCIE_GTX_C_MRX_N[0..15]

U58B PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_N15 PCIE_MRX_PTX_P0 PCIE_MRX_PTX_N0 PCIE_MRX_PTX_P1 PCIE_MRX_PTX_N1 R114 1 R115 1 R116 1 R117 1 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% PCIE_MRX_PTX_P0_R PCIE_MRX_PTX_N0_R PCIE_MRX_PTX_P1_R PCIE_MRX_PTX_N1_R G5 G4 J8 J7 J4 J5 L8 L7 L4 L5 M8 M7 M4 M5 P8 P7 P4 P5 R4 R5 R7 R8 U4 U5 W4 W5 Y4 Y5 V9 W9 AB7 AB6 W11 W12 AA11 AB11 Y7 AA7 AB9 AA9 A_MRX_STX_P0 A_MRX_STX_N0 A_MRX_STX_P1 A_MRX_STX_N1B

C

GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N SB_RX0P SB_RX0N SB_RX1P SB_RX1N PCEH_ISET PCEH_TXISET

PART 2 OF 5

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N

J1 H2 K2 K1 K3 L3 L1 L2 N2 N1 P2 P1 P3 R3 R1 R2 T2 U1 V2 V1 V3 W3 W1 W2 Y2 AA1 AA2 AB2 AB1 AC1 AE3 AE4

PCIE_MTX_GRX_P0 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_P15 PCIE_MTX_GRX_N15

C134 1 C136 1 C138 1 C140 1 C142 1 C144 1 C146 1 C148 1 C150 1 C152 1 C154 1 C156 1 C158 1 C160 1 C162 1 C164 1 C165 1 C167 1

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

C133 1 C135 1 C137 1 C139 1 C141 1 C143 1 C145 1 C147 1 C149 1 C151 1 C153 1 C155 1 C157 1 C159 1 C161 1 C163 1

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15 PCIE_MTX_C_PRX_P0 PCIE_MTX_C_PRX_N0 PCIE_MTX_C_PRX_P1 PCIE_MTX_C_PRX_N1 PCIE_MTX_C_PRX_P0 PCIE_MTX_C_PRX_N0 PCIE_MTX_C_PRX_P1 PCIE_MTX_C_PRX_N1

PCIE I/F GFX

C

AD8 PCIE_MTX_PRX_P0 AE8 PCIE_MTX_PRX_N0 AD7 PCIE_MTX_PRX_P1 AE7 PCIE_MTX_PRX_N1 AD4 AE5 AD5 AD6 AE9 A_MTX_SRX_P0 AD10 A_MTX_SRX_N0 AC8 A_MTX_SRX_P1 AD9 A_MTX_SRX_N1 AD11 AE11 R119 1 R121 1 2 2

C166 1 C168 1

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

PCIE I/F GPP

A_MRX_STX_P0 A_MRX_STX_N0 A_MRX_STX_P1 A_MRX_STX_N1 2 10K_0402_1% 2 8.25K_0402_1%

W14 W15 AB12 AA12 AA14 AB14

PCIE I/F SB

SB_TX0P SB_TX0N SB_TX1P SB_TX1N PCEH_PCAL PCEH_NCAL

C169 1 C171 1 150_0402_1% 100_0402_1%

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

C170 1 C172 1

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

A_MTX_C_SRX_P0 A_MTX_C_SRX_N0 A_MTX_C_SRX_P1 A_MTX_C_SRX_N1

A_MTX_C_SRX_P0 A_MTX_C_SRX_N0 A_MTX_C_SRX_P1 A_MTX_C_SRX_N1 B

R214: R213:

10KOhm FOR RS485 1.47KOhm FOR RS690 8.25KOhm FOR RS485 DNI FOR RS690

R118 1 R120 1

+1.2V_HT


R119: R121:

150 Ohm FOR RS485 562 Ohm FOR RS690 100 Ohm FOR RS485 2KOhm FOR RS690

ATI side check , use +1.2V or not

A

A






5

4

3

2

1

ATI check , CRT / TV/ LVDS can delete or not when I use RX485D

Modify 11/29

D

+1.8VS 1 R846 2 0_0603_5% 1 C947 2 +3VS 1 R809 2 0_0603_5%

U58C B22 C22 G17 H17 A20 B20 A21 A22 C21 C20 D19 E19 F19 G19 C6 A5 1 R123 B21 2 @ 715_0402_1% B6 A6 A10 B10 B24 B25 C10 C11 C5 B5 1 10K_0402_5% C23 B23 C2 AVDD1 AVDD2 AVSSN1 AVSSN2 AVDDDI AVSSDI AVDDQ AVSSQ C_R Y_G COMP_B RED GREEN BLUE DACVSYNC DACHSYNC RSET DACSCL DACSDA

PART 3 OF 5

@ 1U_0402_6.3V4Z +1.8VS +1.8VS PLLVDD L63 1 2 MBK1608800YZF_0805 1 C173 1 2 C174 4.7U_0805_10V4Z 1 R847 2 0_0603_5% 1 C948

TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N TXCLK_LP TXCLK_LN TXCLK_UP TXCLK_UN LPVDD LPVSS

B14 B15 B13 A13 H14 G14 D17 E17 A15 B16 C17 C18 B17 A17 A18 B18 E15 D15 H15 G15 D14 E14 A12 B12 C12 C13 A16 A14 D12 C19 C15 C16 F14 F15

@ 1U_0402_6.3V4Z

CRT/TVOUT

Modify 11/29

2

2

10U_0805_10V4Z

Modify : 11/07

+1.8VS R848 1 1 2 0_0603_5%

+1.8VS HTPVDDC

+1.8VS L67 1 +3VS PLLVDD 1 R125 1K_0402_5% 2 R126 1 HTPVDD

2

C949 @ 1U_0402_6.3V4Z +1.8VS R849 1 2 0_0603_5% R850 1 2 0_0603_5%C

1

2 C175 1 C176 4.7U_0805_10V4Z LDT_STOP#

PM PLL PWR

R810 10K_0402_5% 2 2

PLLVDD PLLVSS HTPVDD HTPVSS

MBK1608800YZF_0805 1

LVDDR18D_1 LVDDR18D_2 LVDDR18A_1 LVDDR18A_2 LVSSR1 LVSSR3 LVSSR5 LVSSR6 LVSSR7 LVSSR8 LVSSR12 LVSSR13

Modify : 11/07

2

2 10U_0805_10V4Z

NB_RST# Q4 NB_PWRGD 3 1 ALLOW_LDTSTOP MMBT3904_SOT23 E C HTREFCLK

NB_OSC NBSRC_CLKP NBSRC_CLKN

B11 A11 F2 E1 G1 G2 R128 1 2 @ 3K_0402_5% R130 R131 R132 R133 1 1 1 1 2 2 @ 2.7K_0402_5% 2 2 2 2 @ 2.7K_0402_5% @ 2.7K_0402_5% @ 2.7K_0402_5% @ 2.7K_0402_5% D33 1 DFT_GPIO0 LOAD_ROM# DFT_GPIO2 DFT_GPIO3 DFT_GPIO4 DFT_GPIO5 D6 D7 C8 C7 B8 A8 B2 A2 B4 AA15 AB15 C14 B3 C3 A3

OSCIN OSCOUT GFX_CLKP GFX_CLKN SB_CLKP SB_CLKN DFT_GPIO0 DFT_GPIO1 DFT_GPIO2 DFT_GPIO3 DFT_GPIO4 DFT_GPIO5

CLOCKs

LOAD_ROM#: LOAD ROM STRAP ENABLE

High, LOAD ROM STRAP DISABLEB

Low, LOAD ROM STRAP ENABLE

BMREQ#

1N4148_SOT23 PAD T11 PAD T7

BMREQb I2C_CLK I2C_DATA THERMALDIODE_P THERMALDIODE_N TMDS_HPD DDC_DATA TESTMODE STRP_DATA 215NSA4ALA11FG RS485M_BGA465

MIS.

1

A

2

B

0_0402_5% 2 LDT_STOP#_NB R127 2

SYSRESET# POWERGOOD LDTSTOP# ALLOW_LDTSTOP HTTSTCLK HTREFCLK TVCLKIN

1 C950 @ 1U_0402_6.3V4Z

1 C951 @ 1U_0402_6.3V4Z

2

2

SBLINK_CLKP SBLINK_CLKN R129 1

LVDS_DIGON LVDS_BLON LVDS_BLEN DVO_D0 DVO_D1 DVO_D2 DVO_D3 DVO_D4 DVO_D5 DVO_D6 DVO_D7 DVO_D8 DVO_D9 DVO_D10 DVO_D11 DVO_VSYNC DVO_DE DVO_HSYNC DVO_IDCKP DVO_IDCKN

E12 G12 F12 AD14 AD15 AE15 AD16 AE16 AC17 AD18 AE19 AD19 AE20 AD20 AE21 AD13 AC13 AE13 AE17 AD17

T4 T5 T6

PAD PAD PAD

B

PAD PAD PAD R134 4.7K_0402_5%

T8 T9 T10

A






5

4

3

2

1

NB RS485 POWER STATESPower Signal VDDHT VDDR VDD18 VDDCD

S0 ON ON ON ON ON ON ON ON ON ON ON ON ON ON

S1 ON ON ON ON ON ON ON ON ON ON ON ON ON ON

S3

S4/S5

G3 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFFU58E A25 F11 D23 E9 G11 Y23 P11 R24 AE18 M15 J22 G23 J12 L12 L14 L20 L23 M11 M20 M23 M25 N12 N14 B7 L24 P13 P20 P15 R12 R14 R20 W23 Y25 AD25 U20 H25 W24 Y22 AC23 D25 G24 AC14 H12 AC22 R23 C4 AE22 T23 T25 AE14 R17 H23 M17 A23 AC15 F17 D4 AC16 M13 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSSA1 VSSA2 VSSA3 VSSA4 VSSA5 VSSA6 VSSA7 VSSA8 VSSA9 VSSA10 VSSA11 VSSA12 VSSA13 VSSA14 VSSA15 VSSA16 VSSA17 VSSA18 VSSA19 VSSA20 VSSA21 VSSA22 VSSA23 VSSA24 VSSA25 VSSA26 VSSA27 VSSA28 VSSA29 VSSA30 VSSA31 VSSA32 VSSA33 VSSA34 VSSA35 VSSA36 VSSA93 VSSA94 VSSA95 VSSA37 VSSA38 VSSA39 VSSA40 VSSA41 VSSA42 VSSA43 VSSA44 VSSA45 M3 V12 V11 V14 F3 V15 A1 H1 G3 J2 H3 AE10 J6 AE6 F1 L6 M2 M6 J3 P6 T1 N3 P9 R6 U2 T3 U3 U6 AC4 Y1 Y15 W6 AC2 Y3 Y9 Y11 Y12 Y14 AA3 R9 AD1 AC5 AC6 AC7 AD3 AC9 AC10 G6D

OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF

VDDA18 VDDA12 AVDD AVDDDI PLLVDD HTPVDD VDDR3 LPVDD LVDDR18D LVDDR18A

CURRENT MEASUREMENT+VDDA_12 +1.2V_HT L70 1 +VDD_HT 2 1 10U_0805_10V4Z 1 1 C183 C184 C185 AE24 AD24 AD22 AB17 AE23 Y17 W17 AC18 AD21 AC19 AC20 AB19 AD23 AA17 AE25 J14 J15 AE2 AB3 U7 W7 AB4 AC3 AD2 AE1 E11 D11 AC12 AD12 AE12 E7 F7 F9 G9 +1.2V_HT +1.2V_HT +1.2V_HT D22 M1 AC11 U58D VDD_HT1 PART VDD_HT2 VDD_HT5 VDD_HT6 VDD_HT9 VDD_HT10 VDD_HT11 VDD_HT12 VDD_HT13 VDD_HT14 VDD_HT15 VDD_HT16 VDD_HT17 VDD_HT18 VDD_HT19 VDD18_1 VDD18_2 VDDA18_1 VDDA18_2 VDDA18_3 VDDA18_4 VDDA18_5 VDDA18_6 VDDA18_7 VDDA18_8 VDDR3_2 VDDR3_1 VDDR_1 VDDR_2 VDDR_3 VDDA12/VDDPLL_1 VDDA12/VDDPLL_2 VSSA12/VSSPLL_1 VSSA12/VSSPLL_2 VDDHT_PKG VDDA12_PKG1 VDDA12_PKG2 L69

PAR 5 OF 5

+1.2V_HT

4 OF 5 VDDA_12_1VDDA_12_2 VDDA_12_3 VDDA_12_4 VDDA_12_5 VDDA_12_6 VDDA_12_7 VDDA_12_8 VDDA_12_9 VDDA_12_10 VDDA_12_11 VDDA_12_12 VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32

C

1

C186

1

C187

1

C188

1

C189 1U_0402_6.3V4Z

KC FBM-L11-201209-221LMAT_0805 2 2

+1.8VS L2 1 2 MBK1608800YZF_0805

2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VDD18

D1 G7 E2 C1 E3 D2 M9 F4 B1 D3 L9 E6 L11 L13 L15 M12 R15 M14 N11 N13 N15 J11 H11 P12 P14 R11 R13 A19 B19 U11 U14 P17 L17 J19 D20 G20 A9 B9 C9 D9 A7 A4 U12 U15

1U_0402_6.3V4Z 10U_0805_10V4Z 1 1 1 1 C178 C179 C180 C181 2 2 1U_0402_6.3V4Z

1 1 C182

2

KC FBM-L11-201209-221LMAT_0805

C

2 2 2 1U_0402_6.3V4Z 10U_0805_10V4Z

+1.2V_HT 10U_0805_10V4Z 1U_0402_6.3V4Z 1 1 1 1 1 C192 C193 C194 C195 C196 2 10U_0805_10V4Z 1 + C803 2 220U_D2_4VM 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2 2 1U_0402_6.3V4Z 1 C205 1

1

C190 2.2U_0603_6.3V6K

1

C191 2.2U_0603_6.3V6K VDDA18

+1.8VS L64 1 2 1 C198 1 C199 1 C200 1 C201 1 C202 1

3A beadC203 1 C204

KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z

POWER

2 2 1U_0402_6.3V4Z C206 1 C207

1U_0402_6.3V4Z

2

+3VS

2 2 2 2 2 2 10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VDDR3 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

L3 1 2 MBK1608800YZF_0805B

1

C208 4.7U_0805_10V4Z VDDR

GROUND

RS690: VDDA18=1.2V RS485: VDDA18=1.8V

1

2

2

C197

B

2 +1.8VS L4 1 2 MBK1608800YZF_0805 @

1

C209

1

1 C210 C211

1U_0402_6.3V4Z

2

2 2 @ 1U_0402_6.3V4Z @ 1U_0402_6.3V4Z

+1.2V_HT 1

+VDDA_12

1

C213

1

2 C214

C212 10U_0805_10V4Z


4.7U_0805_10V4Z

Modify 11/07 for EMI

Close to U58.M12 2 1U_0402_6.3V4Z


RS485: 0 Ohm RESISTOR RS690: 220 Ohm 500mA FERRITE BEADA A






5

4

3

2

1

+3VS CLK_VDD L5 1 2 MBK2012121YZF_0805 10U_0805_10V4Z 1 C215 C216 2 +3VS L6 1 2 MBK2012121YZF_0805 C225 10U_0805_10V4ZD

1

1

C217

1

C218

1

C219

1

C220

1

C221

1

C222

1

C223

CLK_VDDA 2 C224 0.1U_0402_16V4Z 1

2

2

2

2

2

2

2

2 1

D

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS

2

1- PLACE ALL SERIAL TERMINATION RESISTORS CLOSE TO U800 2- PUT DECOUPLING CAPS CLOSE TO U800 POWER PIN

L7 1 2 MBK2012121YZF_0805 1 C226 +3VS 2.2U_0603_6.3V6K 2 L8 1 2 MBK2012121YZF_0805 1 C227 2.2U_0603_6.3V6K 2

CLK_VDD U8 54 14 23 28 44 5 39 2 60 53 15 22 29 45 8 38 1 58 3 1 0_0402_5% 4 VDDCPU VDDSRC VDDSRC VDDSRC VDDSRC VDD48 VDDATIG VDDREF VDDHTT GNDCPU GNDSRC GNDSRC GNDSRC GNDSRC GND48 GNDATIG GNDREF GNDHTT X1 X2 VDDA GNDA CPUCLK8T0 CPUCLK8C0 CPUCLK8T1 CPUCLK8C1 SRCCLKT6 SRCCLKC6 ATIGCLKT0 ATIGCLKC0 ATIGCLKT1 ATIGCLKC1 ATIGCLKT2 ATIGCLKC2 ATIGCLKT3 ATIGCLKC3 SRCCLKT5 SRCCLKC5 SRCCLKT4 SRCCLKC4 SRCCLKT3 SRCCLKC3 SRCCLKT2 SRCCLKC2 SRCCLKT0 SRCCLKC0 SRCCLKT1 SRCCLKC1 SRCCLKT7 SRCCLKC7 CLKREQA# CLKREQB# CLKREQC# 48MHz_1 48MHz_0 FS1/REF1 FS0/REF0 FS2/REF2 HTTCLK0 ICS951462AGLFT_TSSOP64 50 49 56 55 52 51 16 17 41 40 37 36 35 34 30 31 18 19 20 21 24 25 26 27 47 46 43 42 12 13 57 32 33 7 6 63 64 62 59 CPUCLK_EXT_R R140 1 CPUCLK#_EXT_R R141 1 2 47_0402_1% 2 47_0402_1% R139 261_0402_1% 1 2 CPUCLK CPUCLK#

Parallel Resonance CrystalC228 1 CLK_VDD Y1 1 2C

SBLINK_CLKP_R SBLINK_CLKN_R NBSRC_CLKP_R NBSRC_CLKN_R GFX_CLKP_R GFX_CLKN_R

R142 R143 R144 R145 R146 R147

1 1 1 1 1 1

2 2 2 2 2 2

33_0402_1% 33_0402_1% 33_0402_1% 33_0402_1% 33_0402_1% 33_0402_1%

SBLINK_CLKP SBLINK_CLKN NBSRC_CLKP NBSRC_CLKN CLK_PCIE_VGA CLK_PCIE_VGA#

2 1 2 R148 @ 1

33P_0402_50V8J

R153 10K_0402_5% 2

33P_0402_50V8J 1M_0402_5% R154 2 1 2 C229 14.31818MHz_20P_1BX14318BE1A

SBSRC_CLKP_R SBSRC_CLKN_R GPP_CLK4P_R GPP_CLK4N_R GPP_CLK0P_R GPP_CLK0N_R

R149 R150 R151 R152 R155 R156

1 1 1 1 1 1

2 2 2 2 2 2

33_0402_1% 33_0402_1% 33_0402_1% 33_0402_1% 33_0402_1% 33_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1%

SBSRC_CLKP SBSRC_CLKN CLK_PCIE_CARD CLK_PCIE_CARD# CLK_PCIE_MINI1 CLK_PCIE_MINI1#

C

11 61 1 C230 0.1U_0402_16V4Z @ SB_CK_SCLK SB_CK_SDAT

RESET_IN# NC

2

1 R159

1 R160

1 R161

1 R162

1 R163

1 R164

1 R165

1 R166

1 R167

1 R168

1 R169

R158 1 R171 1

2 2

0_0402_5% 0_0402_5%

EXP_CLKREQ# MINI1_CLKREQ#

48

Ioh = 5 * Iref (2.32mA) Voh = 0.71V @ 60 ohm

IREF

2

CLK_48M_SIO_R CLK_48M_USB_R R175 1 R176 1 2 33_0402_1% 2 33_0402_1%

R173 475_0402_1% 1

CLK_VDD 1 CLK_SD_48M CLK_USB_48M R177

2.2K_0402_5% 1 R178 1 R179 2.2K_0402_5% 2 2 2 R181 2 R183 2 R185 2 1 @ 0_0402_5% 1 @ 0_0402_5% 1 @ 0_0402_5%

2.2K_0402_5% R180 1 R182 1 R184 1 SB_OSCIN_R R186 1 R187 1 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 33_0402_1% 2 33_0402_1%

ICH_SMBDATAB

ICH_SMBDATA ICH_SMBCLK

R192 1 R193 1

2 2

0_0402_5% SB_CK_SDAT 0_0402_5% SB_CK_SCLK FS0

SB_OSCIN CLK_14M_SIO B

ICH_SMBCLK

NB_OSCIN_R HTREFCLK_R

R188 1 R190 1

2 33_0402_1% 2 33_0402_1% 1

NB_OSC HTREFCLK

R191 51.1_0402_1% 2

EXT CLK FREQUENCY SELECT TABLE(MHZ)FS2 FS1 FS0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 CPU Hi-Z X 180.00 220.00 100.00 133.33 200.005

SRCCLK [2:1] 100.00 100.00 100.00 100.00 100.00 100.00 100.00

HTT Hi-Z X/3 60.00 36.56 66.66 66.66 66.66

PCI Hi-Z X/6 30.00 73.12 33.33 33.33 33.33

USB 48.00 48.00 48.00 48.00 48.00 48.00 48.00

COMMENT Reserved Reserved Reserved Reserved Reserved Reserved Normal ATHLON64 operation4

A

1 R170

SB_CK_SCLK SB_CK_SDAT

9 10

SMBCLK SMBDAT

A




THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2


5

4

3

2

1

PCIE Lane Reversal CLK_PCIE_VGA CLK_PCIE_VGA# PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P0 C232 1 C234 1 C236 1 C238 1 C240 1 C242 1 C244 1 C246 1 C248 1 C251 1 C253 1 C255 1 C257 1 C259 1 C261 1 C263 1 CLK_PCIE_VGA CLK_PCIE_VGA# PCIE_GTX_MRX_N15 PCIE_GTX_MRX_P15 PCIE_GTX_MRX_N14 PCIE_GTX_MRX_P14 PCIE_GTX_MRX_N13 PCIE_GTX_MRX_P13 PCIE_GTX_MRX_N12 PCIE_GTX_MRX_P12 PCIE_GTX_MRX_N11 PCIE_GTX_MRX_P11 PCIE_GTX_MRX_N10 PCIE_GTX_MRX_P10 PCIE_GTX_MRX_N9 PCIE_GTX_MRX_P9 PCIE_GTX_MRX_N8 PCIE_GTX_MRX_P8 PCIE_GTX_MRX_N7 PCIE_GTX_MRX_P7 PCIE_GTX_MRX_N6 PCIE_GTX_MRX_P6 PCIE_GTX_MRX_N5 PCIE_GTX_MRX_P5 PCIE_GTX_MRX_N4 PCIE_GTX_MRX_P4 PCIE_GTX_MRX_N3 PCIE_GTX_MRX_P3 PCIE_GTX_MRX_N2 PCIE_GTX_MRX_P2 PCIE_GTX_MRX_N1 PCIE_GTX_MRX_P1 PCIE_GTX_MRX_N0 PCIE_GTX_MRX_P0 PCIE_MTX_C_GRX_N15 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P0 +1.2VS R215 1 R217 1 R218 1 R220 1 R221 1

U9A

+3VS

Straps: (Internal pull down)Transmitter power saving enable Transmitter de-emphasis enable Debug Access PLL_IBIAS_RD ROM ID Config Low -> VDDC=1.2V High -> VDDC=1.0V GPIO[0] GPIO[1] GPIO[4] 0: 50% TX output swing 1: Full TX output swing 0: TX de-emphasis disable 1: TX de-emphasis enable 0: OFF Pad must be available 1: ON000X: No ROM, AP_SIZE=00 128M share Memory 001X: No ROM, AP_SIZE=01 256M share Memory 010X: No ROM, AP_SIZE=10 64M share Memory 011X: No ROM, AP_SIZE=11 Reserved

AL28 AK28 AK27 AJ27 AJ25 AH25 AH28 AG28 AG27 AF27 AF25 AE25 AE28 AD28 AD27 AC27 AC25 AB25 AB28 AA28 AA27 Y27 Y25 W25 W28 V28 V27 U27 U25 T25 T28 R28 R27 P27 AJ31 AH31 AH30 AG30 AG32 AF32 AF31 AE31 AE30 AD30 AD32 AC32 AC31 AB31 AB30 AA30 AA32 Y32 Y31 W31 W30 V30 V32 U32 U31 T31 T30 R30 R32 P32 P31 N31

PCIE_REFCLKP PCIE_REFCLKN PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N PCIE_TX4P PCIE_TX4N PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N PCIE_TX13P PCIE_TX13N PCIE_TX14P PCIE_TX14N PCIE_TX15P PCIE_TX15N PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_RX4P PCIE_RX4N PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N PCIE_RX13P PCIE_RX13N PCIE_RX14P PCIE_RX14N PCIE_RX15P PCIE_RX15N PCIE_CALRN PCIE_CALRP PCIE_CALI PERST# PCIE_TEST PERST#_MASK

GPIO

D

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

C

VIP HOST/ EXTERNAL TMDS

PCI EXPRESS

2 0.1U_0402_16V7K C231 1 2 0.1U_0402_16V7K C233 1 2 0.1U_0402_16V7K C235 1 2 0.1U_0402_16V7K C237 1 2 0.1U_0402_16V7K C239 1 2 0.1U_0402_16V7K C241 1 2 0.1U_0402_16V7K C243 1 2 0.1U_0402_16V7K C245 1 2 0.1U_0402_16V7K C247 1 0.1U_0402_16V7K 2 C249 1 2 0.1U_0402_16V7K C252 1 0.1U_0402_16V7K 2 C254 1 2 0.1U_0402_16V7K C256 1 0.1U_0402_16V7K 2 C258 1 2 0.1U_0402_16V7K C260 1 0.1U_0402_16V7K 2 C262 1

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7_BLON GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 NC VREFG

AD4 AD2 AD1 AD3 AC1 AC2 AC3 AB2 AC6 AC5 AC4 AB3 AB4 AB5 AD5 AB8 AA8 AB7 AB6 AC8 AK4 AL4 AF2 AF1 AF3 AG1 AG2 AG3 AH2 AH3 AJ2 AJ1 AK2 AK1 AK3 AL2 AL3 AM3 AE6 AF4 AF5 AG4 AJ3 AH4 AJ4 AG5 AH5 AF6 AE7 AG6

R194 1 R195 1 R196 1 R197 1 R198 1 R199 1 TP1 R200 1 R201 1 R202 1

2 10K_0402_5% 2 10K_0402_5%@ 10K_0402_5% 2 2 10K_0402_5% @ 10K_0402_5% 2 @ 2 10K_0402_5% @ 2 10K_0402_5% X76@ 2 10K_0402_5% X76@ 2 10K_0402_5%

GPIO[6,5] Default : 01 GPIO[9, 13:11]D

POWER_SEL OSC_SPREAD THER_ALERT# R203 2 R204 1

POWER_SEL +3VS 499_0402_1% 1 499_0402_1% 2 C250 1 2 0.1U_0402_16V4Z

NC_DVOVMODE_0 NC_DVOVMODE_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

C

PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_N[0..15]

PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_N[0..15]

+3VS TP2 TP3 MEMID0 MEMID1 MEMID2 TP4 R205 1 R206 1 R207 1 R208 1 R209 1

+3VS +3VS

2 4.7K_0402_5% 2 4.7K_0402_5% I2C_DAT I2C_CLK 2 10K_0402_5% X76@ 2 10K_0402_5% X76@ 10K_0402_5% X76@ 2

I2C_DAT I2C_CLK +3VS

Thermal sensor1R210 2.2K_0402_5% THM@ U10

CRT

R211

1 2 2 3

VDD D+ D-

SCLK SDATA ALERT# GND

8 7 6 5

THERM_SCL

R G B HSYNC VSYNC

AK24 AM24 AL24 AJ23 AJ22

VGA_CRT_R VGA_CRT_G VGA_CRT_B CRT_HSYNC CRT_VSYNC R213 1 R214 1

VGA_CRT_R VGA_CRT_G VGA_CRT_B CRT_HSYNC CRT_VSYNC Need Level Shift Need Level Shift VGA_CRT_DAT VGA_CRT_CLK B

2 1THERM_SDA 2.2K_0402_5% THM@ THER_ALERT#

D+ DC264 1 2

1 R212

4

OVERT#

2 0_0402_5% THM@

2 4.7K_0402_5% 2 4.7K_0402_5%

+3VS VGA_CRT_DAT VGA_CRT_CLK

B

DDC1DATA DDC1CLK GENERICA GENERICB RSET

AH22 AH23 AK22 AF23 AL22 AK15 AM15 AL15 AF15 AG15 AJ15 AJ13 AH15 AK14 AC7 AG14 AG22R228 2 VGA_TV_Y VGA_TV_C VGA_TV_COMP R223 2

THM@ 2200P_0402_50V7K THM@ MAX6649MUA_8UMAX

2 2K_0402_1% AE24 2 562_0603_1% AD24 2 1.47K_0603_1% AB24 2 0_0402_5% 2 10K_0402_5% AG24 AA24 AF24

GENERICA NC,GENERICB Grounded -->Internal SS R216 2 1K_0402_5% LVDS Bus 1 R219 2

Vedio Memory Config. (VGA Internal PD) MEMID[2:0] Size Size 16M16 Vender Chips VGA Hynix Hynix Hynix 2 2 4 4 4 4 A-test A-test Frequence

1

499_0402_1%

NB_RST#

TVTHERMAL

R2 G2 B2 H2SYNC V2SYNC Y C COMP R2SET ROMCS# PLLTEST TESTEN

+3VS 0_0603_5% 2 1

D+ R222

AG12 AH12 AE12 AF12 AL26 AM26

SSC@

Spread spectrum+3VS U11 R224 1 R225 1 4.7K_0402_5% 2 2 4.7K_0402_5%

DPLUS DMINUS DDC3DATA DDC3CLK XTALIN XTALOUTM56P M56@

DTHERM_SDA THERM_SCL

VGA_TV_Y VGA_TV_C VGA_TV_COMP

1

715_0402_1%

7 1 C265SSC@ 0.1U_0402_16V4Z

VDD

REF

5 4 3 6 1 R226

Memory Interface SS

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

64MB 64MB

16M16 Samsung

128MB 16M16 256MB 32M16 Resreved Resreved

128MB 16M16 Samsung 256MB 32M16 Samsung

1 8

XIN MODOUT XOUT VSS NC PD#

2 OSC_SPREAD 22_0402_5% SSC@

OSC_IN 1 R227

2 121_0402_1%R229

XTAL

1

1K_0402_5%

2

2

A

2

+3VS

ASM3P1819N-SR_SO8 SSC@ Minimize distance from X1 pin3 to U3 pin1

1

71.5_0402_1%

A

R230 1K_0402_5% 2

1 2 C266 0.1U_0402_16V4Z X1 4 VDD OUT 1 OE GND27MHZ_15P

TBDSecurity Classification3 2OSC_IN

1

Compal Secret Data2005/09/10 Deciphered Date 2006/09/10Title

Compal Electronics, Inc.SCHEMATIC, M/B LA-3151PRev B Sheet1

Issued Date

Keep away from other signal at last 25mils4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2

Size Document Number Custom 401412 Date: |, 09, 2006

16

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2

1

U9F U9G U9B

D

AE13 AF13 AF9 AG7 AE10 AE9 AF7 AF8 AH6 AF10 AG10 AH9 AJ8 AH8 AG9 AH7 AG8 AE23 Y23 K15 R10 AC17100mA

TV GND

GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 GPIO_32 GPIO_33 GPIO_34 GENERICC BBN BBN BBN BBN BBP BBP BBP BBP VDD25 VDD25 VDD25

EXPAND GPIO LVDS

TXCLK_LN TXCLK_LP TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N VARY_BL DIGON GENERICD TXCM TXCP TX0M TX0P TX1M TX1P TX2M TX2P TX3M TX3P TX4M TX4P TX5M TX5P DDC2DATA DDC2CLK HPD1

AL18 AM18 AL19 AK19 AM20 AL20 AM21 AL21 AJ18 AK18 AD12 AE11 AD23 AL9 AM9 AK10 AL10 AL11 AM11 AL12 AM12 AK9 AJ9 AK11 AJ11 AK12 AJ12 AH13 AG13 AF11

VGA_LVDSACVGA_LVDSAC+ VGA_LVDSA0+ VGA_LVDSA0VGA_LVDSA1+ VGA_LVDSA1VGA_LVDSA2+ VGA_LVDSA2-

CRT GND

TXCLK_UP TXCLK_UN TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N

AJ21 AK21 AG18 AH18 AK20 AJ20 AG20 AH20 AH21 AG21

VGA_LVDSBC+ VGA_LVDSBCVGA_LVDSB0+ VGA_LVDSB0VGA_LVDSB1+ VGA_LVDSB1VGA_LVDSB2+ VGA_LVDSB2-

VGA_LVDSBC+ VGA_LVDSBC- VGA_LVDSB0+ VGA_LVDSB0- VGA_LVDSB1+ VGA_LVDSB1- VGA_LVDSB2+ VGA_LVDSB2-

VGA_LVDSAC- VGA_LVDSAC+ VGA_LVDSA0+ VGA_LVDSA0- VGA_LVDSA1+ VGA_LVDSA1- VGA_LVDSA2+ VGA_LVDSA2- ENBKL To EC

PLL GND

R231 1

FOREARD COMPATIBILITY

2 10K_0402_5% ENVDD ENVDD 10/20/05"

PCIE GND

+VDD_CORE

DVI_TX0-_L R631 2 DVI_TX0+_L R632 2 DVI_TX1-_L R633 2 DVI_TX1+_L R634 2 DVI_TX2-_L R635 2 DVI_TX2+_L R636 2 11/07/05"

1 0_0402_5% DVI@ DVI_TX01 0_0402_5% DVI@ DVI_TX0+ 1 0_0402_5% DVI@ DVI_TX11 0_0402_5% DVI@ DVI_TX1+ 1 0_0402_5% DVI@ DVI_TX21 0_0402_5% DVI@ DVI_TX2+

LVDS PLL&I/O GND

AC14 M23 V10 K18 L10 K22 AA10

DVI_TXC-_L R629 2 DVI_TXC+_L R630 2

1 0_0402_5% DVI@ DVI_TXC1 0_0402_5% DVI@ DVI_TXC+

C

+VDD25

100mA

1 C267 0.1U_0402_16V4Z 2

1 C268 20.1U_0402_16V4Z

+3VS R236 1 R237 1

2 6.8K_0402_5% 2 6.8K_0402_5% VGA_DVI_DAT VGA_DVI_CLKVGA_DVI_DET

Need Level Shift VGA_DVI_DAT VGA_DVI_CLK VGA_DVI_DET

M56P M56@

AH27 AC23 AL27 R23 P25 R25 T26 U26 Y26 AB26 AC26 AD25 AE26 AF26 AD26 AG25 AH26 AC28 Y28 U28 P28 AH29 AF28 V29 AC29 W27 AB27 V26 AJ26 AJ32 AK29 P26 P29 R29 T29 U29 W29 Y29 AA29 AB29 AD29 AE29 AF29 AG29 AJ29 AK26 AK30 AG26 N30 R31 AF30 AC30 V31 P30 AA31 U30 AD31 AK32 AJ28 Y30 AJ30 AK31

PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSSM56P M56@

TMDS GND

TXVSSR TXVSSR TXVSSR TXVSSR TXVSSR TPVSS AVSSQ AVSSN AVSSN VSS1DI A2VSSQ A2VSSN A2VSSN VSS2DI PVSS MPVSS LPVSS LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR PCIE_PVSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS

AJ7 AK7 AL7 AM7 AK8 AL8 AK23 AK25 AJ24 AL23 AK13 AM17 AL17 AJ17 AH14 A5 AE18 AK17 AJ19 AF18 AH17 AG17 AG19 AH19 AF22 AF17 AF21 W23 AB23 P24 R24 T24 U24 V24 W24 Y24 AC24 AH24 V25 AA25 R26 AA26 T27 AE27 AG31 W26 N24 AA23

Use 15mils trace connect to GND

B

R232 1 DVI_TXCDVI_TXC+ R233 1 DVI_TX0DVI_TX0+ R234 1 DVI_TX1DVI_TX1+ DVI_TX2DVI_TX2+ R235 1

2 180_0402_5% DVI@ 2 180_0402_5% DVI@ 2 180_0402_5% DVI@ 2 180_0402_5% DVI@DVI_TXC- DVI_TXC+ DVI_TX0- DVI_TX0+ DVI_TX1- DVI_TX1+ DVI_TX2- DVI_TX2+ 10/20/05" Close to connector

B1 H1 L1 P1 U1 Y1 AD7 AE8 AL1 A2 AM2 AD10 E8 H5 K10 M8 T10 E12 AC9 AF14 AD8 C5 F10 J3 L6 M6 P6 AA4 AG11 V3 AG16 R3 C6 C9 F6 H7 J6 AD16 AA6 P7 P5 M3 M9 L7 M7 AD17 AH11 A8 U7 C10 E9 F3 J9 N7 N3 Y5 AM13 AC10 Y6 U6 E5 AL13 A11 U8 U9 U10 R6 AD6 V6 AD14 AD13 D11 J12 K12 A13 F13 E13 F15 K16 W18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CORE GND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

C27 E32 H28 J30 K17 K27 M32 A22 C20 E19 H20 J24 M28 J28 J16 F30 L29 A31 B32 E30 AE15 AG23 AD9 AF16 AH10 AJ10 AD15 AH16 K23 U18 AE16 AE17 A19 H32 F19 G19 N8 Y7 T19 V19 G21 C21 F21 AE14 AK16 U5 F22 F18 K30 C24 F24 M24 A25 D30 E25 G25 G20 G22 F27 E28 H21 J21 H16 T15 V17 C15 C4 U14 P15 A16 E16 G13 G16 P17 R16 R14 W16 C18 F16

D

INTERGRATED TMDS

C

B

M56P M56@

A

A



Compal Electronics, Inc.SCHEMATIC, M/B LA-3151PRev B Sheet1


Size Document Number Custom 401412 Date: |, 09, 2006

17

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2

1

U9D U9C FBCD0 FBCD1 FBCD2 FBCD3 FBCD4 FBCD5 FBCD6 FBCD7 FBCD8 FBCD9 FBCD10 FBCD11 FBCD12 FBCD13 FBCD14 FBCD15 FBCD16 FBCD17 FBCD18 FBCD19 FBCD20 FBCD21 FBCD22 FBCD23 FBCD24 FBCD25 FBCD26 FBCD27 FBCD28 FBCD29 FBCD30 FBCD31 FBCD32 FBCD33 FBCD34 FBCD35 FBCD36 FBCD37 FBCD38 FBCD39 FBCD40 FBCD41 FBCD42 FBCD43 FBCD44 FBCD45 FBCD46 FBCD47 FBCD48 FBCD49 FBCD50 FBCD51 FBCD52 FBCD53 FBCD54 FBCD55 FBCD56 FBCD57 FBCD58 FBCD59 FBCD60 FBCD61 FBCD62 FBCD63 +MVREFD_1 +MVREFS_1

D

C

M31 M30 L31 L30 H30 G31 G30 F31 M27 M29 L28 L27 J27 H29 G29 G27 M26 L26 M25 L25 J25 G28 H27 H26 F26 G26 H25 H24 H23 H22 J23 J22 E23 D22 D23 E22 E20 F20 D19 D18 B19 B18 C17 B17 C14 B14 C13 B13 D17 E18 E17 F17 E15 E14 F14 D13 H18 H17 G18 G17 G15 G14 H14 J14PAD PAD T32 T33

DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63

MEMORY A

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9 MAA_10 MAA_11 MAA_12 MAA_13 MAA_14 MAA_15

D26 F28 D28 D25 E24 E26 D27 F25 C26 B26 D29 B27 B25 C25 E27 E29 H31 J29 J26 G23 E21 B15 D14 J17 J31 K29 K25 F23 D20 B16 D16 H15 K31 K28 K26 G24 D21 C16 D15 J15 F29 D24 D31 E31 B30 B28 C29 B31 B29 C28 2 B20 C19+1.8VS

FBCD[0..63] FBCA[0..12] FBCDQS[0..7] FBCDQS#[0..7] FBCDQM#[0..7]

FBCD[0..63] FBCA[0..12] FBCDQS[0..7] FBCDQS#[0..7] FBCDQM#[0..7]

FBC_BA0 FBC_BA1

FBC_BA0 FBC_BA1

DQMA#_0 DQMA#_1 DQMA#_2 DQMA#_3 DQMA#_4 DQMA#_5 DQMA#_6 DQMA#_7 QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7 QSA_0# QSA_1# QSA_2# QSA_3# QSA_4# QSA_5# QSA_6# QSA_7# ODTA0 ODTA1 CLKA0 CLKA0# CKEA0 RASA0# CASA0# WEA0# CSA0#_0 CSA0#_1 CLKA1 CLKA1# CKEA1

FBCCLK0 FBCCLK0#

R637 2 R638 2

56_0402_5% 1 56_0402_5% 1 64BIT@ 56_0402_5% 1 56_0402_5% 64BIT@ 1

C804

1

2

470P_0402_50V7K

FBCCLK1 FBCCLK1#

R639 2 R640 2

C805

1

2

470P_0402_50V7K 64BIT@

10/20/05" Close to Memory Side

+1.8VS

R238 100_0402_1%

R239 100_0402_1%

B12 C12 B11 C11 C8 B7 C7 B6 F12 D12 E11 F11 F9 D8 D7 F7 G12 G11 H12 H11 H9 E7 F8 G8 G6 G7 H8 J8 K8 L8 K9 L9 K5 L4 K4 L5 N5 N6 P4 R4 P2 R2 T3 T2 W3 W2 Y3 Y2 T4 R5 T5 T6 V5 W5 W6 Y4 R8 T8 R7 T7 V7 W7 W8 W9 B3 C3 AA3 AA5 AA2 AA7

DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63

MEMORY B

MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8 MAB_9 MAB_10 MAB_11 MAB_12 MAB_13 MAB_14 MAB_15

G4 E6 E4 H4 J5 G5 F4 H6 G3 G2 D4 F2 H2 H3 F5 D5 B8 D9 G9 K7 M5 V2 W4 T9 B9 D10 H10 K6 N4 U2 U4 V8 B10 E10 G10 J7 M4 U3 V4 V9 D6 J4 B4 B5 C2 E2 D3 B2 D2 E3 N2 P3 L3 J2 L2 M2 K2 K3

FBCA0 FBCA1 FBCA2 FBCA3 FBCA4 FBCA5 FBCA6 FBCA7 FBCA8 FBCA9 FBCA10 FBCA11 FBC_BA0 FBC_BA1 FBCA12

D

DQMB#_0 DQMB#_1 DQMB#_2 DQMB#_3 DQMB#_4 DQMB#_5 DQMB#_6 DQMB#_7 QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7 QSB_0# QSB_1# QSB_2# QSB_3# QSB_4# QSB_5# QSB_6# QSB_7# ODTB0 ODTB1 CLKB0 CLKB0# CKEB0 RASB0# CASB0# WEB0# CSB0#_0 CSB0#_1 CLKB1 CLKB1# CKEB1

FBCDQM#0 FBCDQM#1 FBCDQM#2 FBCDQM#3 FBCDQM#4 FBCDQM#5 FBCDQM#6 FBCDQM#7 FBCDQS0 FBCDQS1 FBCDQS2 FBCDQS3 FBCDQS4 FBCDQS5 FBCDQS6 FBCD

Compal La-3151p Hcw50 Schematics

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