Compact MOSFET Model for ESD Applications* ESD Protection Scheme for RF Applications • Designed...
Transcript of Compact MOSFET Model for ESD Applications* ESD Protection Scheme for RF Applications • Designed...
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Compact MOSFET Model for ESD Applications*
Juin J. Liou1 and Xiaofang Gao2
1Electrical and Computer Engineering Dept.University of Central Florida, Orlando, Florida
2Modeling and Simulation GroupIntel Corporation, Sacramento, CA
* This work was supported in part by Intersil Corp., Intel Corp., and Semiconductor Research Corporation
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Outline
• Overview of electrostatic discharge (ESD)• ESD protection scheme• MOS compact modeling for ESD
applications• Implementation into Cadence SPICE• Results• Conclusions
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Customer Return Failure Statistics
26%
37%
15%
3%4%
14% 1%
ee
Fab
ESD/EOS
Unknown
Mobile Ion
Good
Assembly Electrical QA
Data from National Semiconductor Corporation
The protection circuits are becoming more and more important in the circuitdesign. The ESD failures typically constitute a major portion of customer returns
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Ouch!~~~
A Phenomenon of Electrostatic Discharge
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ESD Models
±
±
±
±
MODELS
Parameters
Timerise (nsec) Timedecay (nsec) Vpeak (V)Standard wave
form load
HBM < 10 150 20 2000~ 15000 Short/ 500Ω
MM 6 ~ 7.5 66-90(Ring period)
100 ~400 Short/ 500Ω
CDM < 0.2 ~ 0.4 0.4 ~2 250 ~2000Cu discs4/30pF
IEC 0.7 ~1 ~80 2000 ~ 15000Air gap
Discharge/50MΩ-100MΩ
±
HBM: Human Body ModelMM: Machine ModelCDM: Charge Device ModelIEC: International Electrotechnical Commission
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Damages from ESD Events
Blown Polysilicon resistor, soft damage at the MOS drain edge, rupture in gate oxide, and Zener diode junction spiking
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Outline
• Overview of electrostatic discharge (ESD)• ESD protection scheme• MOS compact modeling for ESD
applications• Implementation into Cadence SPICE• Results• Conclusions
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On-Chip ESD Protection Structures
PD
PSNS
VDD
VSS
I/O
ND
Single path at I/O (i.e., ggMOS) with one-direction supply clamp
Duel path at I/O (i.e., diode, SCR) with one-direction supply clamp
Duel path at I/O (i.e., diode, SCR) with bi-direction supply clamp
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Complete On-Chip ESD Protection Scheme
Core Circuit SupplyClamp
I/O pad
PI/O-Vcc
NVss-I/O PI/O-Vss
NVcc-I/O
Vcc
Vss
Design Considerations:
1) A highly conductive path between any two pads when One pad can be subject to either positive or negative ESD stress and the other is grounded;
2) The ESD protection structure should be transparent to the core circuit under normal operation;
3) The ESD protection should not be damaged by the ESD stress and yet sufficiently small to reduce the chip size and parasitic C and R.
I/O pad protection devicesSupply clamp
Supply Clamp: Need to consider both holding and triggering voltagesI/O devices: Consider only the triggering voltage. Voltage at the I/O pad can be varying!
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Protection Devices at the I/O Pad
I/O
Rg
Rg
LVTSCR ggNMOS Chain of diodes
I/O
I/O
LVTSCR: Fast turn-on speed and robust, but complex structureggNMOS/PMOS: Simple structure, but higher hold-on voltage and lower current
handling capabilityDiodes: Most widely used I/O protections. Simple structure, but large area
needed
Cathode
N-L
VTS
CR
N+
P well
N well
P+
Anode
Rg
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Supply Clamps
Vss
ControlNode
C
R
Simple MOSFET clamp
Vss
Vcc
Inverter MOS clamp
Vss
BJT clamp
Vcc
Vcc
Vcc
Vss
LVTSCR clamp
Cathode
N-L
VTS
CR
N+
P well
N well
P+
Anode
Rg
C
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ESD Protection for MEMS Gas Sensor SoC
Gas Sensor microchip by National Institute of Standard and Technology
This MEMS chip has ESD protection designed based on LVTSCRs
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Typical ESD Protection Schemefor RF Applications
• Designed based on diodes and supply clamps
• ESD protection structure must be processed using the same technology and at the same time as the circuit core (i.e., 0.13 µm CMOS technology)
• Ideally, the ESD structure can protect the circuit core during the ESD event, yet does not degrade the circuit core performance during normal RF operation
CircuitCore
SupplyClamp
SupplyClamp
SupplyClamp
SupplyClamp
V+
V-
Output
Input Input
I/O
Floating Rail #1
Floating Rail #2
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ESD Discharge PathCase: positive ESD pulse at one
I/O and the other I/O grounded• The preferred discharging path
involves two forward-path diodes and supply clamp
• The supply clamp provides a small and near constant voltage across the two supply rails
• Without the supply clamp, one or more diodes will be operating in the breakdown region ⇒ large-size diodes required
Supply Clamp
D1
D2
VDD
VSS
I/O I/OCore Circuit
Current
Vdd
Vss
ControlNode
C
R
Our focus here is to develop a compact MOSFET model for simulations during the ESD event (i.e., fast transient, high voltage/current conditions)
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Outline
• Overview of electrostatic discharge (ESD)• ESD protection scheme• MOS compact modeling for ESD
applications• Implementation into Cadence SPICE• Results• Conclusions
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Comparison of I-V Characteristics between Measurementsand SPICE Simulation Based on Conventional MOS model
D ra in V o lta g e (V )
0 1 0 2 0 3 0 4 0 5 0
Dra
in C
urre
nt (m
A)
0
2 0
4 0
6 0
8 0
1 0 0
S im u la t io n
0 1 0 2 0 3 0 4 0 5 00
2 0
4 0
6 0
8 0
1 0 0M e a s u re m e n t
Device Size = 160µm/1.2µm
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An NMOS Transistor with Parasitic Bipolar Action
N+ N+
VB
VDVS
VG
Electrons Injected WhenJunction Is Forward Biased IC
ISUB
IB
DepletionBoundary
ImpactIonization
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Equivalent Circuit of the NMOS Devices Including Parasitic Bipolar Mechanism
D
G
S
Sub
IDT
Ih,gen
IC
ID
IBIsub
Rsub
IE
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Important Issues for MOS ESD Compact Modeling
• Substrate resistance• Impact ionization and substrate current• Parasitic bipolar transistor• Implementation into SPICE platform
The following are needed in addition to the standard MOS model:
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Substrate Resistance Modeling
x
y0
HL
Xsd
Inversion layer
LS+0.8*L
Xdm
X1
DrainSourceXj
Xdd
m
LS
Subregion 2
Subregion 3
Subregion 1
LD
Averaged y position
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Substrate Resistance Modeling
6.6 6.9 7.2 7.5 7.8 8.1 8.4
0.2
0.3
0.4
0.5
0.61.0
1.5
2.0
2.5
3.0
Vgs = 4V
Vgs = 3VVgs = 2V
Vgs = 1V
Present Model Spreading R[3] Atlas Simulation
Subs
trat
e R
esis
t( K
Ω)
Drain Voltage ( V )
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Substrate Current Modeling
0.0 0.1 0.2 0.3 0.4-10
-8
-6
-4
-2
0
2 Vgs = 1.0 V
Slope=-P2 ( P2=29.27653 )
ln(P1)=1.85915
ln(1
-1/M
)
1/(Vds-η*Vdsat)
)exp(1
12
1dsatds VV
PP
M
−−⋅−
=
0 1 2 3 4 5 6
1.2
1.4
1.6
1.8
2.0
2.2
2.4 Present Model Conventional Model Fitting Curve
ln( P
1 )
Vgs (V)
0 1 2 3 4 5 6
22
24
26
28
30
32
34
36 Present Model Conventional Model Fitting Curve
P 2
Vgs (V)
321 007.0006.03.01.2))(ln( gsgsgsgs VVVVP ⋅+⋅−⋅−=
322 08.05.18.73.35)( gsgsgsgs VVVVP ⋅−⋅+⋅−=
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Substrate Current Modeling
0 1 2 3 4 5 6 70
10
20
30
40
50
60
70W/L=160/1.2µmVds=5.0 VVbs=0 V
Present model Experiment Existing model [14] Existing model [15] Existing model [16] Existing model [17]
Subs
trat
e C
urre
nt (µ
A)
Vgs (V)
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Parasitic Bipolar Transistor Modeling
0.5 0.6 0.7 0.8 0.9
1E-7
1E-6
1E-5
1E-4
1E-3
0.01
Measured IS-nF-fit
IS=2.50E-13 nF=1.14
I C (A
)
VBE (V)
)1()1( // −+−= kTnqVSE
kTnqV
F
SB
EBEFBE eIeI
Iβ
)]1()1[( // −−−= kTnqVkTnqV
qB
SC
EBCFBE eeNI
IkMF =−⋅ )1(β
In the snapback region:
21 ≤≤ k 18.1=M
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Outline
• Overview of electrostatic discharge (ESD)• ESD protection scheme• MOS compact modeling for ESD
applications• Implementation into Cadence SPICE• Results• Conclusions
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D
GE
N
BC MD
S
G
Pn
D
GS
gnd!
gnd
Block of RSUB
Block of Generation Hole current source
+ -
L=7.5uHV = HBM
Charging voltager
= 1.
5K
C =
2pF
C =
100
pF
C =
2pF
r =
100K
Extend R and C for ESDProtection Circuit
Equivalent Circuit of ImprovedSPICE MOS Model
HBM Equivalent Circuitof with Parasitic Elements (C,L)
Macrmodeling implementation via AHDL for the supply clamp subject to HBM stress
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Outline
• Overview of electrostatic discharge (ESD)• ESD protection scheme• MOS compact modeling for ESD
applications• Implementation into Cadence SPICE• Results• Conclusions
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0 2 4 6 8 10 120
20
40
60
80
100
120
~600µAVgs=0VVgs=1V
Vgs=2V
Vgs=3V
Vgs=4V
Device=160µm/1.2µm Present Model Simple Model TLP Measurement
Dra
in C
urre
nt (m
A)
Drain Voltage (V)
Simulated and Measured I-V Curves of MOSFET
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0 100 200 300 400 5000.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
HBM Charging Voltages increasing from 400 to 1000V
Present Model HBM Tester Measurements
Dra
in C
urre
nt (A
)
Transient Time (ns)0 100 200 300 400 500
0
3
6
9
12
15
18Charging voltages from 400 to 1000V
HBM Tester Measurements Present Model
Dra
in-S
ourc
e V
olta
ge (V
)Transient Time (ns)
Comparison of Measured and Simulated Transient Response of Supply Clamp
The ability to predict the peak drain current and holding drain-source voltage is critical for the design of a robust ESD protection structure
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0 100 2000
2
4
6
8
10
12
14
16
18 P5100
Dra
in V
olta
ge (V
)
Time (ns)
0 100 200
0
5
10
15
20
25P6106
Dra
in V
olta
ge (V
)
Time (ns)
0 100 2000
2
4
6
8
10
12
14
16
18
20 P6131
Dra
in V
olta
ge (V
)
Time (ns)
Source of drain voltage oscillation
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0 100 200 300 400 5000
3
6
9
12
15
18 Charging voltages are and 800 and 1000 V
Present Model Simple Model A Simple Model BD
rain
-Sou
rce
Vol
tage
(V)
Transient Time (ns)
Simple Model A: lumped Rsub = 2000 Ω and constant P1 = 8.4 and P2 = 35.36 for MSimple Model B: lumped Rsub = 2000 Ω and constant M = 1.05
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Main challenge for designing ESD protection structure for RF applications
• All active components in the ESD protection structure (i.e., MOSFET and diodes) must have a relatively large area to withstand the large power dissipation associated with the ESD stress
• The large device size leads to a large parasitice capacitance and thus a degradation in the RF performance of the core circuit being protected
How to design a robust ESD protection structure with a minimal parasitice capacitance?
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RF performance including the ESD parasitic
LNA circuit (P1-P4 are SCR-based ESD devices)
K. Higashi et al., 2002 IEEE Radio Freq. IC Symp., p. 285
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RF performance including the ESD parasitic
2.4 GHz LNA circuit for Bluetooth
A. Z. Wang et al., 2002 IEEE Custom Integrated Circuit Conf., p. 411
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Conclusions• ESD protection for microchips is increasingly
important in modern electronics• Background of ESD mechanisms and a compact
MOS model has been developed for ESD applications
• The model has been successfully implemented into Cadence SPICE and verified against measured data obtained from the TLP technique and HBM tester
• More work is needed to increase the robustness and decrease the parasitics of ESD protecion structures for RF applications