Compact model of Negative

Capacitance MOSFETs (NCFETs)

Ujwal Radhakrishna, Prof. Asif Khan

Prof. Sayeef Salahuddin and Prof. Dimitri Antoniadis

MIT, Georgia Tech, and U. C. Berkeley

MVSNC model

L-K equation for FE-oxide and MVS model for MOSFET

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Table of Contents INTRODUCTION ................................................................................................................................................................................. 3

NCFET: WORKING PRINCIPLE ............................................................................................................................................................. 3

OPERATING PRINCIPLES FOR FE-OXIDE .............................................................................................................................................. 4 Isolated ferroelectric capacitor ......................................................................................................................................................... 4 Impact of DE-leakage ........................................................................................................................................................................ 6 Implementation in QF=f(VF) form ....................................................................................................................................................... 7 Implementation in VF=f-1(QF) form .................................................................................................................................................... 8 Stabilizing the NC-state in ferroelectric capacitor ........................................................................................................................... 10 Impact of DE-leakage on the stability the NC-state in ferroelectric capacitor-CD combination ...................................................... 11

MVS MODEL FOR UNDERLYING FET ................................................................................................................................................. 12 Terminals and voltage definitions ................................................................................................................................................... 12 Introduction ..................................................................................................................................................................................... 13 Drain current model ........................................................................................................................................................................ 13 Terminal Charges ............................................................................................................................................................................ 14 Ballistic charges (Parabolic profile) ................................................................................................................................................. 15 Drift-diffusion non-velocity saturated (DD-NVSAT) charges ........................................................................................................... 15 Outer-fringing and inner-fringing charges ...................................................................................................................................... 16 Body charge ..................................................................................................................................................................................... 17

GATE-CHARGE FROM MOSFET DETERMINING VOLTAGE ACROSS FE-OXIDE .................................................................................... 17

TIME CONSTANTS ASSOCIATED WITH FE-OXIDE .............................................................................................................................. 17 Switching time-constant of FE-oxide polarization dipoles............................................................................................................... 17 Time-constant for FE-oxide leakage ................................................................................................................................................ 18

MVSNC MODEL PARAMETERS ......................................................................................................................................................... 18 FE-oxide parameters ....................................................................................................................................................................... 18 Si-FET parameters ........................................................................................................................................................................... 18 Parameter combination for leakage scenarios ............................................................................................................................... 19

SIMULATION RESULTS ..................................................................................................................................................................... 20 Si-FET device-level simulations ........................................................................................................................................................ 20 NCFET device-level IV simulations ................................................................................................................................................... 21 NCFET device-level CV simulations .................................................................................................................................................. 22 NCFET circuit-level simulations........................................................................................................................................................ 23

CONCLUSIONS ................................................................................................................................................................................. 25

REFERENCES .................................................................................................................................................................................... 26

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Introduction A Negative Capacitance FET (NCFET) with a ferroelectric (FE) material used as the gate oxide can operate at a subthreshold swing

less than the fundamental Boltzmann limit of 60 mV/decade [1]–[5]. In the last few years, a number of proof-of-concept

demonstrations of negative capacitance have been achieved [6]–[11]. In addition, sub-60 mV/decade operation has been

experimentally demonstrated in the bulk and FinFET device structures with both integrated FE gate oxides [12]–[17] and with

externally connected FE capacitors [18]–[20].

Compact models for NCFETs are necessary to study the static and dynamic behavior of the device along with the device-

performance in circuits and systems. Furthermore, effects such as dielectric-leakage in the gate-stack and inherent switching speed

associated with the dipoles in FE-oxide are yet to be understood. The compact model developed at MIT for these devices and

described in this release uses Landau-Khalatnikov equation for describing the FE-oxide [21] and MVS model [22]-[23] for the

underlying Si-MOSFET. The compact model is called MIT Virtual Source Ferroelectric (MVSNC) model and has been used as a tool to

understand the implications of aforementioned effects on the device-level as well as circuit and system-level performance [21], [24].

Several compact models of NCFETs have been reported [25]-[26] but either they are empirical or do not capture all the device-level

behavioral nuances that is described by MVSNC model. In this report, details of model equations along with parameter extraction

procedure are explained.

NCFET: Working principle The underlying mechanism for sub-60 mV/decade operation of an NCFET is the passive amplification of the gate voltage at the

interface between the FE gate oxide and the semiconductor channel. Essentially, the charge balance between two series capacitors

(FE and semiconductor) leads to a depolarization field that stabilizes the FE at a state of negative capacitance that in turn amplifies

the surface potential of the semiconductor. Given that the charge balance is critical in the overall performance of the device, it has

been extensively discussed in the literature for many different types of device configurations [27]–[42]. Two of the most important

aspects of a negative capacitance FET (NCFET) are amplification and stabilization [43]-[44]. The differential amplification of the gate

voltage at the interface between the semiconductor channel and the gate oxide underlies the sub-60 mV/decade operation of a

NCFET. On the other hand, negative capacitance is unstable by nature, and, when properly designed, the positive capacitances in the

device structure can stabilize the ferroelectric in its negative capacitance state leading to a stable amplification.

Fig.1: The schematic diagram and the equivalent circuit model of a NCFET with an intermediate metallic layer. An Intel 45nm n-type

bulk FET is used as the baseline FET. The ferroelectric thickness tFE, coercive field EC and remnant polarization P0 are 5 nm, 800 kV/cm

and 8 C/cm2, respectively. The anisotropy coefficients of the ferroelectric based on these parameters are calculated using the

relations presented in Ref. [21]. The area of the ferroelectric is set equal to the area of the channel of the baseline FET.

The structure of a NCFET shown in Fig. 1. The purpose of the intermediate metallic layer (as originally intended in Ref. [43]-[44]) is to

average out the non-uniform potential profile along the source-drain direction and any charge non-uniformity coming from domain

formation in the ferroelectric, thereby, making the single-domain Landau-Khalatnikov based description of the system a valid one.

RFE represents the leakage through the ferroelectric layer. In the equivalent circuit model, there should, in principle, be two

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additional resistors connected between the internal metal gate and source and drain terminals representing the leakage through the

high K-oxide layer. In this model, we assume that the gate-to-source/drain resistances are significantly larger than RFE, and, hence,

are ignored.

The baseline MOSFET used in the model represents a CMOS p-type/n-type FET with parameters calibrated against Intel 45 nm n-type

bulk FET, which is modeled using the MIT Virtual Source (MVS) compact device model (key device model equations and parameters

are listed in ref. [22]). The ferroelectric layer is modeled using the Landau-Khalatnikov equation, which is detailed in Ref. [21]. In the

following sections, details of operating physics and model equations formulated for both FE-oxide and baseline FET will be

highlighted.

Operating principles for FE-oxide A ferroelectric material is characterized by an “S”-shaped charge (QF)-voltage (VF) characteristic shown in Fig. 2. Here, the

ferroelectric charge QF represents the actual charge across the ferroelectric due to its polarization. Fig. 2 (a) shows the experimental

charge-voltage characteristics for a typical FE-oxide material (DE-HZO: Hafnium Zirconium oxide) given in [45]. The characteristics

exhibit regions with negative differential slope in the P-E (polarization charge vs. Electric field) or QF- VF curves representing negative

capacitance behavior in certain voltage (VF) regimes. This is the key to the operation of the NCFET device as will be explained later

and is captured by the Landau-Khalatnikov (L-K) equation that approximates the observed P-E characteristics of the FE-oxide by the

“S”-shaped characteristics shown in Fig. 2b.

Fig.2: (a) Hysteresis loops of polarization versus E-field (P-E) for FE-HZO and DE-HZO with physical thickness 1.5nm. The negative

slope of dP/dE indicates a shortcut path with NC effect. The slope of the P-E is positively correlated with dielectric constant, and it

indicates that FE-HZO has higher K value than that of DE-HZO. (b) QF –VF characteristics obtained from L-K equation showing negative

differential slope (negative capacitance) regions.

Isolated ferroelectric capacitor The dynamic characteristics of an isolated FE capacitor directly connected to a voltage source VS as shown in Fig. 3(a) is characterized

by using the L-K equation described in this subsection. Following the Landau–Khalatnikov equation [21], the rate of change in

polarization charge QF = PA in the FE, where P is the polarization and A is the cross-sectional area, can be written as:

𝜌𝑑𝑄𝐹

𝑑𝑡= −

𝑑𝑈

𝑑𝑄𝐹

(1)

Here, ρ > 0 signifies the frictional inertia of the system and U (in electron volts) is the free energy of the FE material that can be

written as

𝑈 = 𝛼

2𝑄𝐹

2 + 𝛽

4𝑄𝐹

4 − 𝑄𝐹𝑉𝐹 (2)

Where α and β are anisotropy constants (α < 0) and VF is the voltage across the FE capacitor. For simplicity, we have only included up

to the fourth order of QF, which corresponds to a second-order phase transition. Combining (1) and (2) one finds

𝑉𝐹 = 𝜌𝑑𝑄𝐹

𝑑𝑡+ (𝛼𝑄𝐹 + 𝛽𝑄𝐹

3) (3)

(a) (b)

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Which in the steady state results in

𝑉𝐹 = (𝛼𝑄𝐹 + 𝛽𝑄𝐹3) (4)

Equation (4) results in the “S”-shaped QF –VF characteristics in steady state, which is plotted is Fig. 3(b).

Fig.3: (a) Isolated FE connected to a voltage source VS. (b) QF –VF characteristics obtained from (4). (c) dQ/dt as a function of QF in an

isolated FE. Only QF = ±Q0 states are dynamically stable. Here Vc=Ec tFE.

We note in Fig. 3(b) that dQF /dVF is negative in the range −QC < QF < +QC. Fig. 3(c) shows the behavior of dQF /dt as a function QF at

VF=0. It is observed that dQF /dt = 0 at three different values of QF : QF = −Q0, 0, and + Q0, which correspond to the solutions of (4). If

one starts at QF = + Q0 or −Q0, a small perturbation increases (decreases) QF, dQF /dt becomes negative (positive), which pushes QF

back to QF = + Q0 or −Q0, respectively. This points to the fact that QF = + Q0, and −Q0 are dynamically stable solutions of (4). This

situation is illustrated by the convergent arrows around QF = + Q0 or - Q0 points in Fig. 3(c). On the other hand, starting at QF =0, if a

small perturbation increases (or decreases) QF, the sign of dQF /dt around QF=0 is such that QF will keep on changing until it reaches

+Q0 (or −Q0). This situation is illustrated by the divergent arrows at QF = 0 in Fig. 3(c). Hence, QF = 0 is a dynamically unstable solution

of (4). To put this into perspective, the above-mentioned analysis shows that negative capacitance is not a stable state in an isolated

FE capacitor. For such an isolated FE capacitor, the state of negative capacitance can only be accessed in time-dependent switching

experiments [45]. In light of this observation, a stabilization technique is necessary to access the negative-capacitance (NC) state but

the isolated FE-oxide can be modeled using the equation (3)-(4) as it is pertinent to modeling NCFETs that use FE-oxide.

The sub-circuit shown in Fig. 4 captures the FE-oxide capacitor in the MVSNC model. The resistor 𝜌 represents the frictional inertia

(𝜌 in equation (3)) and the non-linear capacitor element is modeled using equation (4). Since 𝑑𝑄𝐹

𝑑𝑡= 0 in static condition, 𝑉𝐺 =

𝑉𝐺,𝑖𝑛𝑡1 and 𝜌 has no impact. The voltage difference between 𝑉𝐺,𝑖𝑛𝑡1 and 𝑉𝐺,𝑖𝑛𝑡 is governed by (4) since 𝑉𝐹 = 𝑉𝐺,𝑖𝑛𝑡1 − 𝑉𝐺,𝑖𝑛𝑡. In the

MVSNC model, we assumed coercive field EC = 800 kV/cm, FE thickness tFE = 5 nm, area A = 45 nm × 1 μm, and the remnant

polarization Q0 =8 μC/cm2 × A. This is relevant for DE-HZO since based on these parameters, the anisotropic constants are calculated

using the following equations [21] with values that are consistent with those measured for HZO.

𝛼 = −3√3

2

𝑉𝐶

𝑄0

; 𝛽 =3√3

2

𝑉𝐶

𝑄03 (5)

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Fig.4: The sub-circuit modeling approach adopted in MVSNC model to describe the behavior of FE-oxide. The non-linear capacitance

element is modeled using equation (4) that captures the static behavior of L-K equation. The series resistance captures the inertia

of dipole switching. The parallel RFE resistance captures the DE-leakage which affects the stability of NC-state of FE-oxide.

Impact of DE-leakage The MVSNC model captures DE-leakage using the element RFE as shown in Fig. 4 in parallel to the ideal non-leaky FE-oxide elements. As such due to leakage in the ferroelectric layer, the voltage across the ferroelectric is determined by RFE at the steady state and it is always zero, i.e. the voltage at the external gate VG appears at the internal gate (i.e: VG,int = VG). The “S”-shaped charge (QF)-voltage (VF) characteristic shown in Fig. 3(b), where the ferroelectric charge QF represents the actual charge across the ferroelectric due to its polarization gets modified under leakage. In the presence of leakage in a series network with an intermediate metallic layer, the effective ferroelectric charge Q–the amount of charge that gets transferred to the ferroelectric capacitor from the voltage source and that the series positive capacitor actually “sees”–is different from QF [24]. The Q-VF characteristics can be obtained by shifting the corresponding QF -VF curve along Q-axis by an amount equal to the initial charge across the ferroelectric capacitor, Qoffset [24]. As explained in the previous paragraph, since VF (t = 0)=0 due dielectric-leakage (through RFE ), Qoffset = QF (VG = 0). When the metals across the ferroelectric layer have the same work function, QF -VF is anti-symmetric with respect to the VF = 0 line (black curve in Fig. 5(a)), and the corresponding QF-VF curve (black curve in Fig. 5(b)) is obtained by shifting it by Q0, Q0 being the remnant polarization. This (black) curve is referred as the nominal one. The QF-VF curve can also be shifted along the VF -axis by utilizing electrodes with dissimilar work-functions across the ferroelectric, defect dipole formation and strain gradients [24]. The red curve in Fig. 5(a) represents the QF-VF curve for such a case, where it is shifted by Voffset with respect to the ideal QF-VF characteristics. The corresponding QF-VF curve under leakage is represented by the red curve in Fig. 5(b), which we refer to as the engineered charge-voltage characteristics. The engineered charge-voltage characteristics is important for designing a high performance leaky NCFET and will be explained later. These nuances associated with leakage is modeled in the MVSNC model as explained in following subsections.

Fig.5: The actual charge-voltage (QF-VF) (a) and the effective charge-voltage (QF-VF) (b) characteristics of the ferroelectric for the ideal

case (black curve) and the engineered case (red curve) under leakage.

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Implementation in QF=f(VF) form The non-linear capacitor depicted in Fig. 4 is representative of the static behavior of FE-oxide capacitor element which can be

modeled as a charge dependent voltage source in MVSNC model given by following equations:

Ferroelectric Landau coefficients of FE-oxide

a1_p = -3.0 * sqrt(3.0) /4.0 * Ec/ P0; a2_p = 3.0 * sqrt(3.0) / 8.0 * Ec/ ( P0 * P0 * P0 ); a3_p = 0; a4_p = 0;

Here P0 is Q0 in equation (5), a1_p is 𝛼/2𝑡𝐹𝐸 , a2_p is 𝛽/4𝑡𝐹𝐸 , where 𝛼 and 𝛽 are given by Eq. (5). For completeness the third and

fourth co-efficient a3_p and a4_p are also included but set to 0 for simplicity. The appropriate equations can be added if further

accuracy requirements are needed to represent the static portion of L-K equation instead of the simplified form of Eq. (5).

Work function engineering

Qbias = tipe * dir * Qoffset * P0;

Qbias3 = Qbias * Qbias * Qbias;

Qbias4 = Qbias3 * Qbias;

Vbias = wfeflag * tfe * (2 * a1_p * Qbias + 4 * a2_p * Qbias3 + 6 * a3_p * Qbias3

* Qbias * Qbias + 8 * a4_p * Qbias4 * Qbias3); Here Vbias is the voltage offset (Voffset) achieved in the QF -VF curve in Fig. 5 from work-function engineering (WFE) and Qbias is

charge-per unit area. Qoffset is an input parameter that can be adjusted to define the extent of work-function engineering and set

the presence of leakage. wfeflag is an input flag which when set to 1 activates WFE by shifting the QF -VF curve along the voltage axis.

WFE to mitigate the effect of leakage in transient operation of NCFET which will be explained in the simulation section later. The

parameters dir and tipe indicate the polarity of charge and current depending on whether the NCFET is p-type/n-type as well as

operating regime (forward or reverse). This is determined by the underlying S-FET and will be explained later.

Impact of DE-Leakage with work-function engineering

Qinit = (1e-4 * (Lgdr - dLg) * W ) * (Qbias); The shift in charge axis in QF -VF curve due to leakage is captured by Qinit above. This represents the red-curve of Fig. 5b to

represent the most generic case of leakage with WFE. The total charge is computed by multiplying with cross-section area of the

gate-stack of NCFET determined by the device width W and effective gate-length (Lgdr-dLg) (both in cm) which are input parameters.

Charge-voltage characteristics

Finally the full QF -VF curve is implemented in QF =f(VF) form as a charge-controlled voltage source below, including the effects of

leakage and WFE to mitigate it.

Qnet = Qgfe - Qinit;

Qfe = Qnet / (1e-4 * (Lgdr - dLg) * W );

Qfe3 = Qfe * Qfe * Qfe;

Qfe4 = Qfe3 * Qfe;

Efe = 2 * a1_p * Qfe + 4 * a2_p * Qfe3 + 6 * a3_p * Qfe3 * Qfe * Qfe + 8 * a4_p

* Qfe4 * Qfe3;

Vfe = Efe * tfe + Vbias;

V(gint1 , gint) <+ Vfe; The last statement above implements the static portion of L-K equation of Eq. (5) representing FE-oxide as a charge-dependent

voltage source connected between the nodes gint1 and gint as shown in the sub-circuit of Fig. 4. The Qgfe variable above is the

charges of the gate of underlying MOSFET that determine the state of FE-oxide. The charge Qgfe is computed in the MVS model and

is a function of external gate and drain voltages as explained in the section describing the MVS model later.

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Implementation in VF=f-1(QF) form The implementation of FE-oxide static behavior as described in the previous subsection while is easy to implement in Verilog-A

language may not capture the full-impact of the “folding” (NC-region) in the “S”-shaped QF -VF curve in circuit-level IV simulations of

NCFETs. The reason for this is that QF -VF curve in the folded region is a many-one function with three solutions of QF for each VF in

the curve. This is reflected as hysteresis in the IV curves of NCFETs and the folding in the IV curve is not captured by numerical

circuit simulators unless robust numerical tools such as homotopy are incorporated in the numerical circuit simulators. Apart from

the MAPP software developed in the NEEDS platform, we do not see the algorithm implemented in commercial circuit simulators. So,

it may be useful to also look into the inverse function implementation of the QF -VF curve. This form described in this section is

purely for the sake of completeness and while has been implemented in Verilog-A, is not included in this release.

The static portion of the L-K equation with higher order terms ignored (without leakage and WFE) can be written as

𝑉𝐹 = (𝛼𝑄𝐹 + 𝛽𝑄𝐹3) (6)

To invert this function and find the three roots, we adopt the approach followed in [45]. The above equation is of the form

(7)

With 𝐴 = 𝛼/𝛽 and 𝐵 = −𝑉𝐹/𝛽. The solution to Eq. (7) depends upon the sign of the discriminant:

(8)

D may be zero, greater than zero, or less than zero. The solution to equation (7) for each of these three cases is now shown.

Case 1: For D > 0, equation (7) has one real root and two imaginary roots. The real root is given by:

𝑦1 = −(𝑀 + 𝑁) (9)

where,

(10) This represents single solution PC-state region of the QF-VF curve of the static behavior of the FE-oxide.

Case 2: For D = 0, there are three real roots and at least two are equal. Since both A and B can be positive as well as negative, D can

become zero either by A and B simultaneously becoming zero, or by the constituent terms canceling each other. When A and B are

both zero, then there are three equal roots. This is an inflection point and is the case when predicting the critical point with a cubic

equation of state. The three real roots are given by:

𝑦1 = (𝑀 + 𝑁) (11a)

(11b)

Case 3: For D < 0, there are three, distinct, real roots which are given by the following trigonometric functions:

(12)

where, i = 1, 2, or 3, k = 0, 1, or 2, and,

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(13) This represents the NC-state region of the FE-oxide capacitor with three real roots. Exact implementation of this form will yield the

full solution of the QF-VF curve of the static behavior of the FE-oxide.

Verilog-A implementation of the inverse function

Vfe = V(gint1,gint); A = a1_p / 2.0 / a2_p; B = - Vfe / (4.0 * a2_p * tfe); D = A * A * A /27.0 + B * B /4.0; Qc = sqrt ( - a1_p / 6.0 / a2_p ); if ( D >= 0) begin M = pow(abs( -0.5 * B + sqrt(D) ), (1.0/3.0)); N = pow(abs( -0.5 * B - sqrt(D) ), (1.0/3.0)); if ( Vfe > 0) begin Qfe = M + N ; end else begin Qfe = - ( M + N ) ; end end else begin if ( B == 0) begin phi = 0.5 * `M_PI /3.0; end else begin phi = atan( -sqrt(-D)/ ( 0.5 * B ) )/ 3.0; end amp = 2.0 * sqrt(-A/3.0); if ( Vfe > 0) begin Qub = amp * cos(phi); Qun = amp * cos(phi + 2.0 * `M_PI * 2.0 /3.0); Qlb = amp * cos(phi + 1.0 * `M_PI * 2.0 /3.0); if( Qg/(W * Leff * 1e-4) <= -Qc ) begin Qfe = Qlb; end else begin if( (Qg/(W * Leff * 1e-4)) < 0 ) begin Qfe = Qun; end else begin Qfe = Qub; end end end else if (Vfe< 0) begin Qub = -amp * cos(phi + 2.0 * `M_PI *120.0 / 180.0); Qun = -amp * cos(phi + 1.0 * `M_PI *120.0 / 180.0); Qlb = -amp * cos(phi); if( Qg/(W * Leff * 1e-4) <= Qc) begin

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if( (Qg/(W * Leff * 1e-4)) > 0 ) begin Qfe = Qun; end else begin Qfe = Qlb; end end else begin Qfe = Qub; end end else if (Vfe==0.0)begin Qub = amp * cos(phi); Qun = amp * cos(phi + 2.0 * `M_PI *120.0 / 180.0); Qlb = amp * cos(phi + 1.0 * `M_PI * 2.0 /3.0); if( Qg/(W * Leff * 1e-4) <= Qc) begin if( (Qg/(W * Leff * 1e-4)) >=0 ) begin Qfe = Qun; end else begin Qfe = Qlb; end end else begin Qfe = Qub; end

end end

Fig.6: Verilog-A implementation of the inverse QF-VF function QF=f-1(VF) which gives all three regions in ADS® simulator and the

solution that is required based on the state-function Qg which should be an input parameter.

While this implementation is feasible in Verilog-A it is not recommended since we will have to resort to using state-variables (in this

Qg) to get the desired solution. There is also the added issue of derivatives at the boundary between two solutions which is not good

from circuit simulation point of view. As mentioned earlier, the inverse implementation is presented here for the sake of

completeness. The FE-oxide discussed so far cannot be stabilized in its NC-state under stand-alone conditions. It requires a

stabilizing capacitance in series to stabilize the NC-state which is discussed in detail in the next section.

Stabilizing the NC-state in ferroelectric capacitor The FE-oxide capacitor in standalone condition does not reach the NC-state since it is unstable as discussed at the beginning of this

section. We require a series combination of an FE capacitor and a linear positive capacitor CD connected to a voltage source VS,

which is schematically shown in Fig. 7(a). Salahuddin and Datta showed that, if CD < −1/α, the entire negative capacitance region of

the QF –VF curve gets stabilized and this results in a voltage amplification at the internal node without any hysteresis [1]. To

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understand this, we again resort to the dynamic stability analysis. Because of the series combination, the charge, Q, in the DE

capacitor, CD is the same as that (QFE) in the FE capacitor: QFE = EA + QF = Q, where E is the electric field in the DE. For simplicity, we

will assume that QF>>EA, so that QF ≈ Q. Using this relation, one can write the following expression for VS:

𝑉𝑆 = 𝜌𝑑𝑄𝐹

𝑑𝑡+ (𝛼 +

1

𝐶𝐷) 𝑄𝐹 + 𝛽𝑄𝐹

3 (14)

In (14), we have used the relations VF = VS − VD, where VD is the voltage across the DE and VD = Q/CD ≈ QF /CD. In Fig. 7(b), the plot of

dQF /dt as a function of QF at VS=0. For the DE capacitor, we have chosen a relative DE constant of 4 and a thickness of 10 nm, which

makes CD < −1/α. This makes the slope of the dQF/dt – Q negative [i.e., d/dQF (dQF /dt) < 0]. Consequently, in this series combination,

the state of negative capacitance becomes stable at QF =0.

Fig.7: (a) A series combination of an FE and a DE capacitor. The capacitors are perfectly insulating. (b) dQ/dt as a function of QF in

perfectly insulating FE–DE series combination without an internal metallic layer. For CD < −1/α, QF = 0 state is dynamically stable.

Since a series stabilizing capacitance CD is necessary to achieve and stabilize NC-state in FE-capacitor, in NCFET the gate-stack

capacitance (without external fringing capacitance) plays the role of CD. However this CD is bias-dependent non-linear gate-

capacitance of underlying MOSFET which is accurately captured in MVS model.. The last subsection deals with the impact of DE-

leakage on the stability of this series combination of CFE-CD.

Impact of DE-leakage on the stability the NC-state in ferroelectric capacitor-CD combination Next the impact of a leaky FE material on its stability can be analyzed even in the presence of a series positive capacitor CD. For this,

we consider the series combination shown in Fig. 7a along with the parallel resistors (RFE across FE-capacitor and RD across CD) that

represent leakage (nonlinear bias-dependent leakage currents can be included as well) and the equipotential connection facilitated

by the internal metal electrode, the charge across the FE (QF) and the DE capacitor (Q) no longer have to be equal to each other. We

assume that ρ << R, RF and hence ignore ρ.

Fig.8: dQF /dt as a function of QF in a series combination of a leaky FE and a leaky DE capacitor with an internal metallic layer. CD<1/α.

In the presence of leakage, QF = 0 state is dynamically unstable and only QF = ±Q0 states are dynamically stable.

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Applying Kirchoff’s current law at the internal node, we find the following relation:

𝑑𝑄𝐹

𝑑𝑡+

𝑉𝐹

𝑅𝐹𝐸= 𝐶𝐷

𝑑𝑉𝐷

𝑑𝑡+

𝑉𝐷

𝑅𝐷 (15)

Substituting VD = VS − VF and VF = αQF + βQF3

𝑑𝑄𝐹

𝑑𝑡=

𝐶𝐷𝑑𝑉𝑆

𝑑𝑡+

𝑉𝑆𝑅𝐷

−(1

𝑅𝐷+

1

𝑅𝐹𝐸)(𝛼𝑄𝐹+𝛽𝑄𝐹

3)

1+𝐶𝐷(𝛼+3𝛽𝑄𝐹2)

(16)

which, when VS = 0, leads to

𝑑𝑄𝐹

𝑑𝑡= − (

1

𝑅𝐷+

1

𝑅𝐹𝐸)

(𝛼𝑄𝐹+𝛽𝑄𝐹3)

1+𝐶𝐷(𝛼+3𝛽𝑄𝐹2)

(16)

Fig. 8 plots dQF /dt as a function of QF at VS = 0 for CD < −1/α. Notably, in the presence of leakage resistances, QF = 0 is no longer a

stable state, despite the series combination of an FE and a DE capacitor. In other words, Fig. 8. dQF /dt as a function of QF in a series

combination of a leaky FE and a leaky DE capacitor with an internal metallic layer. CD < −1/α. In the presence of leakage, QF = 0 state

is dynamically unstable and only QF = ±Q0 states are dynamically stable. The steady-state condition for the series combination

requires both the FE and DE capacitors to be in a state of positive capacitance at VS = 0. This is modeled in the form of shifted QF-VF

curve under leakage in Fig. 5b where under leakage the curve is shifted on the charge axis by Q0. This also re-emphasizes the need

for work-function engineering captured in the MVSNC model to overcome the limitations of leakage. The next section deals with the

modeling of baseline-MOSFET that stabilizes the NC-state of CFE and achieves steep sub-threshold swing.

MVS model for underlying FET The underlying MOSFET is captured by MVS model formulation that can be found in the NEEDS model list [22]. The manual for the

MVS-1 model equations and parameter list is given in the release and is repeated here for completeness.

Terminals and voltage definitions

Fig. 9: Schematic of the MOSFET with various terminals labeled. The current in the channel is labeled as Id. Id is positive when it flows from d to s terminal, while it is negative when it flows from s to d terminal.

Figure 9 shows the MOSFET schematic where external terminals are labeled as d (drain), gint (internal gate), s (source), b (body).

Internal gate and body terminals are the same as the external ones. Internal drain terminal is labeled as di, while internal source

terminal is labeled as si.

Voltage definitions

Vds = tipe*|V(d)-V(s)| Vgs = tipe*max(V(gint)-V(s), V(gint)-V(d)) Vgd = tipe*min(V(gint)-V(s), V(gint)-V(d)) Vbs = tipe*max(V(b)-V(s), V(b)-V(d)) Vdsi = tipe*|V(di)-V(di)| Vgsi = tipe*max(V(gint)-V(si), V(gint)-V(di))

P a g e | 13

Vdgi = tipe*min(V(gint)-V(si), V(gint)-V(di)) Vbsi = tipe*max(V(gint)-V(si), V(gint)-V(di)) Vgs_raw = tipe*(V(gint)-V(si)) Vgd_raw = tipe*(V(gint)-V(di))

Introduction Silicon MIT virtual source (Si-MVS) model is a semi-empirical model that describes the short-channel metal-oxide-semiconductor-

field-effect transistor (MOSFET) current versus voltage characteristics and is valid in all regions of operation with continuity of both

current and its derivatives (Khakifirooz, Nayfeh et al. 2009). The model also provides intrinsic charge descriptions that extend all the

way to the ballistic regime, where gradual channel approximation (GCA) is often violated. Rather than calculating all the inter-

terminal capacitances separately from the transport model (Chan, Hui et al. 1998), the intrinsic charges associated with each

terminal are calculated self consistently with the current model (Wei, Mysore et al. 2012). The MVS model maintains the advantage

of using only a limited number of input parameters, most of which have straightforward physical meanings and can be easily

measured from device characterization (Jeong, Antoniadis et al. 2009).

Drain current model When devices are scaled to the deep sub-micrometer regime, carriers in the transistor channel (electrons or holes) experience fewer

scattering events traveling along the channel (Lundstrom 2009). Depending on the channel length and material system of the

transistor, devices may operate in quasi-ballistic (QB) transport regime as opposed to the drift-diffusive (DD) transport regime

(Natori 1994), (Rhew, Ren et al. 2002). The drain current in the MOSFET can be described by the product of the local charge areal

density times the local carrier velocity at any point in the channel. It is particularly useful to write this expression at the location of

the “virtual source” (VS), i.e. the location at the top of the energy barrier (x = x0) as shown in Fig. 10 since it is easiest to compute the

charge density at the VS point.

Fig. 10: Schematic of a short-channel n-MOSFET with corresponding energy diagram. Virtual-source point x0 is shown in the figure. The carrier charge and density used throughout this work are defined at this point (at the peak of the conduction band profile).

To model the transition from saturation to linear regime of transport, an empirical function, Fsat, is used. Hence, the current Id

flowing from terminal d to terminal s (in Fig. 9).

𝐼𝑑 = 𝑊𝑄𝑖(𝑥0)𝑣𝑥0𝐹𝑠𝑎𝑡 (16)

Where Qi(x0) and vxo are the channel charge density and velocity, respectively, at the VS point. vxo is assumed to be independent

of bias voltages and is extracted from experimental data (Liu, Luisier et al. 2012). The VS charge density used for current

computation (Qinv_corr) is slightly different than that used for charge computation (Qinv). This was done to smoothen the second

derivative of Id with respect to Vds around Vds = 0 V.

The transition function Fsat is given as

𝐹𝑠𝑎𝑡 =𝑉𝑑𝑠𝑖/𝑉𝑑𝑠𝑎𝑡

(1+(𝑉𝑑𝑠𝑖/𝑉𝑑𝑠𝑎𝑡)𝛽)1/𝛽 (17)

where Vdsat is the saturation voltage given as

𝑉𝑑𝑠𝑎𝑡 = 𝑉𝑑𝑠𝑎𝑡𝑠 (1 − 𝐹𝐹) + 𝐹𝐹 𝜑𝑡 (18a)

P a g e | 14

𝑉𝑑𝑠𝑎𝑡 = 𝑣𝑥0𝐿𝑒𝑓𝑓/𝜇0 (18b)

𝐹𝐹 =1

1+exp ((𝑉𝑔𝑠𝑐𝑜𝑟𝑟−𝑉𝑡𝑝)

𝑎𝑝ℎ𝑖𝑡) (18c)

𝑉𝑡𝑝 = 𝑉𝑡0𝑏𝑠 − 𝛿𝑉𝑑𝑠𝑖 − 0.5 𝑎𝑝ℎ𝑖𝑡 (18d)

𝑉𝑡0𝑏𝑠 = 𝑉𝑡0 + 𝛾 (√𝜑𝑏 − 𝑉𝑏𝑠𝑐𝑜𝑟𝑟 − √𝜑𝑏) (18e)

where the factors Vgscorr and Vbscorr are explained later. The term aphit =alpha×𝝋𝒕 and nphit = n×𝝋𝒕, and other variables are

explained in parameter list in Table I. phit= k×Tjun/q is the thermal voltage, where k is the Boltzmann constant and q is the

electronic charge. The term FF is used for Fermi function. In the next sub-sections, equations pertaining to the computation of

Qinv_corr, Vgscorr, and Vbscorr are explained.

Computation of Qinv_corr

Qinv_corr = Qref×ln( 1 + exp(eta) )

Qref = Cg×nphit

n = n0 + nd×Vdsi

eta = Vgscorr − Vt0bs −δVdsi − aphit ×FF

nphit

Where Vt0bs and FF are given as in Eq. (18c)-(18e).

Computation of Vgscorr and Vbscorr

Vgscorr = Vgsi + Vcorr,

Vbscorr = Vbsi + Vcorr

Vcorr = (1+2 δ)ab

2exp (−

𝑉𝑑𝑠𝑖

𝑎𝑏)

ab = 2 (1 − 0.99FFpre) 𝜑𝑡

FFpre = 1

(1+ exp (𝑉𝑔𝑠−𝑉𝑡𝑝𝑐𝑜𝑟𝑟

1.5 𝑎𝑝ℎ𝑖𝑡))

Vtpcorr = 𝑉𝑡0 + 𝛾 (√𝜑𝑏 − 𝑉𝑏𝑠 − √𝜑𝑏)

Note that the correction factor Vcorr is computed from external Vgs and Vbs but internal Vdsi. The impact of access-region

resistances on current computation is modeled as

𝐼(𝑑, 𝑑𝑖) =𝑉(𝑑)−𝑉(𝑑𝑖)

𝑅𝑑 (19a)

𝐼(𝑠, 𝑠𝑖) =𝑉(𝑠)−𝑉(𝑠𝑖)

𝑅𝑠 (19b)

where I(d,di) is the current flow between terminals d and di, I(s,si) is the current flow between terminals s and si, Rd = Rd0/W and

Rs=Rs0/W. Equations (16)-(19) determine the transport in the channel.

Terminal Charges For dynamic operation, the channel charge behavior must be accounted for in the device model. The time-dependent variation in

the channel charge is supplied by displacement currents through the device terminals (Tsividis 1999) that, obviously, cannot be

predicted by the static transport theory. The intrinsic charges associated with each terminal are computed self consistently with the

transport model. The model terminal charges can produce the full matrix of capacitive components and their voltage dependences.

The partitioning of charges at the source terminal (Qs) and the drain terminal (Qd) is accomplished through the Ward-Dutton charge-

partitioning scheme (Ward 1981) that is universally true as long as the device operates under quasi-static conditions.

P a g e | 15

𝑄𝑠 = 𝑊 ∫ (1 −𝑥

𝐿𝑒𝑓𝑓) 𝑄𝑖(𝑥)𝑑𝑥

𝑥=𝐿𝑒𝑓𝑓

𝑥=0 (20a)

𝑄𝑑 = 𝑊 ∫ (𝑥

𝐿𝑒𝑓𝑓) 𝑄𝑖(𝑥)𝑑𝑥

𝑥=𝐿𝑒𝑓𝑓

𝑥=0 (20b)

Where Qi(x) is the position-dependent inversion charge density along the channel.

Ballistic charges (Parabolic profile) To compute Qi(x) in ballistic transport regime, current continuity and energy balance are used along the channel. Using a Parabolic

potential profile along the channel, the charge Qi(x) is given as

𝑄𝑖(𝑥) =𝑄𝑖𝑛𝑣

√1+𝑘(𝑥

𝐿𝑒𝑓𝑓)

2 ; 𝑘 =

2𝑞𝑒𝑉𝑑𝑠𝑖

𝑚𝑒𝑣𝑥02 (21)

To compute terminal charges, Qinv, will be used instead of Qinv_corr that is used in computation of current. Qinv is computed from

the same set of equations above but with Vgscorr replaced with Vgsi, Vbscorr replaced with Vbsi. Qinv is given as

𝑄𝑖𝑛𝑣 = 𝑄𝑟𝑒𝑓ln (1 + exp (𝑉𝑔𝑠𝑖−(𝑉𝑡0𝑏𝑠0−𝛿𝑉𝑑𝑠𝑖−𝑎𝑝ℎ𝑖𝑡 𝐹𝐹𝑝𝑟𝑒)

𝑛𝑝ℎ𝑖𝑡) (22a)

𝑉𝑡0𝑏𝑠0 = 𝑉𝑡0 + 𝛾(√𝜙𝑏 − 𝑉𝑏𝑠𝑖 − √𝜙𝑏) (22b)

Using Eq. (21) in (22a-b) and carrying out the integration,

𝑞𝑠𝑏 = 𝑄𝑖𝑛𝑣(sinh(𝑘𝑞)

𝑘𝑞−

√𝑘𝑞2+1−1

𝑘𝑞2) (23a)

𝑞𝑑𝑏 = 𝑄𝑖𝑛𝑣(√𝑘𝑞2+1−1

𝑘𝑞2) (23b)

𝑘𝑞 = √2𝑞𝑒𝑉𝑑𝑠𝑖

𝑚𝑒𝑣𝑥𝑜2 ; 𝑘𝑞2 = 𝑘𝑞 (23c)

Drift-diffusion non-velocity saturated (DD-NVSAT) charges In the non-saturation region of operation, Vds is generally small, and the potential profile in the channel is wider and flatter than in

saturation conditions. Under such conditions, carrier transport approaches drift/diffusion conditions dominated by mobility, as

opposed to velocity for operation in saturation. The charges in the DD-NVSAT regime are given as (Tsividis 1999). Here psis denotes

the surface potential solution in weak inversion.

𝑞𝑠𝑐 = 𝑄𝑖𝑛𝑣(6+12𝑥+8𝑥2+4𝑥3

15 (1+𝑥)2 ) (23a)

𝑞𝑑𝑐 = 𝑄𝑖𝑛𝑣(4+8𝑥+12𝑥2+6𝑥3

15 (1+𝑥)2 ) (23b)

Where x=1-Fsatq with other minor equations given by the following lines in code

Computation of DD-NVSAT charge aiding equations

Fsatq = 𝑉𝑑𝑠𝑖/𝑉𝑑𝑠𝑎𝑡𝑞

(1+(𝑉𝑑𝑠𝑖/𝑉𝑑𝑠𝑎𝑡𝑞)𝛽

)1/𝛽

Vdsatq = √FF0 × aphit2 + Vgta2

FF0 = 1/(1 + exp (Vgsi − Vtp0)/aphit)

Vtp0 = Vt0 + γ (√𝜙𝑏 − 𝑉𝑏𝑠𝑖 − √𝜙𝑏) − δVdsi− 0.5aphit

Vgta = 1/a Qinv/Cg

a = 1 + γ/2√𝑝𝑠𝑖𝑠 − 𝑉𝑏𝑠𝑖

psis = phib + 1− γ

1+ γ + 𝜙𝑡 (1 + ln(eta0))

P a g e | 16

eta0 = Vgsi −(Vt0bs0 −δVdsi − aphit×FF)

𝑛𝑝ℎ𝑖𝑡

Vt0bs0 = Vt0 + γ (√𝜙𝑏 − 𝑉𝑏𝑠𝑖 − √𝜙𝑏)

Drain-induced barrier lowering (DIBL) correction to charges

qd = qd − dibl_corr

dibl_corr = (1 − FF0) (1 – Fsatq) qi dQinv

dQinv = Qinv − Qinvi

Qinvi = Qref ln( 1 + exp(etai) )

etai = (Vgsi – (Vt0bs0 − aphit×FF) )/ nphit

qi = qsc + qdc

Combining DD-NVSAT and ballistic charges

The function Fsat2 is used to blend the DD-NVSAT and ballistic charges according to

qs = qsc ( 1 − Fsatq )2 + qsb Fsatq2

qd = qdc ( 1 − Fsatq )2 + qdb Fsatq2

The inversion charge partitioning into terminals s and d is given as

Qinvs = 0.5 tipe Leff ( (1 + dir)qs + (1 – dir)qd )

Qinvd = 0.5 tipe Leff ( (1 - dir)qs + (1 + dir)qd )

In the current implementation of the model, only DD-NVSAT charge model is selected when CTM_select = 1 else blended DD-NVSAT

and ballistic charge model is selected.

Outer-fringing and inner-fringing charges Outer fringing charges at the s and d terminals are given as

Qsov = Cofs (V (gint) – V(si))

Qdov = Cofd (V (gint) – V(di))

Inner-fringing charges are given as

Qsif = tipe Cif FFx

Qdif = tipe Cif FFy

FFx = Vgsraw – nphit FSarg

FFy = Vgdraw – nphit Fdarg

FSarg = Vgsraw – (Vt0x – 𝛿 Vdsi Fsat) + 0.5aphit

nphit

FDarg = Vgdraw – (Vt0y – 𝛿 Vdsi Fsat) + 0.5aphit

nphit

Vt0x = Vt0 + γ (√𝜙𝑏 − 𝑡𝑖𝑝𝑒 (𝑉(𝑏) − 𝑉(𝑠𝑖)) − √𝜙𝑏)

Vt0y = Vt0 + γ (√𝜙𝑏 − 𝑡𝑖𝑝𝑒 (𝑉(𝑏) − 𝑉(𝑑𝑖)) − √𝜙𝑏)

P a g e | 17

Body charge The body charge is given as

Qb = tipe W Leff ( Cg γ √psis − Vbsi +𝑎−1

𝑎 ) Qinv (1 − qi)

Where psis, a and qi are given above.

Net-charge/capacitance model

All the charges are combined to give partitioned charges at s and d terminals according to

Qs = −W (Qinvs + Qsov + Qsif)

Qd = −W (Qinvd + Qdov + Qdif)

Qg = −(Qs + Qb + Qd)

The inter-nodal capacitance between terminals i and j is given as

Cij = −∂Qi/∂Vj if i ≠ j

Cii = ∂Qi/∂Vi

Once the nodal charges are obtained, the inter-nodal capacitances can be evaluated using these expressions. This completes the

description of the underlying MVS-model for MOSFET. The relevant gate charge from the MVS-model that sets the charge on the FE-

oxide (Qgfe described in previous section for FE-oxide model) is computed next.

Gate-charge from MOSFET determining voltage across FE-oxide Three gate-charge terms of underlying MOSFET were described in the last section namely: channel (Qinvs/Qinvd), outer fringing

(Osov/Qdov) and inner fringing (Qisf/Qidf). Particularly the outer fringing capacitances include the overlap capacitance between S/D

doped extensions in the channel and gate as well as outer fringing capacitances between S/D metal and gate metal outside the

channel. Of these two components, only the overlap capacitances contribute to CD (positive DE-capacitance) that stabilizes CFE.

Qsov = Cofs (V (gint) – V(si))

Qdov = Cofd (V (gint) – V(di))

Cofs = ( 0.345e-12/ etov ) * dLg/ 2.0 + Cof

Cofd = ( 0.345e-12/ etov ) * dLg/ 2.0 + Cof

Where etov, dLg and Cof are input parameters for effective oxide of overlapped regions, the length of overlapped S/D doped regions

under the gate, the outer fringing capacitance respectively. Of these Cof terms do not contribute to the CD which is used to compute

Qgfe. The re-definition of gate-charges relevant for NCFET FE-oxide model are given below:

Qsfe = Qs + W * (Cof * ( V(gfe) - V(si) ))

Qdfe = Qd + W * (Cof * ( V(gfe) - V(di) ))

Qgfe = -( Qsfe + Qdfe + Qb )

Time constants associated with FE-oxide The FE-oxide has two resistors representing different aspects of device-level dynamics as shown in the sub-circuit of Fig. 4. The

series resistance with FE-oxide capacitance represents the inertia of switching dipoles and the parallel resistance represents the DE-

leakage through the FE-oxide.

Switching time-constant of FE-oxide polarization dipoles V(g, gint1) <+ I(g,gint1) 𝜌

P a g e | 18

The 𝜌 in the L-K equation represents the intrinsic switching speed of dipoles associated with the FE-material and represents the

limitation on the maximum speed of operation of NCFET circuits. Unfortunately there are no significant studies on the estimation of

𝜌 for well-known FE-oxides at the microscopic scale. The reported values in literature are for large –area FE-oxide capacitors which

show switching speeds in the range of MHz [45]. At such area regimes, the speed is limited by multiple domains in FE-oxide and may

explain the slow speed. The scalability of 𝜌 as the gate-length and area of FE-oxide capacitance in NCFETs is still to be ascertained

through measurements and ab-initio physics. Another issue is that the L-K equation itself is a macroscopic lumped representation of

the physics of operation of the FE-oxide and may not be valid at single-domain small area geometry scales. In light of this, the

MVSNC model, though capable of capturing the switching time-constant, we have set the value of 𝜌 to 0 for now.

Time-constant for FE-oxide leakage V(g, gint) <+ I(g,gint) 𝑅𝐹𝐸

The RFE represents the FE-oxide leakage which can be a non-linear bias dependent function as well. Typical values of RFE correspond

to 1V/(1nA/m)=1 Gm. Since this number is large, the time constant associated with leakage in FE-oxides in NCFETs is very large

(ms-s) compared to the speed of operation (s-ns) of these devices in circuits. Thus as mentioned in previous sections, leakage is

only assumed to affect the initial condition in steady state and not during the transients in the operation of NCFET based circuits.

The initial condition dependency is to shift the QF-VF curves along the charge axis as shown in Fig. 5. By modeling shifted QF-VF as

explained in the earlier section, the effect of DE-leakage is essentially captured to affect only the initial condition and not during

transients. If the leakage is severe the above equation can be easily added to account for the memory effects that arise in transient

device operation due to high leakage, where leakage drifts the device-characteristics during switching cycles in logic circuits.

This completes the description of the details of modeling approach followed in MVSNC that includes the full dynamics of device

operation. In the next section, a list of parameter set along with their values used for generating the simulation results are given.

MVSNC model parameters The MVSNC model has two set of key parameters: (i) parameters associated with the FE-oxide and (ii) parameters for underlying

baseline MOSFET. This section lists the values along with description of key model parameters.

FE-oxide parameters The FE-oxide parameters used for the simulations included in the release correspond to DE-HZO. The parameters define the material

characteristics such as remnant polarization, coercive field as well as design parameters such as thickness of the FE-oxide used and

the extent of leakage offsets in charges and voltages after work function engineering (WFE). The thickness and Qoffset are optimized

for the technology of underlying MOSFET used. i.e, both tfe and Qoffset are adjusted to give steeper subthreshold swing compared

to baseline in transient Id-VG characteristics of NCFETs.

The variables are consistent for simulations carried out in the study of the impact of DE-leakage on the performance of FE-capacitor

and NCFET device and circuit performance in [21], [24].

Table I.a: Variables and their meaning for FE-oxide used in MVSNC-NCFET model.

Symbol Meaning Value

tfe Thickness of fE-oxide [m] 5.00E-09

Ec Coercive electric field [V/m] 6.50E+07

P0 Remnant polarization [C/m2] 2.50E-02

Qoffset Charge-offset due to leakage [fraction of P0] 6.70E-01

wfeflag Flag that activates WFE to shift the Q-V curves along voltage axis [0=no WFE, 1=WFE] 0/1

Si-FET parameters The baseline MOSFET chosen for this study and included in the release is Intel 45-nm technology node (Wei, Mysore et al. 2012)

from Intel) that was one of the datasets used in the release of MVS-1. For simplicity, the n-channel and p-channel FETs are assumed

to be identical with the same parameter set given below. The variables highlighted in blue are extracted upon calibration with

experimental data as explained in section Parameter Extraction in [22].

P a g e | 19

Table I.b: Variables and their meaning used in Si-MVS model.

Symbol Meaning Value

tipe type of transistor. nFET tipe=1; pFET tipe=-1 1/-1

W Transistor width [cm] 1.00E-02

Lgdr Physical gate length [cm] 4.00E-06

dLg Overlap length including both source and drain sides [cm] 7.56E-07

Cg Gate-to-channel areal capacitance at the virtual source [F/cm^2] 2.55E-06

etov Equivalent thickness of dielectric at S/D-G overlap [cm] 1.35E-07

delta Drain-induced-barrier-lowering (DIBL) [V/V] 0.122

n0 Subthreshold swing factor [unit-less] {typically between

1.0 and 2.0]

1.54

Rs0 Access resistance on terminal s [Ohms-micron] 71

Rd0 Access resistance on terminal d [Ohms-micron] 71

Cif Inner fringing source or drain capacitance [F/cm] 1.50E-12

Cof Outer fringing capacitance [F/cm] 1.84E-12

vxo Virtual source carrier velocity [cm/s] 9.80E+06

mu Low-field carrier “apparent mobility” [cm^2/V.s] 135

beta Saturation factor. Typ. ~ 1.8 1.8

Tjun Junction temperature [K] 300

phib Effective body voltage for Vt dependence on body bias. Typ. abs(2*phif)>0 [V] 0.9

gamma Effective body factor. Typ. 0.1-1 except =0 for fully depleted FETs [sqrt(V)] 0.2

Vt0 Strong inversion threshold voltage at Vds = 0 V [V] 0.58

alpha Empirical parameter associated with threshold voltage shift (in kT/q) between strong and weak

inversion. Typ.=3.5 [unit-less]

3.5

mc Carrier effective mass used for computation of charges f ballistic and blended quasi-ballistic

model.

0.2

CTM_select If CTM_select = 1, DD-NVSAT charge-transport model selected, otherwise blended

DD_NVSAT and ballistic charge-transport model is selected. Default is 1.

1

nd Dependence of n on Vds [1/V] 0.3

Parameter combination for leakage scenarios The simulation release includes results of the study of leakage scenarios in NCFETs along with the technique of WFE to mitigate it.

More details can be found in [21], [24] and to simulate the leakage scenarios, the following combinations of parameters are

necessary. The results for these scenarios at the device and circuit levels are given in the next section.

Table I.c: Parameter values and combinations for studying different leakage scenarios and mitigation approaches

Leakage scenario Parameter

Baseline MOSFET tfe=0

Non-leaky NCFET tfe=5e-9 , Qoffset =0

Leaky nominal NCFET tfe=5e-9 , Qoffset =1, wfeflag=0

Engineered leaky NCFET tfe=5e-9 , Qoffset =0.67, wfeflag=1

To compare the NCFET and conventional MOSFET technology and observe the performance benefits of NCFETs at device- and

circuit-level, we should be able to simulate both scenarios in the same technology-node. The MOSFET only simulation can be

activated by setting the FE-oxide thickness parameter (tfe) to 0. If tfe is not 0 then the Verilog-A code simulates the NCFET device.

Further an ideal NCFET with no leakage and no WFE can be simulated by setting Qoffset=0. This is useful to test the best-case

scenario performance of NCFET technology.

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In reality, leakage degrades the performance of the device and it will be shown in simulation results in the next section that the

leakage, if not mitigated through WFE can degrade NCFETs below the conventional baseline MOSFETs in terms of sub-threshold

swing (SS). This scenario is referred to as leaky-nominal NCFET case and can be simulated by setting non-zero tfe, along with non-

zero Qoffset=1 (along with wfeflag=0) which shifts the Q-V curves by P0 to set the FE-capacitor in the PC-state. To mitigate the

impact of leakage WFE can be done as proposed in our work in [21], [24] which can be simulated by setting a value to 0<Qoffset<1

and wfeflag=1. For our simulations Qoffset is set to 0.67 as WFE has been optimized for the underlying baseline MOSFET technology

which will be described next.

Simulation results This section deals with simulation results for underlying Si-FET used in this study along with the results for NCFET device- and circuit-

level simulation results. The first subsection presents the calibrated model results for the underlying 45-nm Si MOSFET from Intel.

This is followed by the NCFET results at the device-level that covers the four leakage scenarios. The third section focuses on the

dynamics of non-leaky NCFET using CV simulations that looks at the impact of on the signature of NC-state in the CVs. Lastly

circuit-level benchmarking is carried out using transient inverter and inverter chain simulations to highlight the superior

performance of NCFET technology compared to baseline CMOS.

Si-FET device-level simulations Transfer characteristics

Fig. 11: Transfer curve for Lgdr = 45 nm. Experimental data is shown in symbols, while the model fits are shown in solid lines.

Output characteristics

Fig. 12: Output curve for Lgdr = 45 nm. Experimental data is shown in symbols, while the model fits are shown in solid lines. Vgs value

ranges from 0.2V to 1.0V in steps of 0.2V from bottom to top curves.

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NCFET device-level IV simulations Transient Transfer characteristics

Fig. 13: (a, c,d) Response of VG,int and comparison of ID of baseline FET with ID of a leaky nominal NCFET (a), an engineered leaky

NCFET (c) and a non-leaky NCFET (d) in response to a triangular gate voltage pulse: VG: 0 V-> 2 V->0 V at VD=0.6 V. For each of these

cases, the threshold voltage is adjusted to give the same off-current as that of baseline FET (Ioff = ID (VG = 0 V, VD=0.6 V)=10 nA/m). (b)

Comparison of transient ID-VG characteristics of the baseline FET, the leaky nominal NCFET, the engineered leaky NCFET and the non-

leaky NCFET.

The transient simulations of NCFETs are performed using a commercial simulator (ADS) with the NCFET model implemented in

Verilog-A in this release. Fig. 13(a) plots the waveforms corresponding to VG,int and ID at VD=0.6 V in response to a triangular gate

voltage pulse: VG: 0 V-> 2 V->0 V of the NCFET with ideal ferroelectric charge-voltage characteristic and with leakage (referred to as

leaky nominal NCFET). The transient ID characteristics of the leaky nominal NCFET are compared against ID of baseline MOSFET.

These transient simulations are performed by using the shifted charge-voltage characteristics (along charge-axis) as shown in Fig.

5(b). Simulation of the leaky NCFET with RFE = 1/(JLA) are also performed, JL being the leakage current density through the FE-oxide

for an applied voltage of 1 V and the results agree with ones shown in Fig. 13(a). We assume that JL = 1 nA=m.

Fig. 13(b) plots the ID-VG characteristics of this leaky NCFET with WFE calculated from these responses along with that of the baseline

transistor. We note in Fig. 13(a) that, during the time segments B’D’ and C’E’, the NCFET shows differential amplification (dVG,int=dVG

> 1) and absolute amplification (VG,int > VG), respectively. In these time durations, the ferroelectric traverses the path of negative

slope and negative VF , respectively, in its QF-VF characteristics (segments B’D’ and C’E’, respectively, in Fig. 5(b)). For VG(t = 0)=0, the

P a g e | 22

ferroelectric is in state A’ in Fig. 5(b), which is a positive capacitance state, and a certain amount of VG has to be applied to make the

ferroelectric enter the negative capacitance state at the point B’. This is why in Fig. 13(d), we observe that the slope S

(=dVG=d(log10ID)) of the leaky NCFET is actually worse than that of baseline FET for VG <~1 V. The leaky NCFET has a better S only for

B’C’ segment and has a higher on-current in the segment C’E’ compared to those of the baseline FET.

Based on this study, it is clear that, if the ferroelectric is engineered such that the knee of the QF- VF curve is very close to VF =0, a

smaller VG can put the ferroelectric into the negative capacitance state. To demonstrate, we consider an engineered QF- VF with

Voffset =0.2 V and simulate the response of the corresponding NCFET, which is shown in Fig. 13(c). In this scenario, leakage does

determine the initial condition (at t=0, VG = 0 V) and starts FE-oxide from positive capacitance state but FE-oxide is pushed to

negative capacitance state at smaller VG (VG=0.2 V). The initial positive capacitance state ensures that there is no change in the initial

condition as a function of the number of triangular pulses.

The ID - VG characteristics of the engineered leaky NCFET is also shown in Fig. 13(b). Compared to the leaky NCFET, the engineered

leaky NCFET enters the regions of differential amplification (duration B0D0 in fig. 3(c)) and absolute amplification (duration C0E0 in Fig.

13(c)) at significantly smaller values of VG. Fig. 13(c) clearly shows that the engineered leaky NCFET shows steeper SS and higher on-

current than those of the baseline FET in current levels and voltage ranges of interest. Details of the simulation results can be found

in [24].

NCFET device-level CV simulations Low frequency CV characteristics under different leakage scenarios

Fig. 14: Comparison of CG-VG characteristics of the baseline FET, the leaky nominal NCFET, the engineered leaky NCFET and the non-

leaky NCFET. The peaks in CV-characteristics, which are a signature of NC-state of FE-oxide [45] appear at same VG values where we

observe steep swing in NCFET IV-characteristics in Fig. 13.

The CG- VG characteristics of the NCFETs for the leakage scenarios are compared against CV of baseline MOSFETs. The peaks in CV

characteristics are a signature of internal voltage amplification and negative capacitance state that increases the capacitance from

that of the baseline CG value. The onset of the NC-state happens at different VG for the three leakage scenarios which can also be

seen in the steeper IV characteristics in Fig. 13. This is confirmed by the MVSNC simulations shown in Fig. 14.

Low frequency CV characteristics under different inertial scenarios

The CG- VG characteristics of the NCFETs for different intrinsic speed scenarios with different values are compared against CV of

baseline MOSFETs. The peaks in CV characteristics are a signature of internal voltage amplification and negative capacitance state

that increases the capacitance from that of the baseline CG value. As is increased, the intrinsic inertia of dipoles of FE-oxide

material increases and for CVs at 1 MHz the FE-oxide no longer behaves as expected since there is no NC-state (peaks in the CVs).

This is confirmed by the MVSNC simulations shown in Fig. 15 and is a simple device-level measurement technique to estimate the

intrinsic switching speed of NCFETs.

P a g e | 23

Fig. 15: CG-VG characteristics of the baseline FET and the non-leaky NCFET simulated at f=1 MHz. The peaks in CV-characteristics,

which are a signature of NC-state of FE-oxide [45] change as the value is changed. As the value increases the intrinsic switching

speed of FE-oxide degrades and the peaks disappear. This could be a simple device-level test to study the switching limits of NCFETs.

NCFET circuit-level simulations Inverter transient simulations under different leakage scenarios

Fig. 16: Schematic of a NCFET inverter formed with FE-oxide capacitors at the gate input of constituent N- and P-channel baseline

MOSFETs. The resulting NCFETs forming the inverter are simulated under different leakage conditions.

The schematic of simulated NCFET-inverter simulated in ADS using MVSNC model is shown in Fig.16. These NCFET inverters show

superior performance benefits compared to baseline MOSFETs in their quasi-static voltage transfer characteristics (VTCs) since the

negative capacitance state of FE-oxide provides steeper SS and higher on-currents in the absence of dielectric leakage. The

simulated VTC characteristics along with the drain current and charge characteristics are shown in Fig. 17 that indicate faster

transition in VTC curves, higher on-current and internal voltage amplification due to negative capacitance state of FE-oxide that

manifests as higher gate-charges in Figs. 17(c)-(d).

Here Wn = Wp = 100 m and VT is adjusted in each case to achieve same Joff=10-2A/cm. Leakage can potentially remove these

performance benefits due to the instability of negative capacitance state in the subthreshold regime, which degrades SS as observed

from transfer current characteristics. The degraded SS and lower on-currents in constituent NCFETs under FE-oxide leakage yield

slower inverter-VTC transitions. Careful work function engineering to tackle leakage provide superior inverter characteristics (faster

transition in VTC, higher gate-charge and currents, and better noise margins) compared to baseline even under the scenario of

leakage as can be seen from Fig. 17. If the NCFET gate-metal is engineered to make them leakage-aware, a shift in the threshold

voltage in both N- and P-NCFETs is caused in the absence of leakage.

P a g e | 24

The noise margin of VTC in such NCFET inverter is poor since threshold voltage of N-NCFET becomes negative and P-NCFETs

becomes positive with work-function engineering. However under leakage scenario, such a leakage-aware (LA) NCFET inverter

exhibits stable negative capacitance in FE-oxide and the output currents and gate-charge magnitude are higher than the baseline.

The leakage-aware design results in faster transition in VTC in the presence of leakage, showing significant enhancement in the

effective gate capacitance as can be seen from gate charge curves of Figs. 17(c)-(d). The noise margins and the switching speed of

these inverters are faster than the baseline inverters. Careful choice of tFE under LA-design conditions can yield hysteresis-free

behavior in inverter VTCs as shown.

Fig. 17: (a) Transient voltage transfer characteristics (VTCs) of NCFET based inverters (with FE-capacitors in series with gate-

capacitors of both N- and P-channel MOSFETs in the inverter) are compared against the baseline regular MOSFET inverters. Two

scenarios of non-leaky NCFETs and leaky FE-oxides in leakage-aware (LA)-NCFETs with work-function engineering are simulated.

NCFETs show faster transition than the baseline which is an indication of steeper SS due to the negative capacitance state of FE-oxide.

Engineering the work function of NCFETs show superior fast-transitions under leaky scenario. The Q-V characteristics of FE-oxide are

shifted by (Voffset;Qoffset) for N-NCFET and (-Voffset;-Qoffset) for P-NCFET to achieve faster transition in the VTC under leakage. (c)-(d) the

gate-charge in N- and P-NCFETs are compared in the two scenarios against baseline FET gate-charge showing negative capacitance

regime during transition for the work-function engineered leaky-LA-NCFET.

Inverter-chain transient simulations under different leakage scenarios

Energy-delay product is a standard figure-of-merit for comparing emerging device technologies and in this subsection a realistic

circuit-level benchmarking of the metric is done for NCFET technology using six-stage inverters. The intrinsic delay of the inverter

FETs manifests as stage delay in inverter chain. Simulations of inverter chains of baseline, NCFETs and LA-NCFETs are carried out with

the results shown in Fig. 18.

By adjusting the supply voltage (VDD) of the circuit, the stage delay defined as half of the propagation delay between the outputs of

fourth and sixth stage during high-low (H-L) or low-high (L-H) switching transitions are set to the same value for the three different

cases. In this example, stage delay ts = (tH-L;6- tH-L;4 )/2 = (tL-H;6- tL-H;4 )/2= 5 ps as can be observed from Fig. 18(a)-(b). NCFETs exhibit

internal gate-voltage amplification as seen from the gate-voltage waveforms of constituent NFET (VFEN;6) and PFET (VFEP;6) of inverter-

6 which are higher than supply voltage or lower than ground respectively. For the same stage delay, NCFETs both under no-leakage

and leakage (with LA-design) scenarios allow VDD to be scaled from 0.9 V for baseline to 0.6 V as can be observed from the output

voltage waveforms of 4- and 6- inverters for the three cases.

The average switching current per stage including both static and switching currents during switching-node transitions is about the

same for the three scenarios (0.5 mA). This indicates that the average switching power in NCFET technology can be lower due to

scaled VDD, in order to achieve same speed of switching operation. NCFET inverter chains in this example consume a switching power

P a g e | 25

of 300 W compared to 450 W of baseline inverter, while yielding the same speed of 5 ps. In addition, a further power saving is

possible in NCFETs technology due to lower static power losses as a result of lower VDD (Note that Joff = 10-2A/cm in all three

scenarios). This demonstrates the performance advantages for NCFETs in logic-applications compared to baseline MOSFET

technology, even in the presence of dielectric-leakage conditions. The simulations used for the example shown in Fig. 18 include all

the device-level FET-parasitic capacitances but not the wire capacitances which can load the output of inverter stages (CL) and

contribute to switching power losses: PL = ½ Ac CLV2DDf, where Ac is the activity factor and f is the switching frequency.

The scalability of VDD in NCFET technology contributes to reduction in PL (due to its quadratic dependence on VDD) and boosts the

performance metrics of this technology compared to baseline.

Fig. 18: Six-stage inverter simulations of NCFET inverters for both non-leakage and leakage-aware (LA) scenarios are compared

against baseline inverter chain simulations. (a)-(b) Transitions of voltage waveforms (both low-to-high and high-to-low) at the

outputs of inverters 4 and 6 are used to observe the stage-delay of inverters which is adjusted to 5 ps by varying supply voltage (VDD).

Baseline inverters require VDD = 0.9V to achieve 5 ps-stage delay while NCFET inverters require lower VDD = 0.6V, irrespective of the

leakage scenarios. Lower VDD for NCFETs yields significant reduction in static power loss since the off-currents are adjusted to be

same (Ioff = ID (VG = 0 V; VD = 0.6V) = 10nA/m) for both baseline and NCFET technologies. Note that internal gate-voltage

amplification is observed with the internal gate voltages of NFET-6 (VFEN;6) going above VDD and PFET-6 (VFEP;6) going below ground (0

V ). (c)-(d) The switching currents drawn by the inverter stages from VDD are identical for baseline and NCFET technologies (for both

non-leakage and LA-case)under both switching transitions. Therefore NCFETs also offer the advantage of lower switching losses (due

to lower VDD). Furthermore, switching losses (1/2CL V2DD) associated with constant capacitive loading (CL) due to parasitic

capacitances is also reduced due to lower VDD.

Conclusions A compact model for NCFET called MVSNC is developed. The model has formulations for terminal currents, charges, and DE-leakage.

It incorporates the various time-constants associated with FE-oxide switching dynamics. Model is implemented in Verilog-A,

therefore is compatible with most circuit simulators. It is physics based and has lesser number of parameters compared to other

physical models. The model has been used to test various digital circuit simulations to study the performance benefits of NCFETRs

over conventional CMOS technology and the impact of DE-leakage on this performance advantage.

P a g e | 26

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