EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009

Combinational Circuits

Combinational Logic

OverviewCombinational CircuitChip Design stylesFull-custom designCell library based designProgrammable Logic Array* PJF- *Combinational Logic

Combinational Logic

* PJF- *Combinational LogicCombinational CircuitsA combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs.For n input variables, there are 2n possible binary input combinations.For each binary combination of the input variables, there is one possible output.

Combinational Logic

* PJF- *Combinational LogicCombinational Circuits (cont.)Hence, a combinational circuit can be described by:A truth table that lists the output values for each combination of the input variables, orm Boolean functions, one for each output variable.CombinationalCircuitn-inputsm-outputs

Combinational Logic

* PJF- *Combinational LogicCombinational vs. Sequential CircuitsCombinational circuits are memory-less. Thus, the output value depends ONLY on the current input values.Sequential circuits consist of combinational logic as well as memory elements (used to store certain circuit states). Outputs depend on BOTH current input values and previous input values (kept in the storage elements).

Combinational Logic

* PJF- *Combinational LogicCombinational vs. Sequential CircuitsCombinationalCircuitn-inputsm-outputs(Depend only on inputs)CombinationalCircuitn-inputsm-outputsStorageElementsNextstatePresentstateSequential CircuitCombinational Circuit

Combinational Logic

* PJF- *Combinational LogicImportant Design ConceptsModern digital design deals with various methods and tools that are used to design and verify complex circuits and systems. Concepts:Design HierarchyComputer-Aided-Design (CAD) toolsHardware Description Languages (HDLs)

Combinational Logic

* PJF- *Combinational LogicDesign HierarchyDivide-and-Conquer approach used to cope with the challenges of designing complex circuits and systems (many times in the order of millions of gates).Circuit is broken into blocks, repetitively.

Combinational Logic

* PJF- *Combinational LogicDesign Hierarchy Example: 9-input odd function (for counting # of 1 in inputs)

Combinational Logic

* PJF- *Combinational LogicWhy is Hierarchy useful?Reduces the complexity required to design and represent the overall schematic of the circuit.Reuse of blocks is possible. Identical blocks can be used in various places in a design, or in different designs.

Combinational Logic

* PJF- *Combinational LogicReusable Functions and CADWhenever possible, we try to decompose a complex design into common, reusable function blocksThese blocks areverified and well-documentedplaced in libraries for future use

Combinational Logic

* PJF- *Combinational LogicIntegrated CircuitsIntegrated circuit (a chip) is a semiconductor crystal (most often silicon) containing the electronic components for the digital gates and storage elements which are interconnected on the chip.Terminology - Levels of chip integrationSSI (small-scale integrated) - fewer than 10 gatesMSI (medium-scale integrated) - 10 to 100 gatesLSI (large-scale integrated) - 100 to thousands of gatesVLSI (very large-scale integrated) - thousands to 100s of millions of gates

Combinational Logic

* PJF- *Combinational LogicTechnology ParametersSpecific gate implementation technologies are characterized by the following parameters: Fan-in the number of inputs available on a gateFan-out the number of standard loads driven by a gate outputCost for a gate - a measure of the contribution by the gate to the cost of the integrated circuitPropagation Delay The time required for a change in the value of a signal to propagate from an input to an outputPower Dissipation the amount of power drawn from the power supply and consumed by the gate

Combinational Logic

* PJF- *Combinational LogicPropagation DelayPropagation delay is the time for a change on an input of a gate to propagate to the output.Delay is usually measured at the 50% point with respect to the H and L output voltage levels.High-to-low falling and low-to-high rising delays.

Combinational Logic

* PJF- *Combinational LogicPropagation Delay Example

IN (volts)OUT (volts)t (ns)1.0 ns per division

Combinational Logic

* PJF- *Combinational LogicChip Design StylesFull custom - the entire design of the chip down to the smallest detail of the layout is performedExpensive, its timing and power is hard to analyzeonly for dense, fast chips with high sales volumeStandard cell - blocks have been design ahead of time or as part of previous designsIntermediate cost Less density and speed compared to full customGate array - regular patterns of gate transistors that can be used in many designs built into chip - only the interconnections between gates are specific to a designLowest costLess density compared to full custom and standard cellPrototype designThe base of FPGA

Combinational Logic

* PJF- *Combinational LogicCell LibrariesCell - a pre-designed primitive blockCell library - a collection of cells available for design using a particular implementation technologyCell characterization - a detailed specification of a cell for use by a designer

Combinational Logic

* PJF- *Combinational LogicCell Library Based Design ProcedureSpecificationWrite a specification for the circuit if one is not already availableFormulationDerive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specificationOptimizationDraw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters

Combinational Logic

* PJF- *Combinational LogicCell Library Based Design ProcedureTechnology MappingMap the logic diagram to the implementation technology selectedMap to CMOSEvaluationEvaluate the timing and power

Combinational Logic

* PJF- *Combinational LogicDesign ExampleSpecification BCD to Excess-3 code converterTransforms BCD code for the decimal digits to Excess-3 code for the decimal digitsBCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectivelyExcess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word

Combinational Logic

* PJF- *Combinational LogicDesign Example (continued) FormulationConversion of 4-bit codes can be most easily formulated by a truth tableVariables - BCD: A,B,C,DVariables - Excess-3 W,X,Y,ZDont Cares - BCD 1010 to 1111

Input BCD A B C D Output Excess-3 WXYZ 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 1 1

Combinational Logic

* PJF- *Combinational LogicDesign Example (continued)OptimizationK-maps

W = A + BC + BDX = C + D + BY = CD + Z =

Combinational Logic

* PJF- *Combinational LogicDesign Example (continued)Optimization (continued) Multiple-level using transformations W = A + BC + BD X = C + D + B Y = CD + Z = Perform extraction, finding factor: T1 = C + D W = A + BT1 X = T1 + B Y = CD + Z =

Combinational Logic

*Combinational LogicDesign Example (continued)Technology Mapping Map with a library containing inverters and 2-input NAND, and then map it to a CMOS based circuitZ

Combinational Logic

* PJF- *Combinational LogicNAND Mapping Example

Combinational Logic

Timing AnalysisUse static timing analysis which has been covered.* PJF- *Combinational Logic

Combinational Logic

*PJF - *Combinational LogicProgrammable Logic ArrayThe set of functions to be implemented is first transformed to product termsSince output inversion is available, terms can implement either a function or its complement

Combinational Logic

*PJF - *Combinational LogicProgrammable Logic Array ExampleTo implementF1= ABC+ABC+ABC=(AB+AC+BC+ABC)F2=AB+AC+BC

Combinational Logic

*PJF - *Combinational LogicProgrammable Logic Array Example

Combinational Logic

****************************tPHL = 1.4 ns, tPLH = 1.1 ns, tpd = 1.25 ns**************************