Gianluigi De Geronimo, Alessio D’Anadragora*, Shaorui Li, Neena Nambiar, Sergio Rescia, Emerson VernonHucheng Chen, Francesco Lanni, Don Makowiecki, Veljko Radeka, Craig Thorn, and Bo Yu

Brookhaven National Laboratory, NY, USA* University of L’Aquila, L’Aquila, Italy

Cold CMOS Electronicsfor the readout of

very large LAr TPCsCraig Thorn

On behalf of the LBNE LAr Working Group

TIPP 2011June 11, 2011

Outline• LAr40 overview• The Cold Electronics System• Analog Front End• ADC• Summary

Other presentations at TIPP 2011 describing LBNE LAr40:o [412] Membrane cryostat technology and prototyping program

towards kton scale Neutrino detectors, Rucinskio [422] Designs of Large Liquid Argon TPCs — from MicroBooNE to

LBNE LAr40, Yuo [223] Front End Readout Electronics of the MicroBooNE

Experiment, Chen

June 11, 2011 2TIPP 2011 – Cold Electronics

LBNE LArTPC inside Cryostats in Cavern

Membrane Cryostat

TPC Arrays

High Bay AccessTruss Lid for

CryostatIsolated Personnel

Access

Deep Underground Science & Engineering Lab(DUSEL) in Homestake, South Dakota, USA

LAr40 TPC2x20 killotonnes

June 11, 2011 3

Field Cage Bars

APA + CPA Assemblies form TPC modulesin the Cryostat

APA = Anode Plane Assembly

CPA = Cathode Plane

Assembly

APA CPARepeatRepeat

Unit CellTPM = TPC Module

= 1 APA + 1 CPA(+1 “terminal”

CPA)

Volume~ 0.5 x ICARUS

~2 xMicroBooNE

June 11, 2011 4

Anode Plane Assembly (APA): the core element of a TPC unit

APAs are structural and electrical units containing all

sense wires and readout

electronics. They can be tested in LN2 and stored

and transported in shipping

containers.

Cold Electronics

June 11, 2011

5

TIPP 2011 – Cold Electronics

LAr TPC - Cold CMOS ElectronicsBlock Diagram – Reference Design

June 11, 2011 6TIPP 2011 – Cold Electronics

~ 7 mm

~ 5

mm

Layoutchg amp filter ac reg ADC cmp

pulser BGR, bias, temp. sens. reg control logic

mux

buffer• 16 channels• charge amplifier (adj. gain)• high-order filter (adj. time

constant)• ac/dc, adjustable baseline• test capacitor, channel mask• ADC (12-bit, 2 MS/s)• compression, discrimination• multiplexing and digital buffering• LV or CM digital interface• pulse generator, analog monitor• temperature sensor• LAr environment (> 20 years at

88K)• estimated total size ~ 6 x 8 mm²• estimated power ~ 10 mW/channel

dual-stage charge amplifier filter ac/dc

common register

channel registergain &mode bypasspeaking time &

mode

16 channels

mode

wire

mode & couplingtest

ADC12-bit, 2 MS/s

BGR, common bias, temp. sensor control logicpulse generator

compression muxdigital

interface(LV or CM)

CKCSDI

DO

AO

buffer

Block DiagramLAr TPC Front-End ASIC

• 16 channels• charge amplifier, high-order filter• adjustable gain: 4.7, 7.8, 14, 25 mV/fC (charge 55, 100, 180, 300 fC)• adjustable filter time constant (peaking time 0.5, 1, 2, 3 µs)• selectable collection/non-collection mode (baseline 200, 800 mV)• selectable dc/ac coupling (100µs)

dual-stage charge amplifier filter ac/dc

common register

channel registergain &mode bypasspeaking time &

mode

16 channels

mode

wire

mode & couplingtest

BGR, common bias, temp. sensordigital

interface

Block Diagram

analogoutputs

• rail-to-rail analog signal processing• band-gap referenced biasing• temperature sensor (~ 3mV/°C)• 136 registers with digital interface• 5.5 mW/channel (input MOSFET 3.9 mW)• single MOSFET test structures• ~ 15,000 MOSFETs• designed for room (300K) and cryogenic (77K)

operation• technology CMOS 0.18 µm, 1.8 V

6.0 mm

5.7 mm

Analog ASIC

June 11, 2011 8TIPP 2011 – Cold Electronics

Measurements affected by:• input line parasitic resistance

• ~ 150 e- at 77 K (~ 590 e- at 300K )• addressed in next revision

Layout Detail

Input MOSFETL = 270 nmW = 10 mm

(50µm x 200)gm,77K ≈ 90 mS (11 Ω)gm,300K ≈ 45 mS (22 Ω)

Input LineL ≈ 1 mm

W = 3.5 µm(M3 + M4)R77K ≈ 3 Ω

R300K ≈ 12 Ω

• CINdielectric noise (not present in wire)• ~ 60 e- at 77 K

MICAfore60

NPOfore200

tgkTC2dENC IN

0 1 2 3500

600

700

800

900

ENC

(elec

trons

r.m

.s.)

Peaking Time (µs)

Dielectric: MICA NP0

T=77KC

IN=220pF

0 1 2 30

200

400

600

800

1000

1200

1400

1600

1800

simulated input MOSFET

target at 90K

measured

simulated whole front-end

EN

C (e

lectro

ns r.

m.s.

)

Peaking Time (µs)

T=300K T=77K

CDET

=220pF

Noise Measurements

ASIC revision 2 designed and fabricated, currently being tested

Dynamic Range > 3,000

Qmax=300fC

9

v1

v2

FEE ASIC Evaluation

FEE Test Stand for MicroBooNE is operational Full front end electronics chain, from CMOS ASIC to Receiver/ADC

board, data is acquired to PC through FPGA board and Gigabit Ethernet

One  temporary  32 channel  cold  cable  is  available which  has  one  broken  channel

Without detector capacitance, noise is ~200e- with 1us peaking time

Nonlinearity and crosstalk are less than 0.5%

FEE test stand will be upgraded with the second version of ASICs and two prototype cold cables, more tests to follow

June 11, 2011 10TIPP 2011 – Cold Electronics

June 11, 2011 11TIPP 2011 – Cold Electronics

0.0 0.3 0.6 0.9 1.2 1.5 1.80

2

4

6

8

10CMOS018SIMULATED (foundry parameters)

LN RT

I D [m

A]

VDS

[V]

NMOS, L=0.18µm, W=10µm

0.0 0.3 0.6 0.9 1.2 1.5 1.80

2

4

6

8

10CMOS018

NMOS, L=0.18µm, W=10µm

MEASURED LN RT

I D [m

A]

VDS

[V]

Some differences in saturation voltage, sub-threshold slope, transconductance

IDvsVDS

IDvsVGS

0.0 0.3 0.6 0.9 1.2 1.5 1.810-5

10-4

10-3

10-2

10-1

100

101

CMOS018

SIMULATED(foundry parameters)

LN RT

ID

gm

I D [mA]

, gm [m

S]

VGS

[V]

NMOS, L=0.18µm, W=10µm

0.0 0.3 0.6 0.9 1.2 1.5 1.810-5

10-4

10-3

10-2

10-1

100

101

CMOS018

MEASURED

ID

gm

LN RT

I D [mA]

, gm [m

S]

VGS

[V]

NMOS, L=0.18µm, W=10µm

MOS Static Model

12

-4 -2 0 2 4 6 8

0.0

0.2

0.4

0.6

0.8

Am

plitu

de [V

]

Time [µs]

T=300K T=77K

Gain 25 mV/fCPeaking time 1µs

Pole-zero cancellation at 77K to be addressed in next revision

K77atV164.1

K300atV185.1VBGR

Bandgap Reference

0 10 20 30 40 50

Am

plitu

de [a

.u.]

Time [µs]

Peak time [µs] 0.5 1.0 2.0 3.0

collecting mode

non-collecting mode

gain [mV/fC]25147.84.7Adjustable gain, peaking time and baseline

maximum charge 55, 100, 180, 300 fC

variation ≈ 1.8 %

K77atVm3.259K300atmV0.867

VTMP

Temperature Sensor

~ 2.86 mV / °K

Signal Measurements

13

n p

e ne

logic

n p e ne

share

curr

ent s

ourc

e

shaped pulse (current signal I)

I v1

sa1

i1

sb1 dsc1

v2

sa2

i2

sb2 dsc2

vm-1

sam-1

im-1

sbm-1 dscm-1

d1 d2 dm-2 dm-1

V

Current mode ADC• dual stage6-MSBs in 150ns, 6-LSBs in 250ns• single trigger conversion per stage• 12-bit resolution• 2 MS/s conversion rate • power dissipation 3.6 mW at 2 MS/s• power-down option for low rate

applications• wake up in few tens of ns

• layout size: 0.23 mm x 1.25 mm

ADC cell

Clockless low power ADC stageDemonstrated in ASIC for SNS, see De Geronimo, et al., IEEE Trans NSS, 54

(2007) 541

ADC - Architecture

14

• operation verified at room and cryogenic temperatures• differential non-linearity limited by timing design error in control circuit• integral non-linearity limited by mismatch (linear → common centroid)

ADC - Preliminary Results

ASIC revision being designed, to be fabricated in July

ADC output - 500mV dc

σ=1.1LSB

77 K

ADC output - 1.4 V sine

300 K16-channelADC+buffer

6mm

4.3 mm

15

• CMOS performs better at cryogenic temperatures• Defined and predictable design for cryogenic T is possible• Low-noise at cryogenic T demonstrated

• ENC < 1,000 e- at 200pF ~5mW/ch.• characterization and modeling of CMOS 180nm

• Long lifetime at cryogenic T possible with guidelines• Critical building blocks - front-end & ADC - developed

• Future work• Improve cryogenic static models• Optimize ADC• Merge, add zero-suppression & buffering, and finalize

Conclusions and Future Work

June 11, 2011 16TIPP 2011 – Cold Electronics

17

Backup Slides

LAr TPC - Cold CMOS ElectronicsBlock Diagram – Alernate Design

June 11, 2011 18TIPP 2011 – Cold Electronics

M4

200fF (mismatch σ < 0.25% (< 0.5% lot-to-lot)

M1 MP M2 M2xN2

MNto

shaper

frominput wire

M1xN1

C2 C2xN2C1 C1xN1

cal. pulse

M3

dis en

dual-stage charge amplifier

N1 = 20 N2 = 3, 5, 9, 16

CINJ = 180 fF nominalIntegrated injection capacitance (10 x 18 µm²)Disabled (grounded) when unused

K77atfF183

K300atfF184CINJ

Calibration Scheme

Measured with high-precision external capacitance change ~ 0.5%

• increases as the temperature decreases

J. Cressler et al.

• Degradation is due to impact ionization• charge trap in oxide, interface generation → shift in Vth and gm

Lifetime - Basic Mechanism

Commercial technologies are rated 10 years lifetime (10% gm shift) in continuousring oscillator operation: T = 300 K, L = Lmin, Vds = nominal VDD+5%, VGS≈ VDS/2)

• Substrate current is a monitor of impact ionization• increases with drain voltage• is higher in short channel devices• has a maximum at VGS≈ VDS/2

J. Cressler et al.

20

Desired lifetimeat low temperature can be achieved by:1. decreasing VDS (e.g. decreasing

the supply voltage)

2. decreasing JD(i.e. decreasing the drain current density)

3. increasing L (i.e. non-minimum channel length devices)

J. Cressler et al.

Accelerated tests at cryogenic temperature are being performed to verify guidelines

Lifetime - Design Guidelines

analog circuits- operate devices at low current density- use non-minimum channel length L

Accelerated tests at increased VDSallow extrapolation of lifetime

digital circuits- operate devices at -10% of nom. VDD

- use non-minimum channel length L- operate at low clock frequency

Design guidelines can be obtained for:

21