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Cogent CSB737 Hardware Reference Manual – P3.0 3/17/2009

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”ALWAYS COMPLETE”

Cogent CSB737 Atmel SAM9263

System On a Module (SOM)

Hardware Reference Manual © 2008

Cogent Computer Systems, Inc.

COGENT


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Table of Contents 1 Warranty ................................................................................................................................................................................................... 4 2 Operating Specifications .......................................................................................................................................................................... 5

2.1 CSB737 Operating specifications .................................................................................................................................................... 5 3 Overview................................................................................................................................................................................................... 6

3.1 Introduction ....................................................................................................................................................................................... 6 3.2 Block Diagram .................................................................................................................................................................................. 6

4 OnBoard Devices.................................................................................................................................................................................... 8 4.1 CSB737 Address Map...................................................................................................................................................................... 8

4.1.1 Address Map Notes .................................................................................................................................................................. 8 4.2 64Mbyte Spansion FLASH............................................................................................................................................................... 9 4.3 64Mbyte SDRAM.............................................................................................................................................................................. 9 4.4 512MByte 8Bit NAND Flash ........................................................................................................................................................... 9

4.4.1 NAND Flash Notes ................................................................................................................................................................. 10 4.5 16Mbyte PSRAM ............................................................................................................................................................................ 10

4.5.1 16Mbyte PSRAM Notes.......................................................................................................................................................... 10 4.6 DS1339 RTC .................................................................................................................................................................................. 10

4.6.1 DS1339 RTC Interface Notes................................................................................................................................................. 11 4.7 LM3489 3.3V Regulator ................................................................................................................................................................. 11

4.7.1 LM3489 3.3V Regulator Notes ............................................................................................................................................... 11 5 SAM9263 OnChip Peripherals ............................................................................................................................................................. 12

5.1 Overview ......................................................................................................................................................................................... 12 5.2 SAM9263 to SODIMM Peripheral Mapping................................................................................................................................... 12 5.3 SAM9263 Chip Selects .................................................................................................................................................................. 13 5.4 SAM9263 General Purpose I/O Assignments ............................................................................................................................... 13

5.4.1 SAM9263 GPIO Notes ........................................................................................................................................................... 20 5.5 SAM9263 Interrupt Pin Assignments............................................................................................................................................. 20 5.6 SAM9263 UARTS........................................................................................................................................................................... 21

5.6.1 SAM9263 UART Notes........................................................................................................................................................... 21 5.7 SAM9263 SPI Controllers .............................................................................................................................................................. 21

5.7.1 SAM9263 SPI Interface Notes ............................................................................................................................................... 22 5.8 SAM9263 SSI Controller ................................................................................................................................................................ 22

5.8.1 SAM9263 SSI Interface Notes ............................................................................................................................................... 23 5.9 SAM9263 I2C Interface.................................................................................................................................................................. 23 5.10 SAM9263 4Bit SD/MMC Controller ............................................................................................................................................ 24

5.10.1 SAM9263 SD/MMC Controller Notes................................................................................................................................... 24 5.11 SAM9263 Compact Flash Interface............................................................................................................................................. 25

5.11.1 SAM9263 Compact Flash Interface Notes .......................................................................................................................... 25 5.12 SAM9263 USB Host Controller.................................................................................................................................................... 26

5.12.1 SAM9263 USB Host Interface Notes ................................................................................................................................... 26 5.13 SAM9263 USB Device Controller ................................................................................................................................................ 26

5.13.1 SAM9263 USB Device Interface Notes ............................................................................................................................... 26 5.14 SAM9263 AC97 Audio Codec Interface ...................................................................................................................................... 26

5.14.1 AC97 Audio Interface Notes................................................................................................................................................. 27 5.15 SAM9263 LCD Controller............................................................................................................................................................. 27

5.15.1 SAM9263 LCD Notes ........................................................................................................................................................... 28 5.16 2D Graphics Controller................................................................................................................................................................. 28 5.17 SAM9263 Image Sensor Interface............................................................................................................................................... 29

5.17.1 SAM9263 Image Sensor Notes............................................................................................................................................ 29 5.18 SAM9263 10/100 Ethernet MAC and LAN8700 PHY ................................................................................................................. 29

5.18.1 SAM9263 Ethernet MAC/PHY Notes................................................................................................................................... 30 5.19 Unavailable SAM9263 Peripherals/Signals................................................................................................................................. 31

6 CSB737 Clocking ................................................................................................................................................................................... 32 6.1 SAM9263 Input Clocks................................................................................................................................................................... 32 6.2 SAM9263 Output Clocks................................................................................................................................................................ 32 6.3 RMII and LAN8700 PHY Clock ...................................................................................................................................................... 32

7 CSB737 Power Management ................................................................................................................................................................ 33 7.1 SAM9263 Wakeup and Shutdown................................................................................................................................................. 33 7.2 SODIMM *LOW_PWR.................................................................................................................................................................... 33 7.3 SODIMM *PWR_DIS...................................................................................................................................................................... 33

8 CSB737 Software................................................................................................................................................................................... 34 8.1 Overview ......................................................................................................................................................................................... 34

9 SODIMM Format and Pinout ................................................................................................................................................................. 35 9.1 Overview ......................................................................................................................................................................................... 35 9.2 SODIMM Format ............................................................................................................................................................................ 35 9.3 SODIMM Pinout.............................................................................................................................................................................. 35

10 Component Locations .......................................................................................................................................................................... 44 10.1 Overview....................................................................................................................................................................................... 44

11 Document Revisions ............................................................................................................................................................................ 45


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List of Tables Table 1 – CSB737 Operating Specifications.............................................................................................................................................. 5 Table 2 – CSB737 Address Map ................................................................................................................................................................ 8 Table 3 – SAM9263 to NAND Flash Connections ................................................................................................................................... 10 Table 4 – SAM9263 to DS1339 Connections .......................................................................................................................................... 11 Table 5 –SAM9263 Peripheral to SODIMM Mapping .............................................................................................................................. 13 Table 6 – SAM9263 Chip Select Assignments ........................................................................................................................................ 13 Table 7 – SAM9263 GPIO Port A Assignments....................................................................................................................................... 15 Table 8 – SAM9263 GPIO Port B Assignments....................................................................................................................................... 16 Table 9 – SAM9263 GPIO Port C Assignments ...................................................................................................................................... 17 Table 10 – SAM9263 GPIO Port D Assignments .................................................................................................................................... 18 Table 11 – SAM9263 GPIO Port E Assignments..................................................................................................................................... 19 Table 12 – SAM9263 Interrupt Pin Assignments ..................................................................................................................................... 20 Table 13 – SAM9263 UARTS to SODIMM Connections......................................................................................................................... 21 Table 14 – SAM9263 SPI Controllers to SODIMM Connections............................................................................................................. 22 Table 15 – SAM9263 SSI Controller to SODIMM Connections .............................................................................................................. 23 Table 16 – SAM9263 I2C Controller to SODIMM Connections............................................................................................................... 24 Table 17 – SAM9263 SD/MMC Controller to SODIMM Connections ..................................................................................................... 24 Table 18 – SAM9263 Compact Flash Controller to SODIMM Connections ........................................................................................... 25 Table 19 – SAM9263 AC97 Controller to SODIMM Connections ........................................................................................................... 27 Table 20 – SAM9263 LCD Interface to SODIMM Connections............................................................................................................... 28 Table 21 – SAM9263 Image Sensor Interface to SODIMM Connections ............................................................................................... 29 Table 22 – SAM9263 MAC to PHY Connections..................................................................................................................................... 30 Table 23 – SAM9263 Unavailable Peripherals/Signals ........................................................................................................................... 31 Table 24 – CSB737 SODIMM Expansion Connector Pinout................................................................................................................... 43 Table 25 – Document Revisions............................................................................................................................................................... 45

List of Figures Figure 1 – CSB737 Block Diagram............................................................................................................................................................. 7 Figure 2 – CSB737 Component Locations............................................................................................................................................... 44


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1 WARRANTY The enclosed product ("the Product"), a part of the Cogent Modular Architecture or Cogent Single Board series, is warranted by Cogent Computer Systems, Inc. ("Cogent") for a period of six months for reasonable development testing and use, all as further described and defined below. This warranty runs solely to the individual or entity purchasing the Product and is not transferable or assignable in any respect. This warranty is valid only for so long as the product is used intact as shipped from Cogent. Any attempt or effort to alter the Product, including but not limited to any attempt to solder, desolder, unplug, replace, add or affix any part or component of or onto the Product, other than components specifically intended for the user to plug and unplug into appropriate sockets and/or connectors to facilitate user programming and development, all as specifically described and authorized in the Cogent Customer Product Users Manual, shall void this warranty in all respects. Coverage under this warranty requires that the Product be used and stored at all times in conditions with proper electrostatic protection necessary and appropriate for a complex electronic device. These conditions include proper temperature, humidity, radiation, atmosphere and voltage (standard commercial environment, 0C to +70C, <60%RH). Any Product that has been modified without the express, prior written consent of Cogent is not covered by this warranty. Cogent Single Board and Cogent Modular Architecture test and bus connectors are for use with Cogent adapters only. The use or connection of any test or bus connector, adapter or component with any device other than a Cogent connector or adapter shall void this warranty and the warranty of all other components, parts and modules connected to the rest of the system. Cogent shall not be responsible for any damage to the Product as a result of a customer's use or application of circuitry not developed or approved by Cogent for use on or in connection with the Product.

This warranty does not cover defects caused by electrical or temperature fluctuations or from stress resulting from or caused by abuse, misuse or misapplication of the Product. Any evidence of tampering with the serial number on the Product shall immediately void this warranty. This Product is not intended to be used on or embedded in or otherwise used in connection with any life sustaining or life saving product and this warranty is not applicable nor is Cogent liable in any respect if the Product is so used. Notwithstanding anything to the contrary herein, Cogent expressly disclaims any implied warranty of merchantability or implied warranty of fitness for a particular purpose in connection with the manufacture or use of the Product.


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2 OPERATING SPECIFICATIONS 2.1 CSB737 OPERATING SPECIFICATIONS

The CSB737 conforms to the following specifications:

Specification Value

Dimensions 68mm (2.63”) x 50.8mm (2.00”) x 8mm (.315”)

Weight ~40g

Storage Temperature 20C to +100C

Operating Temperature 0C to +70C (Commercial Temp Version)

Humidity 0% to 95% RH, NonCondensing

Input Voltage (VIN Pin) +6V Minimum to +35V Maximum

VCC3 Output Voltage +3.3V +/ 2% @ 2 Amp Output

Power Consumption (estimated)

750mw Typical, 1.2W Maximum 50mw Sleep to Ram

Table 1 – CSB737 Operating Specifications


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3 OVERVIEW 3.1 INTRODUCTION

The CSB737 was designed and developed by Cogent Computer Systems, Inc. as a highly integrated Atmel SAM9263 System On a Module (SOM). The CSB737 provides a very small, powerful, flexible engine for embedded control systems of all kinds. The major features of the CSB737 are as follows:

• 200Mhz Atmel SAM9263 CPU with 32K ICache and 32K DCache • OnChip High Speed 16Kbyte and 80Kbyte SRAM Blocks • 64Mbyte 32Bit Wide SDRAM • 64Mbyte 16Bit Wide Spansion FLASH with Secure 256 Byte Sector and 128Bit Unique ID • 512Mbyte 8Bit NAND Flash • OnChip LCD Controller up to 1024 x 768 with OnChip 2D Graphics Acceleration • 8Mbyte PSRAM via External Bus Interface 1 for LCD Frame Buffer • 8/10Bit Video Input Port supporting YUV4:2:2, CCIR656 and Standard CMOS Sensors • OnChip 10/100 Ethernet Controller with Low Power LAN8700 10/100 RMII PHY • Dual 12Mbit USB 2.0 Host Ports and Single 12Mbit USB 2.0 Device Port • DS1339 Real Time Clock with Battery Backup • RS232 Buffer for Debug Serial Port (SAM9263 STDUART) • Three Additional TTL UARTS, one 4Wire (UART0) and two 2Wire (UARTS 1 and 2) • Single Channel 1Mbit/sec 2.0B Compliant CAN Interface • SAM9263 SD/MMC Controller, 4Bit, SDIO Compliant • 26Bit Address/16Bit Data bus for Compact Flash or Generic Expansion • Standard ARM JTAG Interface • 10 Dedicated GPIO lines (most peripherals may also be assigned as GPIO) • Programmable Core Regulator (0.9V to 1.5V) for Dynamic Voltage/Frequency Scaling • Wide Input (6V to 35V), On Board 3.3V Regulator provides 2A to the User Board • <750mw typical, 1,200mw maximum, <50mw sleep to RAM • Compact SODIMM form factor, 2.63” (68mm) x 2.0” (50.4mm) x 0.315" (8mm) high • Low EMI design with 0402 components and FineLine, MultiLayer PCB construction • Compatible with Cogent CSB702 Base Board

3.2 BLOCK DIAGRAM Refer to the following figure for a block diagram of the CSB737 SOM.


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200MHZ SAM9263

LAN8700 10/100 PHY

VIN

VCC3 MOUNTING HOLE & POWER TERMINAL 3.3V @ 2A OUT

MOUNTING HOLE & POWER TERMINAL 6V TO 35V IN

CSB737 BLOCK DIAGRAM SODIMM 200 PIN EDGE CONNECTOR

LED IS ON WHEN ERASING OR

PROGRAMMING

3.3V

3.3V

3.3V @ 4A SWITCHING REGULATOR

512MBYTE, 8BIT NAND FLASH

RMII I/F

10/100 TWISTED PAIR I/F

STATUS LED'S

DEBUG SIO

JTAG I2C

SPI0 SPI1 (TOUCH)

UART0 UART1 UART2

AC97 AUDIO SD/MMC COMPACT FLASH

CONTROL GPIO'S TOUCH &

EXPANSION IRQ'S

*LOW_PWR

PWR DISABLE SIGNAL

RTC BAT

SSP

GPIO PB31

PLL AND CORE SUPPLY

SSI1

JTAG I2C

SPI0 SPI1 UART0 UART1

AC97 4BIT SD/MMC

USB DEVICE

PCMCIA/ COMPACT FLASH I/F

GPIO'S

UART2

DS1339 REAL TIME CLOCK

64MBYTE, 32BIT

PC133 SDRAM

1.2V SWITCHING REGULATOR

RS232 BUFFER

EXPANSION CHIP SELECT AND CONTROL 16BIT DATA 25BIT ADD.

18BIT LCD INTERFACE

18Bit LCD CONTROLLER

DEBUG UART

8BIT VIDEO INPUT PORT

CMOS SENSOR INPUT PORT

USB HOST 0 USB DEVICE USB HOST 0 USB HOST 1 USB HOST 1

EBI 0

EBI 1

CHIP SELECTS AND CONTROL

32BIT DATA 25BIT ADD. 10/100 MAC

10/100 TWISTED PAIR I/F

STATUS LED'S

16BIT DATA 23BIT ADD.

CHIP SELECT AND CONTROL

8MBYTE, 16BIT PSRAM

(FRAME BUFFER)

64MBYTE, 16BIT SPANSION FLASH

STATUS OUT

Figure 1 – CSB737 Block Diagram


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4 ONBOARD DEVICES 4.1 CSB737 ADDRESS MAP

The following table describes the Address Map of the CSB737. Note that the SAM9263 support two separate External Bus Interface (EBI) controllers, EBI0 and EBI1. Refer to the SAM9263 documentation for information regarding these as well as for on chip peripheral addressing.

EBI0 Chip Select

Chip Select Width

Wait States

Address Start

Address End

Description

*CS0 16 11 0x1000.0000 0x1FFF.FFFF S29GL512N

*CS1 32 N/A 0x2000.0000 0x2FFF.FFFF 64Mbyte SDRAM

*CS2 16 WAIT 0x3000.0000 0x3FFF.FFFF Expansion Chip Select

*CS3 8 12 0x4000.0000 0x4FFF.FFFF NAND Flash

*CS4 N/A WAIT 0x5000.0000 0x5FFF.FFFF Compact Flash Socket 0

*CS5 N/A N/A 0x6000.0000 0x6FFF.FFFF Compact Flash Socket 1 (unused)

EBI1 Chip Select

Chip Select Width

Wait States

Address Start

Address End

Description

*CS0 16 8 0x7000.0000 0x7FFF.FFFF 16Mbyte PSRAM

I2C I2C Address Description

I2C 0x58 DS1339 Real Time Clock via I2C

Table 2 – CSB737 Address Map

4.1.1 ADDRESS MAP NOTES

1. Address ranges are based on the SAM9263 maximum range for that chip select. The actual device or devices controlled by the chip sect may not fill the range, but will repeat multiple times based on their actual size.

2. WAIT in the “Wait States” column indicates the device uses the *WAIT input to the SAM9263 to control the access. Wait States are based on the device access times assuming a 100Mhz Master Clock (MCK).

3. Software must program EBI0 Chip Select 1 for SDRAM mode.


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4. Software must program EBI0 Chip Select 3 for NAND Mode.

5. Software must program EBI0 Chip Select 4 for Compact Flash Mode.

6. EBI1 Chip Selects 2 and 3 are not available on the CSB737.

7. The DS1339 Address is the I2C address it responds to. SW must setup the SAM9263 I2C Controller to access the DS1339.

4.2 64MBYTE SPANSION FLASH The CSB737 uses a Spansion S29GL512N connected to *EBI0_CS0 for boot memory. *EBI0_CS0 is set to 16bits width by hardware strapping and maximum wait states after reset. Initialization software should change the settings of * EBI0_CS0 to 11 wait states (110ns at 100Mhz Master Clock).

The Spansion S29GL512N also provides a unique 64bit ID thus allowing for security and IP rights software to use this as a board identifier.

4.3 64MBYTE SDRAM The CSB737 uses two 16Mx16, PC133 SDRAM devices connected to *EBI0_CS1 (enabled in SDRAM mode) for system memory. The SAM9263 Master Clock, MCK (which drives the SDRAM Clock directly) should be programmed for 100Mhz (Core/2), CAS Latency=2 and RAS to CAS=2 operation. Refer to the SAM9263 User Manual for more information on programming the SDRAM Memory Controller.

4.4 512MBYTE 8BIT NAND FLASH The CSB737 has a single TSSOP, 8Bit, 512Mbyte NAND Flash. This device is connected to SAM9263 EBI0 Chip Select 3.

The signals used to interface with the NAND Flash are shown in the following table.

NAND Signal

SAM9263 Signal

Notes

*N_CE PD15/ *EBI0_CS3

*CS3 is set for NAND mode, but the pin is assigned to GPIO PD15

*N_WE *EBI0_NWE Dedicated NAND Write Enable

*N_RE *EBI0_NOE Dedicated NAND Read Enable

N_ALE EBI0_A21 Addresses are latched on the rising edge of *N_WE when ALE = 1 (A21 is used on the Atmel Eval board)

N_CLE EBI0_A22 Commands are latched on the rising edge of *N_WE when CLE = 1 (A22 is used on the Atmel Eval board)


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NAND Signal

SAM9263 Signal

Notes

N_RDY GPIO PA22 High indicates the NAND is ready for a new command

N_D07 EBI0_D07 8Bit Data bus, Addresses, Commands and Data are transferred via these signals

Table 3 – SAM9263 to NAND Flash Connections

4.4.1 NAND FLASH NOTES

1. *CS3 should be set as an 8bit wide device with 12 wait states (120ns at 100Mhz Master Clock).

2. The SAM9263 NAND Flash software should monitor GPIO PA22 to detect the completion of a NAND Flash operation (or alternately set PA22 as a high true interrupt input).

3. The Write Protect pin of the NAND Flash is tied high, so no Write Protect function is available.

4. Currently the CSB737 ships with a Samsung K9F4G08U0M (4Mbit, 512M x 8) device. Future products may ship with the same or larger capacity NAND device. Contact Cogent for updated information on the currently shipping NAND Flash.

4.5 16MBYTE PSRAM The CSB737 has an 8M x 16 PseudoStatic RAM (PSRAM) connected to EBI1 Chip Select 0. The high speed cross bar switch internal to the SAM9263 allows the 2D Graphics controller to access the PSRAM on EBI1 simultaneously with CPU accesses to memory or peripherals on EBI0. This eliminates the bandwidth issues created when refreshing and controlling highresolution LCD panels (VGA, 640x480 up to XGA, 1024x768). Systems with lowresolution panels (below VGA, 640x480) may choose to place the LCD frame buffer in main SDRAM memory, and use the PSRAM for general purpose memory.

4.5.1 16MBYTE PSRAM NOTES

1. The 16Mbyte PSRAM is connected to EBI1 *CS0 as a 16bit wide device with 8 wait states minimum (80ns at 100Mhz Master Clock).

4.6 DS1339 RTC A Maxim DS1339 provides a battery backed Real Time Clock function. It is on the SAM9263 I2C Bus at I2C 7bit address 0x68. It is expected that software will transfer the current time value from the DS1339 to the SAM9263 internal RTC function at power


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up and update the DS1339 when the SAM9263 RTC is changed. The DS1339 offer superior current consumption (<1 microamp) compared to the SAM9263 RTC internal function (~17 microamps). A standard 48ma/hr coin cell (CR2032) will power the DS1339 for ~3 years across the full temperature range versus ~120 days for the SAM9263 internal RTC.

The signals used to interface with the DS1339 are shown in the following table.

DS1339 Signal

SAM9263 Signal

Notes

SCL PB5/SCL I2C Bus Clock

SDA PB4/SDA I2C Bus Data

Table 4 – SAM9263 to DS1339 Connections

4.6.1 DS1339 RTC INTERFACE NOTES

1. The DS1339 is powered from the main 3.3V rail when present. This will reduce the current draw on the battery to less than 0.1 microamps.

2. The DS1339 has a provision for a rechargeable coin cell. This is not supported on the CSB737 and must not be enabled.

4.7 LM3489 3.3V REGULATOR A National Semiconductor LM3489 wide input switching regulator provides the CSB737, and optionally the rest of the system, with the main 3.3V rail. The input voltage can be from 6V to a maximum of 35V, though it is optimized for 9V to 15V operation for peak efficiency and maximum current output. However, across the entire input voltage range, the current output of this regulator is 4 Amps minimum. The CSB737 requires up to 2 Amps peak, leaving 2 Amps minimum for the rest of the system.

4.7.1 LM3489 3.3V REGULATOR NOTES

1. The LM3489 is disabled when the SODIMM signal *PWR_DIS is low. *PWR_DIS must be floated to enable the LM3489 (not driven high).

2. The SODIMM VIN Mounting Hole supplies the input to the LM3489 while the SODIMM VCC3 Mounting Hole provides the 3.3V to the system.


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5 SAM9263 ONCHIP PERIPHERALS 5.1 OVERVIEW

The SAM9263 has a number of onchip peripheral devices as well as a large number of user defined GPIOs. While it is beyond the scope of this document to provide detailed programming and interfacing information for the SAM9263 onchip peripherals, the following section describes the assignments for these devices and GPIOs as they are implemented on the CSB737.

5.2 SAM9263 TO SODIMM PERIPHERAL MAPPING The following table provides a high level view of the mapping from the various SAM9263 peripherals to the SODIMM ports.

SAM9263 Peripheral

SODIMM Port

Description and Notes

CAN CAN 0 Single Channel CAN 2.0B

SSI1 SSI May be used in SPI, Microwire or I2S mode

SPI0 SPI0 *SPI0_CS1 is routed to SODIMM GPIO6

SPI1 SPI1 *SPI1_CS1 is routed to SODIMM GPIO6

AC97 AC97 Standard AC97 Codec Interface

UART0 UART0 TXD, RXD, RTS and CTS

UART1 UART1 TXD and RXD only

UART2 UART1 TXD and RXD routed to U1_RTS and U1_CTS

STD UART DBG TXD/RXD via onboard RS232 buffer

LCD LCD LCD interface is supported in 16Bit mode

ISI VIP ISI is supported in 8 or 10Bit mode

KEYPAD Not available

MC0 SD/MMC 4Bit SDIO compatible

MC1 Not Available (pins are shared with SPI0)

CF CF Compact Flash Interface

TWI I2C I2C Bus (Atmel calls this “TwoWire Interface”)

USB HOST A USB HOST 0 12Mbit USB 2.0 Host Port 0


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SAM9263 Peripheral

SODIMM Port


USB HOST B USB HOST 1 12Mbit USB 2.0 Host Port 1

USB DEVICE USB DEVICE 12Mbit USB 2.0 Device Port

TIMER GPIO23 Timer I/O or GPIO

PWM0, 2 GPIO45 PWM or GPIO

10/100 MAC 10/100 Via LAN8700 RMII PHY

Table 5 –SAM9263 Peripheral to SODIMM Mapping

5.3 SAM9263 CHIP SELECTS As described in Section 4.1, the SAM9263 Chip Selects are used to enable the various peripheral devices on the CSB737 as well as expansion devices via the SODIMM connector. As a crossreference they are described again in the following table.

Chip Select Attached Device(s) Notes

*EBI0_CS0 S19GL512 Spansion Flash 16Bit no *WAIT

*EBI0_CS1 SDRAM 32Bit SDRAM Mode

*EBI0_CS2 SODIMM Expansion 16Bit with *WAIT

*EBI0_CS3 NAND Flash 8Bit NAND Flash Mode

*EBI0_CS4 Compact Flash 16Bit Compact Flash Mode

*EBI1_CS0 PSRAM 16Bit no *WAIT

Table 6 – SAM9263 Chip Select Assignments

5.4 SAM9263 GENERAL PURPOSE I/O ASSIGNMENTS The SAM9263 has six 32Bit General Purpose I/O ports (A to E). The GPIO usage on the CSB737 is described in the following tables. It is the responsibility of software to setup these bits for the correct direction and default state as well as the assignment of peripheral usage.

SAM 9263 Port A

DIR CSB737 Usage

Peri pheral A/B?


PA0 IN SPI0_MISO B SPI0 Master InSlave Out


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SAM 9263 Port A

DIR CSB737 Usage

Peri pheral A/B?


PA1 OUT SPI0_MOSI B SPI0 Master OutSlave In

PA2 OUT SPI0_CLK B SPI0 Clock

PA3 IO GPIO6 GPIO or SPI0 Chip Select 1 (Peripheral B)

PA4 IN SPI0_RDY SPI0 Ready or GPIO

PA5 OUT *SPI0_CS0 B SPI0 Chip Select 0

PA6 OUT SD_CLK A SD/MMC Clock

PA7 OUT SD_CMD A SD/MMC Command

PA8 IO SD_D0 A SD/MMC Data Bit 0




PA12 OUT N/A Set as Output and drive 0

PA13 OUT CAN0_TXD A CAN Transmit Data

PA14 IN CAN0_RXD A CAN Receive Data

PA15 IO GPIO1 GPIO or IRQ1 (Peripheral B)







PA22 IN NRDY NAND Ready/Busy (1 = Ready)




PA26 OUT U0_TXD A UART0 Transmit Data

PA27 IN U0_RXD A UART0 Receive Data


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SAM 9263 Port A

DIR CSB737 Usage

Peri pheral A/B?


PA28 OUT U0_RTS A UART0 Request To Send

PA29 IN U0_CTS A UART0 Clear To Send



Table 7 – SAM9263 GPIO Port A Assignments

SAM 9263 Port B

DIR CSB737 Usage

Peri pheral A/B?


PB0 IN AC_SYNC A AC97 SYNC from Codec

PB1 IN AC_BCLK A AC97 Bit Clock from Codec

PB2 OUT AC_SDOUT A AC97 Serial Data to Codec

PB3 IN AC_SDIN A AC97 Serial Data from Codec

PB4 IO I2C_SDA A TwoWire Interface Data

PB5 IO I2C_SCL A TwoWire Interface Clock

PB6 IO SSI_FRM A SSI1 Frame

PB7 IO SSI_CLK A SSI Clock

PB8 OUT SSI_TXD A SSI Transmit

PB9 IN SSI_RXD A SSI Receive

PB10 IO SSI_MCLK A SSI Master Clock

PB11 IN SPI1_RDY SPI1 Ready or GPIO

PB12 IN SPI1_MISO A SPI1 Master InSlave Out

PB13 OUT SPI1_MOSI A SPI1 Master OutSlave In

PB14 OUT SPI1_CLK A SPI1 Clock

PB15 OUT *SPI1_CS0 A SPI1 Chip Select 0

PB16 IO GPIO7 GPIO or SPI1 Chip Select 1 (Peripheral A)

PB17 IO GPIO2 GPIO or Timer A IO2 (Peripheral B)

PB18 IO GPIO3 GPIO or Timer B IO2 (Peripheral B)


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SAM 9263 Port B

DIR CSB737 Usage

Peri pheral A/B?


PB19 OUT *AC_RST AC97 Codec Reset (0 = Reset)

PB20 IN *PIRQ Touch (PEN) Interrupt, Low True

PB21 IN *EXP_IRQ Expansion Interrupt, Low True

PB22 IN CF_RDY Compact Flash Card Ready or Interrupt

PB23 IN *CF_CD Compact Flash Card Detect (0 = Card In)

PB24 OUT CF_RST Compact Flash Card Reset (1 = Reset)

PB25 OUT N/A Set as Output and drive 0

PB26 OUT N/A Set as Output and drive 0

PB27 IO GPIO8 GPIO or PWM2 (Peripheral B)

PB28 IO GPIO9 GPIO or Timer 0 Clock (Peripheral B)

PB29 OUT LCD_BKL GPIO or PWM3 (Peripheral B)

PB30 IN *I2C_INT Shared I2C Devices Interrupt, Low True

PB31 OUT *LOW_PWR Drive 0 to indicate sleep to ram mode

Table 8 – SAM9263 GPIO Port B Assignments

SAM 9263 Port C

DIR CSB737 Usage

Peri pheral A/B?


PC0 OUT LCD_VS A LCD VERTICAL SYNC

PC1 OUT LCD_HS A LCD HORIZONTAL SYNC

PC2 OUT LCD_PCLK A LCD PIXEL CLOCK

PC3 OUT LCD_OE A LCD OUTPUT ENABLE

PC4 OUT LCD_B1 B LCD BLUE BIT 1 (LCDD3)





PC9 OUT LCD_G0 B LCD GREEN BIT 0 (LCDD10)


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SAM 9263 Port C

DIR CSB737 Usage

Peri pheral A/B?







PC15 OUT LCD_R1 B LCD RED BIT 1 (LCDD19)





PC20 OUT N/A Set as Output and drive 0





PC25 OUT E_CRSDV B RMII Carrier Sense/Data Valid



PC28 IO GPIO4 GPIO OR PWM0 (Peripheral A)

PC29 IO GPIO5 GPIO OR PWM2 (Peripheral B)

PC30 IN D_RXD A Debug UART Receive (via RS232)

PC31 OUT D_TXD A Debug UART Transmit (via RS232)

Table 9 – SAM9263 GPIO Port C Assignments

SAM 9263 Port D

DIR CSB737 Usage

Peri pheral A/B?


PD0 OUT U1_TXD A UART1 Transmit


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SAM 9263 Port D

DIR CSB737 Usage

Peri pheral A/B?


PD1 IN U1_RXD A UART1 Receive Data

PD2 OUT U1_RTS UART1 Request To Send (GPIO Mode) or UART2 Transmit Data (Peripheral A)

PD3 IN U1_CTS UART1 Clear To Send (GPIO Mode) or UART2 Receive Data (Peripheral A)

PD4 IN GPIO0 GPIO or FIQ (Peripheral A)

PD5 IN *WAIT A Expansion and Compact Flash Wait

PD6 OUT *EBI0_CS4 A Set *CS4 in Compact Flash Mode

PD7 OUT N/A Set as Output and drive 0

PD8 OUT *CF_CE1 A Compact Flash Chip Enable 1

PD9 OUT *CF_CE2 A Compact Flash Chip Enable 2

PD10 OUT N/A Set as Output and drive 0

PD11 OUT *EBI0_CS2 A SODIMM Expansion Chip Select

PD12 OUT EBI0_A23 A SAM9263 Address Bit 23



PD15 OUT *EBI_CS3 A NAND Flash Chip Select

PD1631 IO EBI0_D1631 A EBI0 Data Bits 16 31

Table 10 – SAM9263 GPIO Port D Assignments

SAM 9263 Port E

DIR CSB737 Usage

Peri pheral A/B?


PE0 IN VIP_D0 A Video Input Port Data Bit 0







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SAM 9263 Port E

DIR CSB737 Usage

Peri pheral A/B?




PE8 IN VIP_PCLK A Video Input Port Pixel Clock

PE9 IN VIP_HS A Video Input Port Horizontal Sync

PE10 IN VIP_VS A Video Input Port Vertical Sync

PE11 IN VIP_MCLK A Video Input Port Master Clock

PE12 IN VIP_D8 B Video Input Port Data Bit 8

PE13 IN VIP_D9 B Video Input Port Data Bit 9

PE14 OUT N/A Set as Output and drive 0







PE21 IN E_REFCK RMII Ethernet Reference Clock (50Mhz)


PE23 OUT E_TXD0 A RMII Ethernet Transmit Data Bit 0

PE24 OUT E_TXD1 A RMII Ethernet Transmit Data Bit 1

PE25 IN E_RXD0 A RMII Ethernet Receive Data Bit 0

PE26 IN E_RXD1 A RMII Ethernet Receive Data Bit 1

PE27 IN E_RXER A RMII Ethernet Receive Error

PE28 OUT E_TXEN A RMII Ethernet Transmit Enable

PE29 OUT E_MDC A RMII Ethernet Management Bus Clock

PE30 IO E_MDIO A RMII Ethernet Management Bus Data


Table 11 – SAM9263 GPIO Port E Assignments


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5.4.1 SAM9263 GPIO NOTES

1. An asterisk (i.e. *PIRQ) before a signal indicates that it is a low true signal.

2. The SODIMM interface defines 10 GPIOS, numbered GPIO0 to GPIO9. Some of these have a preferred usage such as GPIO1/IRQ, which is used as an interrupt. This preference is not required and must be programmed by software to be used.

3. Signals indicated by N/A are not available.

4. Unused SAM9263 GPIO must be programmed as outputs and set to 0 to insure the lowest noise and power consumption. These are indicated with an OUT in the direction column and a 0 in the usage column.

5. All SODIMM inputs should be tied to VCC3 or GND with a 10K ohm resistor on the target board. Do not leave unconnected.

6. The “Peripheral A/B?” column defines what peripheral function should be programmed in order to get the stated functionality. “A” indicates peripheral function A, while “B” indicates alternate function B. No letter indicates an assignment to GPIO.

5.5 SAM9263 INTERRUPT PIN ASSIGNMENTS Any SAM9263 GPIO can be used as an interrupt input to the SAM9263 Advanced Interrupt Controller. The following table describes the GPIO that are, or can be, assigned as interrupts on the CSB737. The SODIMM GPIO0 and GPIO1 are shown with the preferred use, but software is required to enable the interrupt for any signal.

SAM9263 GPIO

CSB737 Usage


PD4 GPIO0 General Purpose I/O or Interrupt from Target Board

PA15 GPIO1 General Purpose I/O or Interrupt from Target Board

PB20 *PIRQ Touch Controller Interrupt, Low True

PB21 *EXP_IRQ Expansion Interrupt

PA22 N_RDY NAND Flash Ready, High True

PB22 CF_RDY Compact Flash Card Ready (Memory Mode), High True or Compact Flash Card Interrupt (I/O Mode), High True

PB23 *CF_CD Compact Flash Card Detect (0 = card inserted)

PB30 *I2C_INT Shared I2C Interrupt, Low True

Table 12 – SAM9263 Interrupt Pin Assignments


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5.6 SAM9263 UARTS The SAM9263 has 4 available UARTS. They are the UARTS 0, 1, 2 and the Debug UART. The Debug UART is buffered with an RS232 Transceiver on the CSB737 and brought to the SODIMM as DBG_TXD and DBG_RXD. Refer to the SAM9263 Users Manual for more information about the various SAM9263 UARTS. .

The signals used to interface the SAM9263 UARTS to the SODIMM are shown in the following table.

SAM9263 Signal

SODIMM Signal

Notes

PA26/TXD0 U0_TXD UART0 Transmit Data

PA27/RXD0 U0_RXD UART0 Receive Data

PA28/RTS0 U0_RTS UART0 Request To Send

PA29/CTS0 U0_CTS UART0 Clear To Send

PD0/TXD1 U1_TXD UART1 Transmit Data

PD1/RXD1 U1_RXD UART1 Receive Data

PD2/TXD2 U1_RTS UART1 Request To Send

PD3/RXD2 U1_CTS UART1 Clear To Send

PC31/DTXD DBG_TXD Debug Transmit Data (RS232)

PC30/DRXD DBG_RXD Debug Receive Data (RS232)

Table 13 – SAM9263 UARTS to SODIMM Connections

5.6.1 SAM9263 UART NOTES

1. SAM9263 UART1 handshaking is not available due to other pin assignments. UART1 TXD and RXD are connected to SODIMM UART1 TXD and RXD. UART2 TXD and RXD are connected to SODIMM UART1 RTS and CTS respectively. They can either be used as UART1 handshaking RTS/CTS (in GPIO mode) or as an extra twowire UART.

2. SAM9263 UARTS 0, 1 and 2 all support 115Kb/s Standard Infrared (SIR) mode.

5.7 SAM9263 SPI CONTROLLERS The SAM9263 provides two highspeed, multislave Serial Peripheral Interface (SPI) controllers. SPI0 and SPI1 are available on SODIMM SPI0 and SPI1 ports respectively. Each controller can interface with multiple SPI slaves with minimal host intervention.


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The internal SAM9263 DMA controller can be used to transfer data between the SPI controllers and system memory for very high data rates (up to 30Mbits/sec). Refer to the SAM9263 Users Manual for detailed programming information.

The signals used to interface the SAM9263 SPI0 and SPI1 controllers to the SODIMM are shown in the following table.

SAM9263 Signal

SODIMM Signal

Notes

PA2/SPI0_CLK SPI0_CLK SPI0 Clock

PA5/*SPI0_CS0 *SPI0_CS0 SPI0 Chip Select 0

PA3/*SPI0_CS1 GPIO6 SPI0 Chip Select 1 OR GPIO6

PA1/SPI0_MOSI SPI0_MOSI SPI0 Master Out/Slave In

PA0/SPI0_MISO SPI0_MISO SPI0 Master In/Slave Out

PA4/*SPI0_CS2 SPI0_RDY SPI0 Ready (or Interrupt)

PB14/SPI1_CLK SPI1_CLK SPI0 Clock

PB15/*SPI1_CS0 *SPI1_CS0 SPI0 Chip Select 0

PB16/*SPI1_CS1 GPIO7 SPI0 Chip Select 1

PB13/SPI1_MOSI SPI1_MOSI SPI0 Master Out/Slave In

PB12/SPI1_MISO SPI1_MISO SPI0 Master In/Slave Out

PB11/*SPI0_CS3 SPI0_RDY SPI0 Ready (or Interrupt)

Table 14 – SAM9263 SPI Controllers to SODIMM Connections

5.7.1 SAM9263 SPI INTERFACE NOTES

1. SODIMM SPI1 is used off board to interface with the AD7843 Touch Controller on the CSB702 “CSB7xx Base Board” or the optional CSB909xx LCD boards. This is the preferred use for this port.

2. SODIMM SPI0 is routed to the I/O sites of the CSB902 “CSB7xx I/O Expansion board”.

5.8 SAM9263 SSI CONTROLLER The SAM9263 supports two highspeed Synchronous Serial Interface (SSI) controllers, SSI0 and SSI1. SSI0 is shared with the AC97 port and is available only if the AC97 port is not used. SSI1 can be used to connect various peripherals to the CSB737 including I2S audio Codec’s. The internal SAM9263 DMA controller can be used to transfer data


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between the SSI Device on the target board and system memory for very high data rates (up to 30Mbits/sec). Refer to the SAM9263 Users Manual for detailed programming information.

The signals used to interface the SAM9263 SSI1 controller to the SODIMM are shown in the following table.

SAM9263 Signal

SODIMM Signal

Notes

PB7/TK1 SSI_CLK SSI Clock

PB6/TF1 SSI_FRM SSI Frame Sync

PB8/TD1 SSI_TXD SSI Transmit Data

PB9/RD1 SSI_RXD SSI Read Data

PB10/RK1 SSI_MCLK SSI Master Clock

SSI_RDY SSI Ready or Interrupt

Table 15 – SAM9263 SSI Controller to SODIMM Connections

5.8.1 SAM9263 SSI INTERFACE NOTES 1. MCI0_CK can be used with SODIMM SPI0 (SAM9263 SPI0) to access SAM9263

SD/MMC Card controller 0 (MCI0).

2. Revision P1 of the CSB737 does not support the SSI port.

3. Revision P2 and P3 have the SSI_RXD signal on the SODIMM pin SSI_RDY. Later revisions will fix this and the pinout will be as described above.

5.9 SAM9263 I2C INTERFACE The SAM9263 has a full speed, master/slave I2C Serial Controller (referred to by Atmel as TWI, or TwoWire Interface). Refer to the SAM9263 Users Manual for detailed programming information.

The signals used to interface the SAM9263 TWI controller to the SODIMM are shown in the following table.

SAM9263 Signal

SODIMM Signal

Notes

PB5/TWCK I2C_SCL I2C Bus Clock

PB4/TWD I2C_SDA I2C Bus Data


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SAM9263 Signal

SODIMM Signal

Notes

PB30 *I2C_INT Shared I2C Bus Interrupt

Table 16 – SAM9263 I2C Controller to SODIMM Connections

5.10 SAM9263 4BIT SD/MMC CONTROLLER The SAM9263 has two highspeed 4Bit Secure Digital (SD/MMC) controllers, MCI0 and MCI1. MCI0 shares its pins with SPI0 and is only available if SPI0 is not used and PA12/MCI0_CLK (used for SODIMM SSI_RDY) is assigned as MCI0_CLK. MCI1 can be used to interface with 1Bit and 4Bit MMC, SD and SDIO Cards with minimal host intervention. The internal SAM9263 DMA controller can be used to transfer data between the SD/MMC Socket on the target board and system memory for very high data rates (up to 100Mbits/sec in 4Bit mode). Refer to the SAM9263 Users Manual for detailed programming information.

The signals used to interface the SAM9263 SD/MMC controller MCI1 to the SODIMM are shown in the following table.

SAM9263 Signal

SODIMM Signal

Notes

PA6/MC1_CLK SD0_CLK SD Card 0 Clock, (SPI Mode Clock)

PA7/MC1_CMD SD0_DIN_CMD SD Card 0 Command (SPI Mode MOSI)

PA8/MC1_D0 SD0_DOUT_D0 SD Card 0 Data 0 (SPI Mode MISO)

PA9/MC1_D1 SD0_IRQ_D1 SD Card 0 Data 1 (SPI Mode IRQ)

PA10/MC1_D2 SD0_D2 SD Card 0 Data 2 (Unused in SPI mode)

PA11/MC1_D3 SD0_CS_D3 SD Card 0 Data 3 (SPI Mode Chip Select)

Table 17 – SAM9263 SD/MMC Controller to SODIMM Connections

5.10.1 SAM9263 SD/MMC CONTROLLER NOTES

1. There is no dedicated hardware card detect signal on the CSB737. Software may use either a polling method or an external mechanism (such as the I2C GPIO Expander used on the CSB702).

2. On the CSB702 “CSB7xx Base Board” an I2C GPIO expander is used to read the state of the SD/MMC Card socket Card Detect and Write Protect pins. Refer to the CSB702 HW Reference Manual for more information.

3. Controlling power (if desired) to the SD/MMC card socket is left to the target board designer.


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4. MCI0_CLK is only available on revision P2 or later of the CSB737 where it is routed to SODIMM signal SSI_RDY.

5.11 SAM9263 COMPACT FLASH INTERFACE The SAM9263 supports the Compact Flash Interface using the internal PCMCIA/CF Memory Controller. The CSB737 supports one socket via the SODIMM connector. Refer to the SAM9263 Users Manual for detailed programming information.

The signals used to interface with the Compact Flash are shown in the following table.

SAM9263 Signal

SODIMM Signal

Notes

PD8/*EBI0_CFCE1 *CF_CE1 Chip Enable 1

PD9/*EBI0_CFCE2 *CF_CE2 Chip Enable 2

*EBI0_OE *CF_OE Memory mode Output Enable

*EBI0_WE *CF_WE Memory mode Write Enable

*EBI0_BS1 *CF_IOR I/O Mode Read Enable

*EBI0_BS3 *CF_IOW I/O Mode Write Enable

EBI0_A22 *CF_REG I/O Mode Enable

PD5/*EBI0_WAIT *CF_WAIT Wait signal to extend access time

PB22 CF_RDY/*INT Ready (Memory mode), or Interrupt (I/O mode)

PB23 *CF_CD Card Detect, 0 = Card Inserted

PB24 CF_RST Card Reset, 1= reset

Table 18 – SAM9263 Compact Flash Controller to SODIMM Connections

5.11.1 SAM9263 COMPACT FLASH INTERFACE NOTES

1. The Data, Address and Control signals must be buffered on the target board before routing them to the Compact Flash socket.

2. The SAM9263 supports two Compact Flash sockets via *EBI0_CS4 and *EBI0_CS5. On the CSB737 only one socket is supported and *EBI_CS5 is unused.

3. Controlling power to the Compact Flash card is left to the target board designer. On the CSB902 “CSB7xx I/O Expansion Board” power to the Compact Flash Socket is enabled when *CF_CD = 0.


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5.12 SAM9263 USB HOST CONTROLLER The SAM9263 has two 12Mbit, USB 2.0 compliant Host Ports. On the CSB737, HDPA and HDMA are routed to SODIMM signals USBH0_DP and USBH0_DM respectively, while HDPB and HDMA are routed to USBH1_DP and USBH1_DM.

5.12.1 SAM9263 USB HOST INTERFACE NOTES

1. Power control for each external host port is left to the target board designer.

2. Over Current Indication is also left to the discretion of the target board designer.

5.13 SAM9263 USB DEVICE CONTROLLER The SAM9263 has a single, 12Mbit, USB 2.0 compliant Device. On the CSB737 DDP and DDM are routed to SODIMM signals USBD_DP and USBD_DM respectively. Refer to the SAM9263 Users Manual for detailed programming information.

5.13.1 SAM9263 USB DEVICE INTERFACE NOTES

1. The Cable Detect method if desired, is left to the target board designer. On the CSB702 “CSB7xx Base Board” an I2C GPIO expander is used to read the state of the USB Device Power pin. Refer to the CSB702 HW Reference Manual for more information.

2. The Soft Connect method if desired, is left to the target board designer. On the CSB702 “CSB7xx Base Board” an I2C GPIO expander is used to control Soft Connect. Refer to the CSB702 HW Reference Manual for more information.

5.14 SAM9263 AC97 AUDIO CODEC INTERFACE The SAM9263 supports an external audio codec using the AC97 bus interface standard. On the CSB737 these signals are routed to the SODIMM AC97 Port.

The signals used to interface with the AC97 Port are shown in the following table.

SAM9263 Signal

SODIMM Signal

Notes

PB19 *AC_RST AC97 Codec Reset

PB1/AC97CK/TK0 AC_BCLK AC97 Codec Bit Clock

PB0/AC97FS/TF0 AC_SYNC AC97 Frame Sync


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SAM9263 Signal

SODIMM Signal

Notes

PB2/AC97TX/TD0 AC_SDOUT AC97 Serial Data Out

PB3/BMS/AC97RX/RD0 AC_RXD AC97 Serial Data In

Table 19 – SAM9263 AC97 Controller to SODIMM Connections

5.14.1 AC97 AUDIO INTERFACE NOTES

1. The AC97 signals are multiplexed with SSI0. If desired these signals could be assigned to I2S/SSI use.

2. *AC_RST is a GPIO and not part of the SAM9263 AC97 Controller.

3. PB3/BMS/AC97RX/RD0 is the SAM9263 signal BMS (Boot Mode Select) during reset. On the CSB737 this signal is pulled low via a 10K resistor. This selects 16bit boot from *EBI_CS0 (S29GL512 Spansion Flash).

5.15 SAM9263 LCD CONTROLLER The SAM9263 has an internal LCD controller. This controller supports LCD panel resolutions up to 1024 x 768.

The signals used to interface to the SODIMM LCD Port are shown in the following table.

SAM9263 Signal

SODIMM Signal

Notes

Tied to ground LCD_B0 Blue Bit 0

PC15/LCD_D19 LCD_B1 Blue Bit 1





PC9/LCD_D10 LCD_G0 Green Bit 0






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SAM9263 Signal

SODIMM Signal

Notes


Tied to ground LCD_R0 Red Bit 0

PC4/LCD_D3 LCD_R1 Red Bit 1





PC0/LCD_VSYNC LCD_VS Vertical Sync

PC1/LCD_HSYNC LCD_HS Horizontal Sync

PC2/LCD_PCLK LCD_PCLK Pixel Clock

PC3/LCD_DEN LCD_OE Data Output Enable

PB29/PWM3 LCD_BKL Backlight Enable (1 = on, 0 = off)

Table 20 – SAM9263 LCD Interface to SODIMM Connections

5.15.1 SAM9263 LCD NOTES

1. The SAM9263 LCD can output 16Bit or 24Bit LCD Data. Only 16Bit is supported on the CSB737.

2. To improve performance, a 16Mbyte PSRAM device is located on EBI1 Chip Select 0 (*EBI1_CS0). Software can use this memory to hold the LCD frame buffer. The internal cross bar switch of the SAM9263 insures that refresh accesses for the LCD will not interfere with CPU or DMA accesses to the rest of the system.

3. LCD_BKL is connected to SAM9263 PB29/PWM3. This allows the LCD backlight to be controlled in PWM mode if desired. Refer to the appropriate documentation to see if PWM mode is supported by the attached LCD backlight power supply (on the CSB702 it is).

5.16 2D GRAPHICS CONTROLLER The SAM9263 contains a 2D Graphics accelerator supporting various functions such as: Line Draw; Polygon draw and fill; Block Move; and Line Clipping. This controller operates on the designated frame buffer memory and has no associated external signals.


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5.17 SAM9263 IMAGE SENSOR INTERFACE The SAM9263 has an internal Image Sensor Interface (ISI). On the CSB737, this port can support 8 or 10Bit sensors as well as video input using standard YUV or RGB formats.

The signals used to interface to the SODIMM Video Input Port are shown in the following table.

SAM9263 Signal

SODIMM Signal

Notes

PE0/ISI_D0 VIP_D0 Image Sensor Data Bit 0








PE12/KBDR0/ISI_D8 VIP_D8 Image Sensor Data Bit 8 (10Bit mode only)

PE13/KBDR1/ISI_D9 VIP_D9 Image Sensor Data Bit 9 (10Bit mode only)

PE9/TIOB1/ISI_HSYNC VIP_HSYNC Image Sensor Horizontal Sync

PE10/PWM3/ISI_VSYNC VIP_VSYNC Image Sensor Vertical Sync

PE8/TIOA1/ISI_PCK VIP_PCLK Image Sensor Pixel Clock

PE11/PCK3/ISI_MCK VIP_MCLK Master Clock to Image Sensor

Table 21 – SAM9263 Image Sensor Interface to SODIMM Connections

5.17.1 SAM9263 IMAGE SENSOR NOTES

4. The SAM9263 Image Sensor Interface supports 8Bit or 10Bit mode. Both are available on the CSB737.

5. VIP_MCLK is an output to the image sensor and is not always needed. In that case, the signal may be used as PWM3 or as a GPIO for ISI control.

5.18 SAM9263 10/100 ETHERNET MAC AND LAN8700 PHY The SAM9263 has an onchip 10/100 Ethernet MAC (Media Access Controller). This


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controller support 10Mbit or 100Mbit transfers according to the IEEE802.3 standard. The SAM9263 MAC requires an external PHY to interface to a standard 10/100 twisted pair cable. On the CSB737 an SMSC LAN8700 PHY is used.

The signals used to interface the MAC to the LAN8700 are shown in the following table.

SAM9263 MAC Signal

LAN8700 PHY Signal

Notes

PE21/E_TXCK CLKIN 50Mhz clock from onboard oscillator

PE23/E_TXD0 TX_D0 Transmit Data Bit 0 to PHY

PE24/E_TXD1 TX_D1 Transmit Data Bit 1 to PHY

PE25/E_RXD0 RX_D0 Receive Data Bit 0 from PHY

PE26/ERTXD1 RX_D1 Receive Data Bit 1 from PHY

PE27/ERXER RX_ER Receive Error from PHY

PE28/ETXEN TX_EN Transmit Enable to PHY

PE29/EMDC MDC MII Bus Clock to PHY

PE30/EMDIO MDIO MII Bus Data to/from PHY

PC25/ERXDV CRS_DV Carrier Send/Data Valid from PHY

Table 22 – SAM9263 MAC to PHY Connections

5.18.1 SAM9263 ETHERNET MAC/PHY NOTES

1. The SAM9263 MAC interfaces to the LAN8700 PHY in RMII mode. Software must program the MAC accordingly. Refer to the SAM9263 documentation for more detail.

2. LAN8700 signal LED_SPD is connected to SODIMM *E_SPD. When a 100Mbit link is valid, this signal will go low.

3. LAN8700 signals LED_LNK and LED_ACT are combined and connected to SODIMM *E_LNK. When a link is valid (10Mbit or 100Mbit), this signal will go low. It will go high for 200msec (thus “blinking” the LED) when there is receive or transmit activity.

4. LAN8700 signals TXP/TXN and RXP/RXN are connected to SODIMM signals E_TD+/E_TD and E_RD+/E_RD respectively.

5. The LAN8700 PHY is located at MII Bus address 0x1F.


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5.19 UNAVAILABLE SAM9263 PERIPHERALS/SIGNALS The following SAM9263 Peripherals/Signals are not available on the CSB737. Note that GPIO usage, including unavailable GPIO, is shown in section 5.4.

SAM9263 Peripheral/Signal


PD7/RTS1/*CS5 Unconnected

PD6/CTS2/*CS4 Mapped to Compact Flash use

SHDN Unconnected

WKUP Always tied high

SSI0/AC97 Used for AC97

MMC1/SPI0 Used as SPI0

KBDR03 Unconnected

KBDC02 Unconnected

LCD_D1623 Unconnected

EBI1 SDRAM I/F Used for Ethernet RMII

EBI1 NAND I/F Used for Ethernet RMII

Table 23 – SAM9263 Unavailable Peripherals/Signals


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6 CSB737 CLOCKING 6.1 SAM9263 INPUT CLOCKS

The SAM9263 is provided with two clocks. The first is a 32.768Khz crystal connected to the SAM9263 XIN32/XOUT32 pins. It is used by the SAM9263 for it’s internal RTC as well as for power management and power sequencing. This clock is also referred to as the “Slow Clock”.

NOTE: There is excessive noise on the 32.768Khz oscillator that may cause it to run higher than specified (as high as 35Khz has been observed). For power management or basic alarm use this is not an issue. For real time clock use software should use the DS1339 for accurate time. This issue is being investigated, but no fix is planned.

The second clock is an 18.432Mhz crystal attached to the SAM9263 XIN/XOUT oscillator pins. This clock is used to drive the internal CPU and System PLL’s. The SAM9263 core clock is set to 198.656Mhz (PLLA Divide = 9, Multiply = 97). Master Clock (MCK) is the core divided by 2, or 99.328Mhz (or simply 100Mhz).

6.2 SAM9263 OUTPUT CLOCKS The SAM9263 drives one clock that is used by the CSB737. This clock is SDCLK and is used to drive the SDRAM and the SODIMM signal EXP_CLK. SDCLK is a buffered version of the internal Maser Clock (MCK).

6.3 RMII AND LAN8700 PHY CLOCK A 50Mhz oscillator is used on the CSB737 to supply the RMII reference clock to the SAM9263 Ethernet Controller and to the LAN8700 PHY. It is used to derive all 10/100 Ethernet interface clocks.


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7 CSB737 POWER MANAGEMENT 7.1 SAM9263 WAKEUP AND SHUTDOWN

The CSB737 does not support the use of the SAM9263 Wakeup or Shutdown pins. On the CSB737 the core regulator is always enabled. However, placing the SDRAM into selfrefresh mode and reducing the internal Core Clock and Master Clock to 512Hz (32.768Khz slow clock divided by 64) can achieve very low power. In this “QuasiStatic” mode, the SAM9263 itself consumes less than 5mw, but remains alert to handle interrupts.

7.2 SODIMM *LOW_PWR SAM9263 GPIO PB31 is routed to the SODIMM *LOW_PWR pin. This allows external devices to be disabled if desired during “QuasiStatic” mode (by setting PB31 = 0 prior to going into “QuasiStatic” mode”).

7.3 SODIMM *PWR_DIS This signal can be driven low by external power management devices to disable the 3.3Vswitching regulator. This will power the entire CSB737 down. Care must be taken to insure that the unpowered pins of the CSB737 devices will not interfere with other external devices that may be connected to those pins. Floating this signal (do not drive high) will enable the 3.3Vswitching regulator.


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8 CSB737 SOFTWARE 8.1 OVERVIEW

Due to the various resources contained on the CSB737, both on and off the SAM9263, it is necessary to initialize a large number of SAM9263 registers and external devices before correct operation can begin. These values and their proper sequencing are beyond the scope of this document. Contact Cogent for example boot initialization code.


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9 SODIMM FORMAT AND PINOUT 9.1 OVERVIEW

This section defines the pinout of the SODIMM connector.

9.2 SODIMM FORMAT The CSB737 is fully compatible with the Cogent CSB7xx family of SODIMM System On a Module (SOM) components. The SODIMM form factor is based on the JEDEC standard MO244 with 2.5V keying (note that this keying is not electrically significant for the CSB737, only for mechanical purposes). The only exceptions are the length of the module, 2.0” vs. 1.0” standard, and the presence of two .125” plated holes for mounting and power. Refer to the “CSB7xx R2 Design Guide” for detailed layout dimensions of the target board SODIMM socket and mountinghole requirements.

9.3 SODIMM PINOUT The CSB737 has a 200pin SODIMM edge connector, with two sides, A and B. The following table describes the pinout of the connector. An “N” in the column marked CSB indicates that the signal is not supported by the CSB737. In cases where the CSB7xx R2 SODIMM pinout defines multiple functions, the function used by the CSB737 is shown. For example, the CSB737 routes the SAM9263 AC97 interface to the SODIMM AC97/I2S port as opposed to I2S audio. Therefore the multifunction AC97/I2S port is labeled as AC97 for the CSB737.

PIN NAME CSB DESCRIPTION

A1 DBG_TXD DEBUG RS232 TRANSMIT

B1 DBG_RXD DEBUG RS232 RECEIVE

A2 RTC_BAT 3V BATTERY INPUT TO DS1338 RTC

B2 *LOW_PWR LOW POWER INDICATION FROM CPU

A3 *PWR_DIS VCC3 DISABLE, 0 = OFF, FLOAT = ON

B3 *I2C_INT I2C DEVICE INTERRUPT

A4 I2C_SCL I2C BUS CLOCK

B4 I2C_SDA I2C BUS DATA

A5 CPU_DBG0 N CPU SPECIFIC DEBUG SIGNAL

B5 CPU_DBG1 N CPU SPECIFIC DEBUG SIGNAL


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A6 *CPU_TRST JTAG RESET

B6 CPU_TMS JTAG MODE

A7 CPU_TCK JTAG CLOCK

B7 CPU_TDI JTAG DATA IN

A8 CPU_TDO JTAG DATA OUT

B8 *RST_IN RESET INPUT (0 = RESET)

A9 GND

B9 GND

A10 CAN0_TXD CAN 0 TRANSMIT

B10 CAN0_RXD CAN 0 RECEIVE

A11 CAN1_TXD N CAN 1 TRANSMIT

B11 CAN1_RXD N CAN 1 RECEIVE

A12 GND

B12 GND

A13 USBH0_P USB HOST PORT 0 PLUS

B13 USBH1_P USB HOST PORT 1 PLUS

A14 USBH0_N USB HOST PORT 0 MINUS

B14 USBH1_N USB HOST PORT 1 MINUS

A15 GND

B15 USBD_P USB DEVICE PORT PLUS

A16 GND

B16 USBD_N USB DEVICE PORT MINUS

A17 GND

B17 GND

A18 E_TD ETHERNET TRANSMIT DATA MINUS

B18 E_RD ETHERNET RECEIVE DATA MINUS

A19 E_TD+ ETHERNET TRANSMIT DATA PLUS

B19 E_RD+ ETHERNET RECEIVE DATA PLUS


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A20 *E_LNK ETHERNET LINK LED

B20 *E_SPD ETHERNET SPEED LED

A21 *RST_OUT SYSTEM RESET

B21 *PIRQ TOUCH SCREEN INTERRUPT

A22 GPIO0/IRQ0 GPIO 0 (INTERRUPT VIA PD4/FIQ)

B22 GPIO1/IRQ1 GPIO 1 (INTERRUPT VIA PA15/IRQ1)

A23 GPIO2/TMR0 GPIO 2 (TIMER VIA PB17/TIOA2)

B23 GPIO3/TMR1 GPIO 3 (TIMER VIA PB18/TIOB2)

A24 GPIO4/PWM0 GPIO 4 (PWM VIA PC28/PWM0)

B24 GPIO5/PWM1 GPIO 5 (PWM VIA PC29/PWM2)

A25 GPIO6/

*SPI0_CS1 GPIO BIT 6 (SPI 0 CHIP SELECT 1 VIA PA3/*SPI0_CS1)

B25 GPIO7/

*SPI1_CS1 GPIO BIT 7 (SPI 1 CHIP SELECT 1 VIA PB16/*SPI1_CS1)

A26 GPIO8 GPIO BIT 8

B26 GPIO9 GPIO BIT 9

A27 SPI0_RDY/INT SPI 0 READY OR INTERRUPT

B27 SPI0_MOSI SPI 0 MASTER OUT/SLAVE IN

A28 SPI0_MISO SPI 0 MASTER IN/SLAVE OUT

B28 *SPI0_CS0 SPI 0 CHIP SELECT 0

A29 SPI0_CLK SPI 0 CLOCK

B29 SPI1_RDY/INT SPI 1 READY OR INTERRUPT

A30 SPI1_MOSI SPI 1 MASTER OUT/SLAVE IN

B30 SPI1_MISO SPI 1 MASTER IN/SLAVE OUT

A31 *SPI1_CS0 SPI 1 CHIP SELECT 0

B31 SPI1_CLK SPI 1 CLOCK

A32 GND

B32 GND


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A33 SD0_DOUT_D0 SD/MMC CARD 0 DATA 0

B33 SD0_IRQ_D1 SD/MMC CARD 0 DATA 1 (SDIO IRQ)

A34 SD0_D2 SD/MMC CARD 0 DATA 2

B34 SD0_CS_D3 SD/MMC CARD 0 DATA 3

A35 SD0_DIN_CMD SD/MMC CARD 0 COMMAND

B35 SD0_CLK SD/MMC CARD 0 CLOCK

A36 U0_TXD UART 0 TRANSMIT

B36 U0_RXD UART 0 RECEIVE

A37 U0_RTS UART 0 REQUEST TO SEND

B37 U0_CTS UART 0 CLEAR TO SEND

A38 U0_DTR/ U2_TXD N

UART 0 DATA TERMINAL READY OR UART 2 TRANSMIT

B38 U0_DSR/ U2_RXD N

UART 0 DATA SET READY OR UART 2 RECEIVE

A39 U0_DCD/ U2_RTS N

UART 0 DATA CARRIER DETECT OR UART 2 REQUEST TO SEND

B39 U0_RI/ U2_CTS N

UART 0 RING INDICATOR OR UART 2 CLEAR TO SEND

A40 U1_TXD UART 1 TRANSMIT

B40 U1_RXD UART 1 RECEIVE

A41 U1_RTS UART 1 REQUEST TO SEND (GPIO VIA PD2)

B41 U1_CTS UART 1 CLEAR TO SEND (GPIO VIA PD3)

A42 AC_SDOUT AC97 SERIAL DATA TO CODEC

B42 AC_SDIN AC97 SERIAL DATA FROM CODEC

A43 AC_BCLK AC97 BIT CLOCK FROM CODEC

B43 AC_SYNC AC97 SYNC FROM CODEC

A44 GND

B44 GND

A45 *AC_RST AC97 RESET TO CODEC


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B45 SSI_RXD SSI RECEIVE – Rev. P2 and P3 have SSI_RXD on A46, this is planned to be fixed in the next rev.

A46 SSI_RDY N SSI READY (SSI_RXD is located on this pin for rev. P2 and P3)

B46 SSI_MCLK SSI MASTER CLOCK

A47 SSI_FRM SSI FRAME

B47 SSI_TXD SSI TRANSMIT

A48 SS1_CLK SSI MASTER CLOCK

B48 *CF_CE1 COMPACT FLASH CHIP ENABLE 1

A49 *CF_CE2 COMPACT FLASH CHIP ENABLE 2

B49 *CF_REG COMPACT FLASH I/O REGISTER SPACE

A50 *CF_OE COMPACT FLASH MEMORY OUTPUT ENABLE

B50 *CF_WE COMPACT FLASH MEMORY WRITE ENABLE

A51 *CF_IOR COMPACT FLASH I/O READ STROBE

B51 *CF_IOW COMPACT FLASH I/O WRITE STROBE

A52 *CF_WAIT COMPACT FLASH WAIT

B52 CF_RDY COMPACT FLASH READY/BUSY/INTERRUPT

A53 CF_RST COMPACT FLASH RESET

B53 *CF_CD COMPACT FLASH CARD DETECT

A54 *EXP_CS EXPANSION CHIP SELECT

B54 GND

A55 EXP_CLK EXPANSION BUS CLOCK

B55 GND

A56 *EXP_WAIT EXPANSION WAIT

B56 *EXP_IRQ EXPANSION INTERRUPT

A57 *EXP_WE EXPANSION WRITE ENABLE

B57 *EXP_OE EXPANSION READ ENABLE

A58 *EXP_BE0 EXPANSION BYTE ENABLE 0


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B58 *EXP_BE1 EXPANSION BYTE ENABLE 1

A59 LD0 COMPACT FLASH/EXPANSION DATA BIT0

B59 LD1 COMPACT FLASH/EXPANSION DATA BIT1















A67 GND

B67 GND

A68 LA0 COMPACT FLASH/EXPANSION ADDRESS BIT 0

B68 LA1 COMPACT FLASH/EXPANSION ADDRESS BIT 1









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B73 LA11 EXPANSION ADDRESS BIT 11

A74 LA12 EXPANSION ADDRESS BIT 12












A80 GND

B80 GND


B81 LCD_B0 N LCD BLUE BIT 0 – TIED TO GROUND

A82 LCD_B1 LCD BLUE BIT 1

B82 LCD_B2 LCD BLUE BIT 2


B83 LCD_B4 LCD BLUE BIT 4


B84 LCD_G0 LCD GREEN BIT 0

A85 LCD_G1 LCD GREEN BIT 1




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B87 LCD_R0 N LCD RED BIT 0 – TIED TO GROUND

A88 LCD_R1 LCD RED BIT 1

B88 LCD_R2 LCD RED BIT 2


B89 LCD_R4 LCD RED BIT 4


B90 LCD_HSYNC LCD HORIZONTAL SYNC

A91 LCD_VSYNC LCD VERTICAL SYNC

B91 LCD_OE LCD OUTPUT ENABLE

A92 LCD_PCLK LCD PIXEL CLOCK

B92 LCD_BKL LCD BACKLIGHT ENABLE

A93 GND

B93 GND

A94 VIP_MCLK MASTER CLOCK OUT TO VIP DEVICE

B94 VIP_PCLK VIDEO INPUT PORT PIXEL CLOCK

A95 VIP_HSYNC VIDEO INPUT PORT HORIZONTAL SYNC

B95 VIP_VSYNC VIDEO INPUT PORT VERTICAL SYNC

A96 VIP_D0 VIDEO INPUT PORT BIT 0

B96 VIP_D1 VIDEO INPUT PORT BIT 1







A100 VIP_D8 VIDEO INPUT PORT BIT 8 (10BIT MODE ONLY)


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B100 VIP_D9 VIDEO INPUT PORT BIT 9 (10BIT MODE ONLY)

Table 24 – CSB737 SODIMM Expansion Connector Pinout


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10 COMPONENT LOCATIONS 10.1 OVERVIEW

The following figure shows the component locations for the CSB737 Top and Bottom sides. These are shown for reference purposes only.

Figure 2 – CSB737 Component Locations


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11 DOCUMENT REVISIONS

Date Revision Change

12/1/2007 P1.0 First Release

1/29/2008 P1.1 Corrected DS1339 I2C address

1/04/2008 P2.0 Added errata for 32.6768Khz Oscillator

5/28/2008 P2.1 Corrected Table 4 regarding DS1339 connection

01/06/09 P2.2 Documented SSI_RXD being on the wrong pin for Rev. P1 and P2

01/06/09 P2.2 Correct LCD Bit Assignment Table

03/17/09 P3.0 Corrected SSI_RXD entry to add that the error is still present on revision P3.

Table 25 – Document Revisions

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