Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States...
Transcript of Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States...
![Page 1: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/1.jpg)
1
Coding for Flash
Memories
Eitan Yaakobi, Jing Ma, Adrian Caulfield, Laura Grupp
Steven Swanson, Paul H. Siegel, Jack K. Wolf
Non-Volatile Memories Workshop, April 2010
Center for Magnetic Recording Research
University of California San Diego
![Page 2: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/2.jpg)
2
Outline
• Error Characterization of Flash Memories
• Implementing WOM-codes in SLC Flash
• WOM-codes with Better Rates
![Page 3: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/3.jpg)
3
Experiment Description
• We checked several flash memory blocks - SLC and MLC
• For each block the following steps are repeated• The block is erased
• A pseudo-random data is written to the block
• The data is read and compared to find errors
• Two runs are chosen as representatives for SLC and MLC• SLC - Collected Iterations: 3,615,224
• MLC - Collected Iterations: 1,054,031
• Remarks:• We measured many more iterations than the manufacturer‟s
guaranteed number of erasures
• The experiment was done in a lab conditions and related factors such
as temperature change, intervals between erasure or multiple
readings before erasures were not considered
![Page 4: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/4.jpg)
4
Raw BER for SLC block
The BER for each
iteration is measured
We average for every 200
consecutive iterations
106
10-4
Guaranteed lifetime
by the manufacturer
![Page 5: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/5.jpg)
5
Raw BER for MLC block
The BER for each
iteration is measured
We average for every 50
consecutive iterations
105
10-3
Guaranteed lifetime
by the manufacturer
![Page 6: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/6.jpg)
6
Basic Error Characteristic
• Directional Errors - Number of Plus errors Vs. Minus errors
• Plus error: Cell in state „0‟ changes to state „1‟
• Minus error: Cell in state „1‟ changes to state „0‟
• We check the distribution of the errors between plus and minus errors and the numbers are the same even for individual bits
• Conclusion: There is no preference to correct more plus than minus errors (or vice versa)
• Burst behavior
• Check how close the errors are to each other
• Explore the potential (dis)advantage of using a RS code VS a BCH code
• Conclusion: The errors are random and do not have burst pattern behavior
![Page 7: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/7.jpg)
7
BER Page Dependency
• We checked the BER for each page independently
• SLC block cells layout:
32x215 cells; each page has 214 cells
page 1 page 2
page 3 page 4
page 5 page 6
.
.
.
.
.
.
page 63 page 64
![Page 8: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/8.jpg)
8
BER per page for SLC block
The odd pages
have higher BER
106
10-3
Red plots – odd pages
Blue plots – even pages
![Page 9: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/9.jpg)
9
BER Page Dependency for MLC
• The Most Significant Bit (MSB) and Least Significant Bit
(LSB) represented by one cell belong to two different pages
• Pages storing the LSB are less protected from errors
1
0
High Voltage
Low Voltage
1,0
0,1
High Voltage
Low Voltage
1,1
0,01 Bit Per Cell2 States
2 Bits Per Cell4 States
TrappedCharge
TrappedCharge
Multi Level Cell (MLC)Single Level Cell (SLC)
![Page 10: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/10.jpg)
10
A possible MLC block cell layout:
Row
index
LSB of first
214 cells
MSB of first
214 cells
LSB of last
214 cells
MSB of last
214 cells
1 page 1 page 5 page 2 page 6
2 page 3 page 9 page 4 page 10
3 page 7 page 13 page 8 page 14
4 page 11 page 17 page 12 page 18
5 page 15 page 21 page 16 page 22
31 page 119 page 125 page 120 page 126
32 page 123 page 127 page 124 page 128
BER Page Dependency for MLC
![Page 11: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/11.jpg)
11
BER per page for MLC block
105
10-3
Pages, colored the
same, behave similarly
![Page 12: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/12.jpg)
12
Bit Error Map in SLC
• We checked how the errors behave for every bit
• For a small window of iterations, 1.5-1.6 106
iterations - the BER is roughly fixed, we checked
for each bit the number of times it was in error
![Page 13: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/13.jpg)
13
Bit Error Map for Odd Pages in SLC
Calculate the number of times
each bit is in error
Errors are clustered in
columns rather than rows
104
104
![Page 14: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/14.jpg)
14
Bit Error Map for Odd Pages in MLC
There are less errors since
the BER of the right part is
less than the BER of the left
part
We saw also data
dependency more in the
columns than the rows
104
![Page 15: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/15.jpg)
15
More Work
• We compared between BCH codes, RS
codes, and burst correcting codes
• We evaluated another ECC scheme that
works in two levels:
• First level: ECC for each page
• Second level: ECC for the entire block
![Page 16: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/16.jpg)
16
Write Once Memories (WOM)
• Introduced by Rivest and Shamir, “How to reuse a write-once memory”, 1982
• The memory elements represent bits (2 levels) and can be irreversibly programmed from the ‘0’ state to the ‘1’ state
• The problem:
What is the required minimum number of cells, w, to write kbits t times?• In order to store k bits twice (t = 2) at least ~1.29k cells are required
• A simple construction achieves 1.5k cells
• Alternatively, it is possible to ask: what is the maximum total number of bits that can be written using n cells and twrites?
![Page 17: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/17.jpg)
17
Write Once Memory (WOM)
Codes for SLC• A scheme for storing two bits twice using only
three cells before erasing the cells
• The cells only increase their level
• How to implement? (in SLC block)• Each page stores 2KB/1.5 = 4/3KB per write
• A page can be written twice before erasing
• Pages are encoded using the WOM code
• When the block has to be rewritten, mark its pages as invalid
• Again write pages using the WOM code without erasing
• Read before write at the second write
data 1st write 2nd write
00 000 111
01 100 011
10 010 101
11 001 110
Cells state
1st
write
2nd
write
data
cells
1st
write
2nd
write
data 01 11
cells 100 110
1st
write
2nd
write
data 01
cells 100
00.11.01.10.11 … 10
WOM
ENCODER
000.001.100.010.001 … 010
000.001.100.010.001 … 01001.10.00.10.11 … 11
100.010.000.010.001 … 001
100.010.000.010.001 … 001
100.100.000.001.010 … 000
000.010.001.100.000 … 010001.010.100.000.100 … 010
01.11.10.00.01 … 00
011.001.101.111.011 … 111
011.001.101.111.011 … 11100.11.00.01.11 … 10
111.110.000.011.001 … 101
111.110.000.011.001 … 101
101.100.101.101.110 … 000
000.110.111.111.110 … 010
111.110.100.101.101 … 110
Advantages:
• The number of bits written per cell is 4/3
• Possible to write twice before a physical
erasure
![Page 18: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/18.jpg)
18
BER for the First and Second Writes
![Page 19: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/19.jpg)
19
WOM-Codes with two writes
• Joint work with Scott Kayser
• Assume there are n cells and two writes, t =2
• First write: k1 bits, R1 = k1/n, second write: k2 bits, R2 = k2/n
• Capacity region (Heegard 1986, Fu and Han Vinck 1999)
C = { (R1, R2) | p [0, 0.5], R1 h(p), R2 1 - p }
The WOM-rate R = R1+ R2 log2(3) 1.58, achieved for p = 1/3
• Rivest and Shamir constructed WOM-codes of rates (2/3, 2/3) and (0.67, 0.67), R =1.34
• Recently, Wu found a WOM-code of rate (0.746, 0.625), R =1.371
![Page 20: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/20.jpg)
20
WOM-Codes with two writes
• Capacity region (Heegard 1986, Fu and Han Vinck 1999)
C = { (R1, R2) | p [0, 0.5], R1 h(p), R2 1 - p }
The WOM-rate R = R1+ R2 log2(3) 1.58, achieved for p = 1/3
• Rivest and Shamir constructed WOM-codes of rates (2/3, 2/3) and (0.67, 0.67)
• Recently, Wu found a WOM-code of rate (0.746, 0.625), R =1.371
• We construct WOM-codes from any linear code:• Given a linear code C[n, k], if on the first write the vector of
programmed cells does not cover a codeword from the code, then it is possible to write k bits on the second write
• VC = { v {0,1}n | v does not cover a codeword from C }
• R1 = log|VC|/n, R2 = k/n, R = (log|VC| + k)/n
• The [16,11,4] extended Hamming code (0.769, 0.6875), R = 1.4566
• The [23,12,7] Golay code: (0.9458, 0.5217) R = 1.4632
• We also show that by choosing randomly the generator matrix of the linear code C we can achieve the capacity
![Page 21: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/21.jpg)
21
![Page 22: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/22.jpg)
22
Future Work
• Implementing WOM-codes in MLC Flash
• ECC for WOM-codes
![Page 23: Coding for Flash Memoriesnvmw.eng.ucsd.edu/2010/documents/Yaakobi_Eitan.pdf2 Bits Per Cell 4 States Trapped Charge Trapped Charge Single Level Cell (SLC) Multi Level Cell (MLC) 10](https://reader036.fdocuments.us/reader036/viewer/2022063021/5fe43bf87d3fbf2978723417/html5/thumbnails/23.jpg)
23
Summary
• Error characterization in flash memories
• Write Once Memory (WOM) codes
• Implementation of a simple WOM-codes scheme
in SLC flash
• WOM-codes with better rates are found