Code Generation

Code Generation

3 April 2015 1 Dr. Azhar, Dept. of CSE, KUET

2

Phases of Compiler Input Source Program

Lexical Analyzer

Syntax Analyzer

Symbol Table Manager

Semantic Analyzer Error Handler

Intermediate Code Generator

Code Optimizer

Code Generator

Target Program

Code Generation

Input : Intermediate language program

such as sequence of quadruples or triples

and so on

Output: Object program such as machine

language form, assembly language

program or some other.


Problems of Code Generation

Deciding what machine instructions to generate

If the target machine has the instruction add one to-storage(AOS) then the statement A:=A+1 should generate

AOS A

Rather than

LOAD A

ADD #1

STORE A


Problems of Code Generation

Deciding in what order the computation should

be done

Some computation require fewer registers

Picking the best order is a very difficult problem

We generate in the order produced by the semantic

routine

Deciding which registers to use for computation.


Machine Model

Code generation requires intimate knowledge of target machine

Assume 16 bit machine with byte addressable 216 bytes.

215 16 bit words.

Eight general purpose registers, R0, R1,, R7 capable of holding 16 bit quantity.

Binary operator of the form OP source, destination


Machine Model

Addressing mode r (register mode): register contains the operand

*r (indirect register): r contains the address of the operand

X(r) (indexed mode): Value X is added to the contents of r to produce the address of the operand.

*X(r) (indirect indexed mode) : Value X is added to the contents of r to produce the address of the word containing the address of the operand.

#X (immediate): The word following the instruction contains the literal operand X.


Machine Model

Op-Codes

MOV (move source to destination)

ADD (add source to destination)

SUB (substract source from destination)


Machine Model

MOV R0,R1 instruction has cost 1

MOV R5,M instruction has cost 2, since the

address of memory location M is in the word

following the instruction

ADD #1, R3, has cost 2 since the constant 1

must appear in the next word

SUB 4(R0), *5(R1) has cost 3, since two

constant 4 and 5


Machine Model For the quadruple of the form a:=b+c

MOV B, R0

ADD C, R0

MOV R0, A

MOV B, A

ADD C, A

MOV *R1, *R0

ADD *R2, *R0

Assuming R0, R1 and R2 contains address of a, b, and c

ADD R2, R1

MOV R1, A

Assuming R1 and R2 contains address of b, and c

Cost=6

Cost=6

Cost=2

Cost=3


Code Generation Algorithm

Next use: Live after the block

Register Descriptor: Keeps track of the register

allocation

Address descriptor: Keeps track of the location of the

current value.


Code Generation Algorithm

Each quadruple of the form A:=B op C Determine the reg where the operation to be

performed

Consult the address descriptor to get the location. If

B is not in reg generate MOV to copy in reg.

Generate the instruction OP C, L, C is the location,

update address descriptor, if L is reg. update register

descriptor

If B or C has no next use alter the register

descriptor.


A Simple Code Generator T: = A-B

U: = A-C

V: = T+U

W: = V+U

Statement Code

generated

Register

descriptor

Address

descriptor

T: = A-B MOV A,R0

SUB B,R0

R0 contains T T in R0

U: = A-C MOV A,R1

SUB C, R1

R0 contains T

R1 contains U

T in R0

U in R1

V: = T+U Add R1, R0 R0 contains V

R1 contains U

U in R1

V in R0

W: = V+U ADD R1, R0

MOV R0, W

R0 contains

W

W in R0

Cost of the generated code is 12

13

A Simple Code Generator

Conditional Statement

two ways

Jump if the value of the registers meet the

conditions, negative, zero, positive, non

negative, nonzero and nonpositive

Ex. If A

A Simple Code Generator

Conditional Statement

Condition Code, a hardware indication

Loaded to r a value zero, negative or positive

Ex. CMP A, B sets the condition code to

positive if A>B and so on.

IF A

Register Allocation

Efficient utilization of registers is important in generating codes

One approach: Assign specific types to certain registers. Ex. Base register to one group, arithmatic

computation to another and so on

It is simple to design

But application is too strict and inefficient for registers use

certain registers may be unused others are unnecessary loaded


Global Register Allocation

Registers to hold values of a single basic block

But forced to store values at the end of BB

Assign registers to frequently used variables and

keep theses registers consistent (global)

Try to use registers in loops

We assume fixed no. registers for global

We can save 1 unit cost for reference to variable

x if x is in register


Usage count Counts the saving for register allocation

USE(x,B) is the number of times x is used

in B prior to any definition of x

LIVE(x,B) is 1 if x is live on exit from B and

is assigned a value in B otherwise 0

LinBblocks

BxLIVEBxUSE )},(*2),({


Usage count

a:= b+c

d:= d-b

e:=a+f

f:=a-d b:= d+f

e:= a-e

b:= d+e

For x=a

a is live on exit from

B1and assigned a value

there but is not live on exit

from B2, B3 and B4

For x=a

LIVE(a,B1)=2

USE(a,B1)=0, since a is

defined in B1 before any use.

USE(a,B2)=1, USE(a,B3)=1, USE(a,B4)=0,

Usage value for x=a is 4

Thus 4 unit of costs can be saved by selecting a for one of the global registers

bcdf

acde acdf

cdef

bcdef

B1

B2 B3

B4

19

Usage count

B1 B2 B3 B4 B1 B2 B3 B4 Total

a 1 0 0 0 0 1 1 0 4

b 0 0 1 1 1 0 0 0 5

c 0 0 0 0 1 0 1 1 3

d 1 0 0 0 1 1 1 1 6

e 1 0 1 0 0 0 0 0 4

f 0 1 0 0 1 0 1 0 4

Live Use


Usage count

MOV R1, R0

ADD C, R0

SUB R1, R2

MOV R0, R3

ADD F, R3 MOV R3,E

MOV R0,R3

SUB R2, R3

MOV R3, F

MOV R2, R1

ADD F, R1

MOV R0,R3

SUB C, R3

MOV R3, E

MOV R2, R1

ADD C, R1

MOV B, R1

MOV D, R2

MOV B, R1

MOV D, R2 MOV B, R1

MOV D, R2

B2

B1

B3

B4

3 April 2015 21

Rearranging

T1:=A+B

T2:=C+D

T3=E-T2

T4:=T1-T3

MOV A, R0

ADD B, R0

MOV C, R1

ADD D, R1

MOV R0, T1 MOV E, R0

SUB R1, R0

MOV T1, R1

SUB R0, R1

MOV R1, T4


Construct the DAG

Rearranging

Rearrange

T2:=C+D

T3=E-T2

T1:=A+B T4:=T1-T3

MOV C, R0

ADD D, R0

MOV E, R1

SUB R0, R1

MOV A, R0 ADD B, R0

SUB R1, R0

MOV R0, T4

COST SVINGS ???


THANK YOU


Code Generation

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