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April 11, 2023 C.Ravindra Murthy 1

Register Transfer and Micro-operations

C.Ravindra Murthy


Micro-operation An elementary operation performed during one clock

pulse, on the information stored in one or more registers R f(R, R)

f: shift, count, clear, load, add, …

Registers (R) ALU (f)1 Clock

Cycle


Register Transfer Language Definition of organization of a computer

Set of registers and their functions Micro-operation set

Set of allowable micro-operations provided by the organization of the computer

Control signals that initiate the sequence of micro-operations

For any function of the computer, a sequence of micro-operations is used to describe it


Register Transfer Language A symbolic language A convenient tool for describing the

internal organization of digital computers

Can also be used to facilitate the design process of digital systems


Register Transfer Designation of a register

A register Portion of a register A bit of a register

Common ways of drawing the block diagram of a register

R1

R2

Register Showing individual bits

15 0 15 078

7 6 5 4 3 2 1 0

PC (H) PC (L)

Numbering of bits Sub fields


Register Transfer Representation of a transfer (Parallel)

R2 R1 A simultaneous transfer of all bits from the source

to the destination register, during one clock pulse Representation of a controlled (conditional)

transfer P: R2 R1 A binary condition(p=1) which determines when

the transfer is to occurif (P=1) then (R2 R1)


Hardware Implementation of Controlled Transfer Implementation of controlled transfer P: R2 R1

Control circuit

R2

R1

LoadP Clock

n

Block Diagram

Clock

LoadTransfer occurs here

Timing Diagram


Basic Symbols for Register TransferSymbols & numerals

Description Meaning

Parentheses ()

Arrow

Colon :

Comma ,

Capital Letters

Denotes a part of a register

Denotes transfer of information

Denotes termination of control function

Separates two micro-operations

Denotes a register

R2(0-7), R2(L)

R2 R1

P:

A B, B A

MAR, R2


Bus and Memory Transfer Bus is a path (of a group of wires) over which information is transferred, from

any of several sources to any of several destinations. From register to a bus: BUS R

Register A Register B Register C Register D

Bus Lines


Bus and Memory Transfer

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

Register A Register B Register C Register D

4 x 1MUX

4 x 1MUX

4 x 1MUX

4 x 1MUX

0 0 0 0

X

Y

Select

B1 C1 D1 B2 C2 D2 B3 C3 D3 B4 C4 D4

4 Line Bus


Transfer from Bus to a Destination Register

Reg. R0 Reg. R1 Reg. R2 Reg. R3

D0 D1 D2 D32 x 4

Decoder

z

wSelect E Enable

Bus Lines

Load

Normal Input ANormal Input C

Output Y = A if C =1

High Impedance if C = 0

Three State Bus Buffers


Bus Lines with Three State Buffers

0123

S0

S1

Enable

Select

A0

B0

C0

D0

Bus Line for Bit 0


Memory Transfers

Memory unit

DR

ARReadWrite

Memory read micro-op: DR M ( DR M[AR] )

Memory write micro-op: M DR ( M[AR] DR )


Summary of Register Transfer Micro-operationsA B Transfer content of register B into register A

AR DR(AD) Transfer content of AD portion of reg. DR into reg. AR

A constant

Transfer binary content to reg. A

ABUS R1, R2 ABUS

Transfer content of R1 into bus A and, at the same time, transfer content of bus A into reg. R2

AR Address Register

DR Data Register

M[R] Memory word specified by reg. R

M Equivalent to M[R]

DR M Memory read operation: transfers the content of memory word specified by AR into DR

M DR Memory write operation: transfers the content of DR into memory word specified by AR


Arithmetic Micro-operations

R3 R1 + R2 Contents of R1 + R2 transferred to R3

R3 R1 – R2 Contents of R1 – R2 transferred to R3

R2 R2’ Complement the content of R2

R2 R2’ + 1 2’s complement the content of R2 (negate)

R3 R1 + R2’ +1 Subtraction

R1 R1 + 1 Increment

R1 R1 – 1 Decrement


Types Micro-operations Four types of Micro-operations

Register Transfer Micro-operations Arithmetic Micro-operations Logic Micro-operations Shift Micro-operations


Binary Adder

FA

B3 A3

S3

FA

B2 A2

S2

FA

B1 A1

S1

FA

B0 A0

S0

C0C1C2C3C4

Binary Adder

FA

A3

S3

FA

A2

S2

FA

A1

S1

FA

B0

A0

S0

C0C1C2C3C4

B1B2B3M

Adder-Subtractor


Binary Increment

HA

x y

C S

1A0

S0

HA

x y

C S

A1

S1

HA

x y

C S

A2

S2

HA

x y

C S

A3

S3C3


Arithmetic Circuit

4 x 1MUX

S0S10123

4 x 1MUX

S0S10123

4 x 1MUX

S0S10123

4 x 1MUX

S0S10123

FAX0

Y0

C0

FAX1

Y1

C1

FAX2

Y2

C2

FAX3

Y3

C3

D0

D1

D2

D3

Cout

CinS0S1

A0

A1

A2

A3

B3

B3

B3

B3

0

S1

S0 Cin

Y Micro-operation

0 0 0 B Add

0 0 1 B Add with Carry

0 1 0 B’ Subtract with borrow

0 1 1 B’ Subtract

1 0 0 0 Transfer A

1 0 1 0 Increment A

1 1 0 1 Decrement A

1 1 1 1 Transfer A

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