CMSC 313 Lecture 18

CMSC 313 Lecture 18

• Midterm Exam returned

• Assign Homework 3• Circuits for Addition

• Digital Logic Components

• Programmable Logic Arrays

UMBC, CMSC313, Richard Chang <[email protected]>

CMSC 313, Computer Organization & Assembly Language Programming, section 0101Fall 2004 Homework 3

Due: November 11, 2004

1. (30 points) Draw schematics for the following functions using AND, OR and NOT gates. (Do notsimplify the formulas.)

(a) XY + XY Z + XY Z

(b) (XY + WZ)(WX + Y Z)

(c) (X + Y ) (X + Y )

2. (30 points) Using the postulates and theorems of Boolean algebra in Table A-1 (p. 451), simplify thefollowing formulas. Show all of your work.

(a) WXY Z(WXY Z + WXY Z + WXY Z + WXY Z)

(b) AB + ABCD + ABDE + ABCE + CDE

(c) MNO + QPN + PRM + QOMP + MR

3. (40 points) For each CMOS circuit below,

(a) Provide a truth table for the circuit’s function.

(b) For diagram (a), write down the Sum-of-Products (SOP) Boolean formula for the truth table. Fordiagram (b), wrtie down the Product-of-Sums (POS) Boolean formula.

(c) Simplify the SOP or POS formula using the postulates and theorems of Boolean Algebra (p. 451).Show all work.

(d) Draw the logic diagram of the simplified formula using AND, OR, NAND, NOR and NOT gates.

A

B

C

+5v

GND

z

D

A

B

C

+5v

GND

z

D

(a) (b)

Last Time

• Postulates & Theorems of Boolean Algebra

• Periodic Table & Semiconductors• P-N junction

• Field-Effect Transistors

• CMOS Logic Gates

UMBC, CMSC313, Richard Chang <[email protected]>

Half Adder

• Inputs: A and B

• Outputs: S = lower bit of A + B, cout = carry bit

A B S cout

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

• Using Sum-of-Products: S = AB + AB, cout = AB.

• Alternatively, we could use XOR: S = A ⊕ B.

� � � � 1

Full Adder

• Inputs: A, B and cin

• Outputs: S = lower bit of A + B, cout = carry bit

A B cin S cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

• S = ABC + ABC + AB C + ABC = A ⊕ B ⊕ C.

• cout = MAJ3 = AB + BC + AC.

� � � � 2

Chapter 3: Arithmetic3-6

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring

Ripple Carry Adder• Two binary numbers A and B are added from right to left, creating

a sum and a carry at the outputs of each full adder for each bit po-sition.

Fulladder

b0 a0

s0

Fulladder

b1 a1

s1

Fulladder

b2 a2

s2

Fulladder

b3 a3

c4

s3

0c0c1c2c3



Constructing Larger Adders• A 16-bit adder can be made up of a cascade of four 4-bit ripple-

carry adders.

s0

b1

a1

s1

b2

a2

s2

b3

a3

c4

s3

04-Bit Adder #0

b0

a0

s12

b13

a13

s13

b14

a14

s14

b15

a15

c16

s15

4-Bit Adder #3

b12

a12

. . .c12 c0



Full Subtractor• Truth table and schematic symbol for a ripple-borrow subtractor:

00110011

01010101

bi bori

00001111

ai

01101001

diffi

01110001

bori+1

Fullsub-

tractor

bi ai

bori

bori+1

diffi(ai – bi)



Ripple-Borrow Subtractor• A ripple-borrow subtractor can be composed of a cascade of full

subtractors.

• Two binary numbers A and B are subtracted from right to left, cre-ating a difference and a borrow at the outputs of each fullsubtractor for each bit position.

b0 a0

diff0

b1 a1

diff1

b2 a2

diff2

Fullsub-

tractor

b3 a3

bor4

diff3

0

Fullsub-

tractor

Fullsub-

tractor

Fullsub-

tractor

bor0



Combined Adder/Subtractor

Fulladder

b0

a0

s0

Fulladder

b1

a1

s1

Fulladder

b2

a2

s2

Fulladder

b3

a3

c4

s3

c0

ADD /SUBTRACT

• A single ripple-carry adder can perform both addition and subtrac-tion, by forming the two’s complement negative for B when sub-tracting. (Note that +1 is added at c0 for two’s complement.)



Carry-Lookahead Addition

Gi = aibi and Pi = ai + bi

c0 = 0

c1 = G0

c2 = G1 + P1G0

c3 = G2 + P2G1 + P2P1G0

c4 = G3 + P3G2 + P3P2G1 + P3P2P1G0

• Carries are represented in termsof Gi (generate) and Pi (propagate)expressions.



Carry Lookahead Adder

Fulladder

s0

Fulladder

s1

Fulladder

s2

Fulladder

s3

0c0

b3 a3b3 a3 b2 a2 b1 a1 b0 a0

G0P1G1P2G2

c1c2c3

P3G3

c4

• Maximum gate delayfor the carry genera-tion is only 3. Thefull adders introducetwo more gate de-lays. Worst casepath is 5 gate de-lays.

Appendix A: Digital LogicA-26


Digital Components• High level digital circuit designs are normally created using col-

lections of logic gates referred to as components , rather than us-ing individual logic gates.

• Levels of integration (numbers of gates) in an integrated circuit(IC) can roughly be considered as:

• Small scale integration (SSI): 10-100 gates.• Medium scale integration (MSI): 100 to 1000 gates.• Large scale integration (LSI): 1000-10,000 logic gates.• Very large scale integration (VLSI): 10,000-upward logic

gates.• These levels are approximate, but the distinctions are useful

in comparing the relative complexity of circuits.



Multiplexer

0011

0101

A B

D0

D1

D2

D3

FD0

A

D1

D2

D3

B

F

0001

1011

F = A B D0

+ A B D1

+ A B D2

+ A B D3

Dat

a In

puts

Control Inputs



AND-OR Implementation of MUX

F

A B

D0

D1

D2

D3



MUX Implementation of Majority• Principle: Use the 3 MUX control inputs to select (one at a time)

the 8 data inputs.

A C

F

000001

010011

B

100101

110111

00

01

01

11

00110011

01010101

B C

00001111

A

00010111

M



4-to-1 MUX Implements 3-Var Function• Principle: Use the A and B inputs to select a pair of minterms.

The value applied to the MUX data input is selected from {0, 1,C, C} to achieve the desired behavior of the minterm pair.

A B

F

00

0110

11

0

1C

C

00110011

01010101

B C

00110110

F

00001111

A

0

1

C

C

CMSC 313 Lecture 18

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