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![Page 1: CMS Pixel Issues ACES 07 Common ATLAS – CMS Electronics Workshop CERN 20. March 2007 R. Horisberger Paul Scherrer Institut.](https://reader036.fdocuments.us/reader036/viewer/2022062407/56649cf95503460f949ca275/html5/thumbnails/1.jpg)
CMS Pixel Issues
ACES 07
Common ATLAS – CMS Electronics Workshop
CERN 20. March 2007
R. Horisberger
Paul Scherrer Institut
![Page 2: CMS Pixel Issues ACES 07 Common ATLAS – CMS Electronics Workshop CERN 20. March 2007 R. Horisberger Paul Scherrer Institut.](https://reader036.fdocuments.us/reader036/viewer/2022062407/56649cf95503460f949ca275/html5/thumbnails/2.jpg)
• SLHC Tracker / Detector upgrade in 2014/16 requires action already now !
• 7-9 years not terribly much for : - Conception of SLHC tracker - Basic R&D - Prototyping - Demonstators - Production - Installation & Commissioning
• Should learn from current experience of LHC trackers ! Cabling/Cost/Cooling
• Present tracker is probably quite good , but too much material budget !
Next tracker should do a factor 2 better !
• SLHC creates extra problems with: - data rates 10x - event complexity 20x
- event selection triggering with tracks
- radiation damage
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• Present pixel detector conceived in 1996 / 97 with:
• focus on easy insertion/removal of pixel system • keep material budget low achieved 1.93% X0/Layer (=0)
• use analog optolinks of strip APV readout adaptation in geometry
• keep optolinks at maximum radius limit rad. damage • Operate at L =1034 at radii 7cm & 11cm data rates, buffer size
• rad. hard DMILL technology 0.8m 2 ½ metal layers5.5V supplyBiCMOS
(was useful)
present pixel ROC architecture with :
1) Zero channel suppression (pixel hit discrimination)
2) Analog pulse height readout (~ 7-8 bit)
Readout : pixel address (5 clocks) + analog pulse height (1 clock)
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Pixel readout analog coded pixel address
Overlap of 4160 pixel readouts
5 clock cycles:encode 13 bits of pixel address information.
1 pixel hit
1 clock cycle: analog pulse height
col# pix#
chipheader
Present system: had to use analog optical link available !Future SLHC system: digital bit stream through high speed link ! (add 1 ADC/ROC)
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Time-stamp buffer Depth: 12data buffer
Depth: 32
marker bits indicate start of new event
set
fast double column OR
hit
data
column drain mechanism
pixel unit cells: 2x80
sketch of a double column
doublecolumn
doublepixels
32 databuffers
12 time stampbuffers
double columninterface
7.8mm
9.8mm
Column Drain Architecture
Transfer data rapidly to periphery and store for L1 latency ( ~3.4usec)
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• DMILL pixel ROC worked ! Yield: 0 pixel defect <1% 1-5 pixel defect 22%
• Translation DMILL ROC to 0.25um ROC with big financial & electrical benefits
DMILL 0.25 IBM Ratio
Wafer size 6” 8” ~2x (area)Wafer cost [CHF] 12K 2.5K ~4xYield 22% (<5px def.) 70% (0 def.) ~3x
Total : ~ 24 x Cost benefits
Engineering run ~200K ~160k
• Will the change from 0.25m to 0.13m give a similar benefit?
No ! 0.13um production wafers of same size (8”) are 60% more expensive
Engineering run ~ 3 times more expensive.
![Page 7: CMS Pixel Issues ACES 07 Common ATLAS – CMS Electronics Workshop CERN 20. March 2007 R. Horisberger Paul Scherrer Institut.](https://reader036.fdocuments.us/reader036/viewer/2022062407/56649cf95503460f949ca275/html5/thumbnails/7.jpg)
0.25 Pixel ROC
9800
m
7900m
• Chip modified to DMILL version - should have uniform address levels - external Operation is same
• Chip Internal Power Regulators
• Column Drain Architecture
• more timestamp & data buffers 8 12 24 32
now fit for r=4cm at L=1034
• less power 28W/pixel
• smaller pixel area: 100 x 150
Total # transistors : 1280 K
(DMILL 430K )
IBM_PSI46
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Data losses of pixel ROC
Data losses @ r=4cm & L=1034
DMILL ROCDM_PSI43
150x 150 pixel
0.25m ROCIBM_PSI46
100x 150 pixel
Timestamp( # buffers)
3.1%(8)
0.17%(12)
Data Buffers(# buffers)
0.1%(24)
0.15%(32)
Column Drain
load cycle
3% 0%
Column Drain
3rd hit capability
1.4% 0.25%
Pixel overwrite 0.3% 0.21%
• Original ROC design (TDR) was done for high lumi operation of 7cm layer!
• Use 0.25 ROC translation to optimize for new pixel size and 4cm radius !!
SLHC Luminosity
Data loss due to limited timestamp buffers & data buffers increase very quickly
e.g. 10 x LHC would need 60 timestamp buffers
Periphery size would increase factor 5x
650 ~ 3250
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SLHC situation
• Track rates at L = 10 35 cm-2 sec-1
•Technology already exists for SLHC tracking at radii > 20cm :
Silicon Pixels Detector
• Performance of present pixels at SLHC?
SLHC Track Rate .vs. Radius
y = 4560 x-1.5
1
10
100
1000
0 10 20 30 40 50 60 70 80 90 100 110 120
Radius [cm]
Tra
ck
Ra
te [
MH
z/c
m^
2]
LHC Rates @10 34
r = 4cm
r = 7cm
r = 11cm
SLHC Rates @10 34
r = 18cm
r = 30cm
r = 50cm
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Data Buffer full:0.07% / 0.08% / 0.17%
Timestamp Buffer full: 0 / 0.001% / 0.17%
Readout and double column reset: 0.7% / 1% / 3.0% for 100kHz L1 trigger rate
Pixel busy:0.04% / 0.08% / 0.21%pixel insensitive until hittransferred to data buffer (column drain mechanism)
Double column busy:0.004% / 0.02% / 0.25%Column drain transfers hits from pixel to data buffer. Maximum 3 pending column drains requests accepted
Double column readout
Pixel-column interface
• 1xLHC: 1034cm-2s-1
11 cm / 7 cm / 4 cm layertotal data loss @ 100kHz L1A:
0.8%1.2%3.8%
Data loss mechanisms 0.25 ROC PSI46
SLHC rate data losses dominated by finite buffer sizes ! chip size ! periphery bigger
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0.0001
0.0010
0.0100
0.1000
1.0000
0 10 20 30 40 50 60
# Timestamps/ Doublecolumn
Inef
ficie
ncy
1xLHC
2.5xLHC
5xLHC
10xLHC
• Present system: 12 time stamp buffers, 32 data buffers. Average pixel multiplicity:2.2
• Possible extension: doubling the buffer size (24/64). Enough for < 2.5x1034cm-2s-1
• For 10x1034 need 60 timestamp buffers and 190 data buffers (average pixel multiplicity: 2.6).
Influence of buffer size at r= 4cm layer
# timestamps / doublecolumn
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0.1
1
10
100
1 2 3 4 5 6 7 8 9 10
Luminosity [ 10^34 ]
Dat
a Lo
ss
[ % ]
DC busy
Readout + DC reset
Pixel busy
Column busy (new)
r/o + column reset (new)
• Timestamp- & Data- buffer limitations removed
• Inefficiency < 7% up to 2.5x1034cm-2s-1 (as before)
• In 130nm technology column drain per column possible (instead of double columns) dashed lines
• 7% inefficiency at 4.5x1034cm-2s-1
Inefficiency for r= 4cm layer
[1034]
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0.1
1
10
100
4 6 8 10 12 14 16 18
Radius [cm]
Dat
a Lo
ss
[%]
DC busy
readout + DC reset
Pixel busy
Column busy (new)
r/o +column reset(new)
• Cannot operate < 7cm
• For higher radii data loss dominated by readout losses
• Worse for higher L1 trigger rates
• Worse for higher trigger latencies
• new parallel module readout scheme
Inefficiency for 10x1034 cm-2sec-1
Radius [cm]
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LHC (1034cm-2s-1): 11cm 7cm 4cm
SLHC rate tests of CMS Pixel Modules
• High rate tests in X-ray box allows hit rates up to 300 MHz/cm2
• Simulation of pixel read out chip (ROC) compares quite well with observed data loss
• We can identify the data loss mechanisms finite data buffers readout times
• For SEU studies and timewalk need to go to pion beam line at PSI
150 MHz/cm2
20nsec bunch structure
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High rate data losses in x-ray test
LHC (1034cm-2s-1): 11cm 7cm 4cm
• X-ray box (pix.mult.= 1) timestamp buffer overflows dominant
• Pion beam (pix.mult.> 1) data buffer overflow
• Loss due to pixel overwrite (~ pixel size) is not relevant
• Small pixels create large data traffic !
pixel overwrite
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0.4mm
mounting screw whole
new ROC size
• Doubling the buffer size in current ROC periphery increase of 800m just possible
• No R&D needed. Design time ~ 1 month
Doubing the buffer size in 0.25m
Cold upgrade of replacement pixel modules produced in >2010
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• CMS pixel modules need to be replaced. ( r=4cm every 2 years @ 1034)
• LHC SLHC has probably no sharp step in luminosity
• Can improve rate capability of present pixel modules by: - increase buffer size in ROC periphery (2x in 0.25m CMOS, 5x in 0.13m ) - extra data buffer in redesigned TBM with parallel ROC read out scheme
• Replaced modules would be fully compatible with present system.
allows operation of present pixel system at L ~ 4x10 34 cm-2 sec-1
Evolutionary upgrade of CMS pixel modules
Present TBM Read Out Scheme Future TBM Read Out Scheme
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• What are our priorities: - tracker for 1035 but same X/X0 and resolution ? - reduce material budget (X/X0) ? - improve resolution (p/p , impact parameter) ? - triggering ( jet, track selection, impact parameter) ?
• Financial envelope for new Super LHC tracker ~ 115 – 120 MCHF
• How many technologies are radially needed to deal with
- rates ( wide range)- cost per unit area- minimal power per layer minimal material budget (X/X0)
• Present Pixel System has radii : r = 4cm 7cm 11cm 15cm was to costly Layer cost go by area ~ r2 = 16 49 121 225
• Present pixel works well under high rates but cannot be financed for r >18cm !
• Increasing layer radius r cost per surface must scale ~ 1/ r2 !
use cheaper technology, just adequate for rate at this layer radius !
SLHC Pixel Tracking (zero suppressed readout)
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Costs of a CMS Pixel Barrel Module
Cables (40cm) & TBM etc. 100 SFr
HDI (High Density Interconnect) 300 SFr
Sensor (DS, n+ in n-Si) 800 SFr
Bump bonding 3200 SFr
16 Readout chips 0.25 250 SFr ( DMILL: 7200 SFr )
Baseplate (SiN) 50 SFr
Module of Area = 10cm2 Costs ~ 4700 SFr
Optical links, FED , FEC, Power supplies add +15% ~550 SFr/cm2
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Costing Speculations [CHF/cm2]
Pixel (now) Large pixels Macropixels MAPS CMOS+Sensor
Pixel Area 0.015 mm2 0.15 mm2 1.5 mm2 - - - - - - Sensor/ROC 1 / 1 1 / 1 10 / 1 0 / 1 1 / 1 Tiling unit 10 cm2 40 cm2 100 cm2 4 cm2 4 cm2
Bumping 320 20* 2* 0 0 Sensors 80 10 10 0 10+10?(4)
ROC 25 50 2 50 200?(3)
HDI 30 30 3 30 30 Cables 8 8 0.8 8 8 Baseplate 5 5 0.5 5 5 Pitchadjust 0 0 15(2) 0 0 Optical Link (1) 32 6 0.6 6 32 pxFED 25 4 0.4 4 25
Total 525 ~130 ~35 ~105 ~320?
* = C4NP (IBM)
(1) ~ 320 CHF/channel(2) ~ 0.02 CHF/cm fine pitch trace(3) Yield speculations based on experience with DMILL SOI-wafers(4) Extra cost for anodic wafer bonding or SOI wafer growth
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C4NP Low Cost Bumping Injection Molded Solder (IBM & Süss)
Mold
IMS Principle
• IMS allows bump 75 size and pitch of 150
• 200 thick wafers processed so far
• Wafer costs (300mm) ~ 150 $
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Material budget & Supplies
Material budget for 3 Layers at = 0Current Pixel Barrel System:
• Bring power in = 4% (On-Chip regulators,Al-wire)
• Take power out = 29%
Cooling is material budget driver !
Low mass cooling and/or
Reduce power consumption ! X/X0 = 5.79% for 3 barrel pixel layers
1.93% / layer
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Current consumption: Analog: Strips reduce noise Pixels speed (timewalk) ! !
Digital: Information processing (data flow)
CMS ROC: ID = 32mA no tracks
ID = 40mA at 40MHz/cm2 track rate • Reduce power by :
- Technology CMOS 0.25 0.13 Digital: local: YES global: NO Analog: NO W.I.
on chip regulators
- Architecture choice Pixel ROC Power : ALICE 466 mW/cm2 no
ATLAS 335 mW/cm2 no
CMS* 194 mW/cm2 yes
CMS 142 mW/cm2 no
- Custom protocols TBM05 ~ 1/6 power of TBM03 abandon LVDS for 5cm distance custom protocol LCDS (Low Current Differential Swing)
The next SLHC tracker must be very cautious and careful with power consumption !
T
DSm
Un
Ig
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Analog Current .vs. Pixel Capacitance
0
100
200
300
400
500
600
700
800
900
0 50 100 150 200 250 300 350
Pixel Capacitance [fF]
An
alo
g C
urr
ent
[A
]
Sensor capacitance & front end analog power dissipation
Spice simulation of present CMSPIX front end with fixed timewalk (<25nsec)C
urr
ent
for
65 M
ega
Pix
el
measured pixel capacitance (n-pixel 100m x 150m, p-spray)
Time walk is power driver not noise !
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Estimate power consequences of sensor element size
Assume: (for toy-tracker)
• 13 layer tracker with radii = 10 – 130 cm
• simple barrel – forward geometry , break at =1.65 layer area = const x r2
• Sensor capacity with fixed pitch variable length Csens = 0.1 pF 3pF
Csens = const x length pixel strixel strips
• Density of channels N (r) ~ r2/Csens
• Analog power depends on sensor capacitance Iana = Io + slope x Csens (prev. page)
• Digital power dependence on data traffic & particle fluence:
CMSPIX measured Idig = 32mA + 0.2 mA x fluence-rate [MHz/cm2]
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13
57
911
1315
1719
2123
2527
29
S1 S5 S9 S13010020030040050060070080090010001100120013001400150016001700180019002000
Current [Ampere]
Cs [pF]
Radius [cm]
Current .vs. Cs & R
Csensor
[0.1pF]
Layer radius [x10cm]
Csens Ilayers
[pF] [Ampere]
0.1 77.1 K 0.1 -2.2 9.4 K (*)3.0 5.4 K
Current per layer for 13 layer SLHC Pixel tracker r = 10cm – 130cm
Linear power increase with radius. Constant cabling density
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Proposal for low power ohmic link together with Optical Information Hubs
Optical links can have very large bandwidth data hubs
Excellent for long distant (20-100m) information transfer.
e.g. 3.3Gbit/sec link with 1200mW/channel 360 pJ/bit
Optical cabling inside tracker region very painfull, due to variable length. (slack management)
Data transfer inside sensitive tracker region has problem with:1) Variable cable length typ. 10cm – 90cm2) Individual tracking modules have modest information transfer
(~0.3Gbits/sec)
Need for 2 wire ohmic bidirectional link with very low power
Idiff = 0.2mA Z0 = 100 e.g.80 MHz 12 pJ/bit
Low Current Differential Signal LCDS voltage swing 20mV
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Conclusions• Present CMS pixel system can be modifed with 0.13 technology to work < 4-5 x 1034
• Please think about cabling from the beginning especially in view of triggering in view of assembly & cost
in view of accessibility
• Trigger layers will be power hungry ! ( CMS muon-pt should go to outer radius)
• Costing and affordability of SLHC tracker is crucial ! low cost design by us !
• Cooling is the dominant material budget driver ! reduce power ! ! low mass cooling possible ?
• Propose development of LCDS – bidirectional ohmic link with very little power !
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Power Dissipation of Pixel ROC’s
• ROC architecture and designs have considerable influence on power dissipation
• 3 chips in same 0.25 technology for same LHC environment
# Pixels
/ chip
Pixel area
[m2]Idig[mA]
Iana
[mA]
Power/chip[mW]
Power/pixelW]
Power density
[ mW/cm2 ]
ALICE 8192 21’250 150 300 810 99 466
ATLAS 2880 20’000 35 75 190 67 335
CMS 4160 15’000 32 24 121 29 194
CMS no on-chip regulators 87 21 142