CMS Annual Review 2003 PACT - the RPC Muon Trigger Bari-Helsinki-Laapperanta-Warsaw

CMS Annual Review 2003PACT - the RPC Muon TriggerBari-Helsinki-Laapperanta-WarsawJan KrlikowskiWarsaw University

PACT tasks

PACT ESRThe Electronics System Review of the PACT Muon Trigger was held on July, 8th, 2003 in Warsaw.The extensive documentation prepared for this review can be found at :http://hep.fuw.edu.pl/cms/esr/. This documentation reflects the present status of the project.

OutlinePACT layoutProgress since 2002 / Open issuesLink systemCounting room electronicsCost, schedule and milestones

Coverage of initial system4 stations up to ~ 1.24 ; 3 up to ~1.6

PACT electronics: layout and main components

PACT inventory

Progress since 2002UXC55 electronics:progress in the Link System prototypes and design. Now entering preparation of production phase.Firming up of the LB boxes installation plans.UCS55 electronics: progress in PAC algorithms and FPGA implementation of 4/6 plane algorithms,VHDL codes for many compnents (sorters, GhostBusters) developed and tested,New Sorter Crate architechtureOverall organization of the projectNew division of tasks between Bari/ Laapperanta/ Warsaw

UXC55 electronicsProgress in the Link systemLink Board + Control Board + Optical Link: prototypes succesfully tested in the LHC-like beam in May 2003Monitoring of the RPC performance and test pulses succesfully tested as well. Powerful diagnostic tools installed on the LBSetting up of the RPC FEB parameters via I2C still to be tested.Radiation tests of FPGAs and FLASH memoriesReloading of FPGAs on the LB every 4-10 minutes is sufficientIntegration and installation issuses: constant progress

LB functionalities

LB RE1/1 prototype 2003

Tested functionalities of Link SystemSynchronization of signals from chambers Histogram of signals in synchronization window Histogram of all signals from chambersHistogram bx history Snapshots Test pulses TTCrx signals distribution LB FPGAs loading from CB CCU and VME interfaces

Test Pulses Sharpness of the Synchronization Window The sharpness of the synchronization window edge is ~0.3 ns (one channel)Test pulsewidow closewidow openTest pulse directly connected to input channel with short (~5cm) cableSynchronization window

Wykres3

100

99

15

0.02

0

"window open" position [ns]

window / all [%]

Arkusz1

offsetoffsetv[mm/ns]

7.88.15181.8181818182

channel

channela[104ps]position a [ns]position - offset[ns]position - offset[ns]b[104ps]b-apath lenght [mm]path lenght [ns]l - p [ns]13

0%

1929.5681.7681.418940.208203.91.12145-0.29655676.968100

2899.2561.4561.106930.416191.21.0516-0.0544687.07299

3889.1521.3521.002920.416158.20.8701-0.1319697.17615

4868.9441.1440.794890.312160.60.88330.0893707.280.02

5868.9441.1440.794890.312135.70.74635-0.04765717.3840

6868.9441.1440.794900.416139.30.76615-0.02785

7879.0481.2480.898910.416149.70.82335-0.07465

8929.5681.7681.418940.208231.41.2727-0.1453

9858.841.040.69890.416153.30.843150.15315

10858.841.040.69880.312128.20.70510.0151

11868.9441.1440.794900.416142.80.7854-0.0086

12858.841.040.69880.3121280.7040.014

13868.9441.1440.794900.416139.50.76725-0.02675

14909.361.561.21930.312164.90.90695-0.30305

15868.9441.1440.794910.521400.77-0.024

16868.9441.1440.794900.416145.50.800250.00625

17838.6320.8320.482860.312134.80.74140.2594

18848.7360.9360.586880.4161310.72050.1345

19848.7360.9360.586870.312107.40.59070.0047

20838.6320.8320.482850.2081050.57750.0955

21909.361.561.21930.312204.61.1253-0.0847

22828.5280.7280.378850.31295.20.52360.1456

23828.5280.7280.378850.31293.50.514250.13625

24828.5280.7280.378850.31290.50.497750.11975

25828.5280.7280.378850.31284.10.462550.08455

26828.5280.7280.378850.31286.20.47410.0961

27848.7360.9360.586860.20891.30.50215-0.08385

28848.7360.9360.586880.41680.90.44495-0.14105

29858.841.040.69890.416100.40.5522-0.1378

30848.7360.9360.586870.312106.40.5852-0.0008

31868.9441.1440.794890.312120.20.6611-0.1329

32838.6320.8320.482860.312114.60.63030.1483

33848.7360.9360.586870.31298.40.5412-0.0448

34828.5280.7280.378850.312710.39050.0125

35879.0481.2480.898910.416143.90.79145-0.10655

36848.7360.9360.586870.312112.10.616550.03055

37828.5280.7280.378850.31291.70.504350.12635

38828.5280.7280.378850.31291.70.504350.12635

39828.5280.7280.378850.312830.45650.0785

40838.6320.8320.482860.312860.473-0.009

41828.5280.7280.378850.31281.40.44770.0697

42848.7360.9360.586870.31290.30.49665-0.08935

43838.6320.8320.482860.31274.20.4081-0.0739

44828.5280.7280.378850.31276.70.421850.04385

45848.7360.9360.586860.20871.70.39435-0.19165

46828.5280.7280.378860.41679.70.438350.06035

47828.5280.7280.378850.31267.90.37345-0.00455

48848.7360.9360.586870.31274.20.4081-0.1779

49848.7360.9360.586860.20878.50.43175-0.15425

50838.6320.8320.482860.31259.60.3278-0.1542

51889.1521.3521.002920.416133.20.7326-0.2694

52848.7360.9360.586870.31278.80.4334-0.1526

53838.6320.8320.482860.31269.90.38445-0.09755

54848.7360.9360.586870.31288.50.48675-0.09925

55848.7360.9360.586870.31271.70.39435-0.19165

56868.9441.1440.794890.3121320.726-0.068

57818.4240.6240.274840.31251.30.282150.00815

58828.5280.7280.378850.31280.50.442750.06475

59818.4240.6240.274840.31261.40.33770.0637

60838.6320.8320.482850.208570.3135-0.1685

61848.7360.9360.586870.31265.40.3597-0.2263

62848.7360.9360.586860.20852.10.28655-0.29945

63848.7360.9360.586870.31265.40.3597-0.2263

Polaczenia pomiedzy kanalem 45 a wyjsciami impulsow testowych

a[104ps]position a [ns]position - offset[ns]position - offset[ns]b[104ps]b-a

0838.632860.312

1707.28730.312

2727.488760.416

3767.904790.312

4676.968700.312

5767.904790.312

6767.904790.312

7757.8780.312

8737.592760.312

9788.112800.208

109810.1921000.208

11899.256920.312

12788.112810.312

13687.072710.312

14596.136620.312

15606.24630.312

16586.032610.312

Arkusz1

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Chanel

Track length

Track length ( chanel number)

Arkusz2

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Chanel number

Delay []

Delay ( chanell number)

Arkusz3

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Path lenght

Test puls position

channels

[ns]

channels

0

0

0

0

0


window/all [%]

0

0

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[ns]

Path lenght - puls position

0

0

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b-a

b-a

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channels

[ns]

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b-a

Test PulsesInput Channels SkewOne test pulse directly connected to each input channelFound the source of the problem: big skew between input channels (~1ns)Reason: differences in paths lengths on the PCB After fixing the paths lengths the skew should be reduced to ~0.4ns

Wykres5

0

1.7681.12145

1.4561.0516

1.3520.8701

1.1440.8833

1.1440.74635

1.1440.76615

1.2480.82335

1.7681.2727

1.040.84315

1.040.7051

1.1440.7854

1.040.704

1.1440.76725

1.560.90695

1.1440.77

1.1440.80025

0.8320.7414

0.9360.7205

0.9360.5907

0.8320.5775

1.561.1253

0.7280.5236

0.7280.51425

0.7280.49775

0.7280.46255

0.7280.4741

0.9360.50215

0.9360.44495

1.040.5522

0.9360.5852

1.1440.6611

0.8320.6303

0.9360.5412

0.7280.3905

1.2480.79145

0.9360.61655

0.7280.50435

0.7280.50435

0.7280.4565

0.8320.473

0.7280.4477

0.9360.49665

0.8320.4081

0.7280.42185

0.9360.39435

0.7280.43835

0.7280.37345

0.9360.4081

0.9360.43175

0.8320.3278

1.3520.7326

0.9360.4334

0.8320.38445

0.9360.48675

0.9360.39435

1.1440.726

0.6240.28215

0.7280.44275

0.6240.3377

0.8320.3135

0.9360.3597

0.9360.28655

0.9360.3597

Relative test puls position

Path lenght

channels

[ns]

Arkusz1

offsetoffsetv[mm/ns]

7.88.15181.8181818182

channel

channela[104ps]position a [ns]position - offset[ns]position - offset[ns]b[104ps]b-apath lenght [mm]path lenght [ns]l - p [ns]13

0%

1929.5681.7681.418940.208203.91.12145-0.29655676.968100

2899.2561.4561.106930.416191.21.0516-0.0544687.07299

3889.1521.3521.002920.416158.20.8701-0.1319697.17615

4868.9441.1440.794890.312160.60.88330.0893707.280.02

5868.9441.1440.794890.312135.70.74635-0.04765717.3840

6868.9441.1440.794900.416139.30.76615-0.02785

7879.0481.2480.898910.416149.70.82335-0.07465

8929.5681.7681.418940.208231.41.2727-0.1453

9858.841.040.69890.416153.30.843150.15315

10858.841.040.69880.312128.20.70510.0151

11868.9441.1440.794900.416142.80.7854-0.0086

12858.841.040.69880.3121280.7040.014

13868.9441.1440.794900.416139.50.76725-0.02675

14909.361.561.21930.312164.90.90695-0.30305

15868.9441.1440.794910.521400.77-0.024

16868.9441.1440.794900.416145.50.800250.00625

17838.6320.8320.482860.312134.80.74140.2594

18848.7360.9360.586880.4161310.72050.1345

19848.7360.9360.586870.312107.40.59070.0047

20838.6320.8320.482850.2081050.57750.0955

21909.361.561.21930.312204.61.1253-0.0847

22828.5280.7280.378850.31295.20.52360.1456

23828.5280.7280.378850.31293.50.514250.13625

24828.5280.7280.378850.31290.50.497750.11975

25828.5280.7280.378850.31284.10.462550.08455

26828.5280.7280.378850.31286.20.47410.0961

27848.7360.9360.586860.20891.30.50215-0.08385

28848.7360.9360.586880.41680.90.44495-0.14105

29858.841.040.69890.416100.40.5522-0.1378

30848.7360.9360.586870.312106.40.5852-0.0008

31868.9441.1440.794890.312120.20.6611-0.1329

32838.6320.8320.482860.312114.60.63030.1483

33848.7360.9360.586870.31298.40.5412-0.0448

34828.5280.7280.378850.312710.39050.0125

35879.0481.2480.898910.416143.90.79145-0.10655

36848.7360.9360.586870.312112.10.616550.03055

37828.5280.7280.378850.31291.70.504350.12635

38828.5280.7280.378850.31291.70.504350.12635

39828.5280.7280.378850.312830.45650.0785

40838.6320.8320.482860.312860.473-0.009

41828.5280.7280.378850.31281.40.44770.0697

42848.7360.9360.586870.31290.30.49665-0.08935

43838.6320.8320.482860.31274.20.4081-0.0739

44828.5280.7280.378850.31276.70.421850.04385

45848.7360.9360.586860.20871.70.39435-0.19165

46828.5280.7280.378860.41679.70.438350.06035

47828.5280.7280.378850.31267.90.37345-0.00455

48848.7360.9360.586870.31274.20.4081-0.1779

49848.7360.9360.586860.20878.50.43175-0.15425

50838.6320.8320.482860.31259.60.3278-0.1542

51889.1521.3521.002920.416133.20.7326-0.2694

52848.7360.9360.586870.31278.80.4334-0.1526

53838.6320.8320.482860.31269.90.38445-0.09755

54848.7360.9360.586870.31288.50.48675-0.09925

55848.7360.9360.586870.31271.70.39435-0.19165

56868.9441.1440.794890.3121320.726-0.068

57818.4240.6240.274840.31251.30.282150.00815

58828.5280.7280.378850.31280.50.442750.06475

59818.4240.6240.274840.31261.40.33770.0637

60838.6320.8320.482850.208570.3135-0.1685

61848.7360.9360.586870.31265.40.3597-0.2263

62848.7360.9360.586860.20852.10.28655-0.29945

63848.7360.9360.586870.31265.40.3597-0.2263

Polaczenia pomiedzy kanalem 45 a wyjsciami impulsow testowych

a[104ps]position a [ns]position - offset[ns]position - offset[ns]b[104ps]b-a

0838.632860.312

1707.28730.312

2727.488760.416

3767.904790.312

4676.968700.312

5767.904790.312

6767.904790.312

7757.8780.312

8737.592760.312

9788.112800.208

109810.1921000.208

11899.256920.312

12788.112810.312

13687.072710.312

14596.136620.312

15606.24630.312

16586.032610.312

Arkusz1

0

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Chanel

Track length

Track length ( chanel number)

Arkusz2

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Chanel number

Delay []

Delay ( chanell number)

Arkusz3

0

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window/all [%]

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[ns]

Path lenght - puls position

0

0

0

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0

b-a

b-a

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

channels

[ns]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

b-a

00

00

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Relative test puls position

Path lenght

channels

[ns]

Beam testsHistogramsThe muon beam profile The bx history histogram - train of 48 bxs with muons

Beam testsWindow Size and Position ScansRatio of chamber noise signals in synchronization window to all measured. The beam bunch time shape scanned with 1ns window

Beam testsSnapshotsBxChannelRB1RB2

Beam testsSnapshots, Clusters Size Distribution

Wykres13

0

2627

558

240

39

40

10

28

28

10

10

11

6

6

7

7

7

5

7

11

11

13

8

10

3

12

0

0

0

0

0

0

RB3_12 9400V, noiseaverage clusters size 2.1

Arkusz1

snap_l1_lb2_103_6_1_5_32_23_His

LB2 in spill

RPC1: clusCount 3979 clusSize 3.5868309

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RB3_12 9400V, muons,average clusters size 3.6

snap_rpc1_lb2_103_6_1_6_3_27_Hi

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RB3_34 9400V, muons, average clusters size 2.5

snap_rpc2_lb2_103_6_1_6_9_28_Hi

LB2 out spill


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corelations

snap_rpc2_lb2_103_6_1_6_9_28_Hi

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snap_rpc1_lb2_9200v_103_6_2_11_

LB2 out spill


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snap_rpc1_lb2_9200v_103_6_2_11_

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RB3_34 9400V, noise,average clusters size 2.5

snap_rpc2_lb2_9200v_103_6_2_11_

LB2 out spill


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LB2 out spill


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Arkusz1

snap_l1_lb2_103_6_1_5_32_23_His

LB2 in spill


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snap_rpc2_lb2_103_6_1_6_9_28_Hi

LB2 out spill


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corelations

snap_rpc2_lb2_103_6_1_6_9_28_Hi

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snap_rpc1_lb2_9200v_103_6_2_11_

LB2 out spill


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snap_rpc1_lb2_9200v_103_6_2_11_

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snap_rpc2_lb2_9200v_103_6_2_11_

LB2 out spill


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LB2 out spill


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Arkusz1

snap_l1_lb2_103_6_1_5_32_23_His

LB2 in spill


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snap_rpc1_lb2_103_6_1_6_3_27_Hi

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snap_rpc2_lb2_103_6_1_6_9_28_Hi

LB2 out spill


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corelations

snap_rpc2_lb2_103_6_1_6_9_28_Hi

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snap_rpc1_lb2_9200v_103_6_2_11_

LB2 out spill


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snap_rpc1_lb2_9200v_103_6_2_11_

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snap_rpc2_lb2_9200v_103_6_2_11_

LB2 out spill


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LB2 out spill


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Arkusz1

snap_l1_lb2_103_6_1_5_32_23_His

LB2 in spill


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snap_rpc1_lb2_103_6_1_6_3_27_Hi

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snap_rpc2_lb2_103_6_1_6_9_28_Hi

LB2 out spill


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corelations

snap_rpc2_lb2_103_6_1_6_9_28_Hi

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snap_rpc1_lb2_9200v_103_6_2_11_

LB2 out spill


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snap_rpc1_lb2_9200v_103_6_2_11_

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snap_rpc2_lb2_9200v_103_6_2_11_

LB2 out spill


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LB2 out spill


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Arkusz1

snap_l1_lb2_103_6_1_5_32_23_His

LB2 in spill


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snap_rpc1_lb2_103_6_1_6_3_27_Hi

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snap_rpc2_lb2_103_6_1_6_9_28_Hi

LB2 out spill


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corelations

snap_rpc2_lb2_103_6_1_6_9_28_Hi

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snap_rpc1_lb2_9200v_103_6_2_11_

LB2 out spill


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snap_rpc1_lb2_9200v_103_6_2_11_

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snap_rpc2_lb2_9200v_103_6_2_11_

LB2 out spill


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LB2 out spill


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Arkusz1

snap_l1_lb2_103_6_1_5_32_23_His

LB2 in spill


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snap_rpc2_lb2_103_6_1_6_9_28_Hi

LB2 out spill


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corelations

snap_rpc2_lb2_103_6_1_6_9_28_Hi

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snap_rpc1_lb2_9200v_103_6_2_11_

LB2 out spill


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snap_rpc1_lb2_9200v_103_6_2_11_

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snap_rpc2_lb2_9200v_103_6_2_11_

LB2 out spill


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LB2 out spill


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Conclusions from the LB system tests in May 2003The histograms and snapshots work well and have proved their usefulness in testing the performance of chambers.TTCrx signals distribution, test pulses and FPGA loading work well.Optical link will be tested as soon as the quartz for the PLL is availableProblems with CCU block transfer and I2C control of FEBsSolved now

Conclusions of 2002 and 2003 radiation tests in JyvaskylaXilinx Spartan-IIE chips have small enough SEU in configuration bitsDynamic SEU are much less probable then SEU in configuration bits Reloading of the FPGAs every 10 minutes should guarantee that at most a few SEUs will be accumulated in all LBs FPGAs, what should not affect the system performance FLASH memories are resistant enough to radiation and will be used on final Control BoardsMore detailshttp://hep.fuw.edu.pl/cms/esr/docs/RadiationTests.pdf

LB boxes (LBx) inventory

RE1/1 LB boxes a special case

Standard LB boxes VME crates

Integration issues: position of LB boxes in the racks on the balconies

Cabling RE1/2 and 1/3 signalsLink Board Boxes (VME crates) in RacksL max= 11.5 m

YE-1 Racks on Towers

Barrel cablingS.Bally

Progress in UCS55 electronics

USC55 inventory

PAC processor progress in the VHDL codes

FPGA PAC in the barrel

FPGA PAC in the endcaps

COSTWe are revising the PACT CORE cost estimate.At present, the CORE costs are 3750 kCHF, while our starting estimate in 1997 was 3695 kCHF. This cost estimate is for the full trigger system up to eta=2.1 but without RE5.

COST contd.Financing:Finland 1020 kCHFPoland 2060 kCHFBari 100 kCHFTOTAL 3180 kCHF+ Korea 400 kCHF ?Conclusion: either design a cheaper system or stage and hope for extra funding.Almost enoughfor up to eta=1.6

COST contd.Main cost uncertainties/ drivers:PAC FPGAs assumed 300 CHF/pc, total amount for PAC FPGA 345 kCHF, present cost of SPARTAN ALTERAs are higher.Splitter system assumed 1000 CHF/ TB, total amount for splitters 108 kCHF. The cost drivers are opto receivers (on the TB as well as on Splitter Bds) / opto transmitters.

Staging and Cost SavingFirst approximation for the strategy for PACT electronics construction: Order elements for LB system for existing RPCs (up to eta=1.6, w/o RE5) and RE11 (difficulties in latter installation of LBx there). Order elements and assembly Splitter System only for existing RPCs. Order elements and assembly TB w/o PAC FPGAs for the complete system. Order PAC FPGAs for towers up to eta=1.6 If not out of money order more FPGAs/ Links.

Schedule defined Nov. 02

LB project schedule

Splitter schedule

2002 2003 2004

TB- TC- Integration schedule

Milestones defined Nov. 02

ManpowerWarsaw: electronics engineers + WUT students 2.5 + 2 (FTE) PhD students 1.5 Technicians 1.5 Programmers 0.8

Finland:

Bari:

ConclusionsCOST: Almost within estimates from 1997Still substantial uncertainties ( 10 %, maybe even up to 20%?) but firming upSCHEDULE:TightCritical path: LB mechanics, splitters, trigger boardMANPOWER:Biggest worryRecently more help from Finland (LB production and Splitters)Warsaw manpower sufficient for USC55 electronics - TB/ ROB/TCBari: suficient for Sorter Crate

CMS Annual Review 2003 PACT - the RPC Muon Trigger Bari-Helsinki-Laapperanta-Warsaw

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