CMPUT 329 - Computer Organization and Architecture II

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CMPUT329 - Fall 2003

TopicI: Building a Multicycle Data Path and a Control Path for

a MicroprocessorJosé Nelson Amaral

CMPUT 329 - Computer Organization and Architecture II

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Reading Material(optional)

Patterson, David A., and Hennessy, John L., Computer Organization & Design: The Hardware/Software Interface, San Mateo, CA: Morgan Kaufmann Pub., 1994.

Chapter 5Appendix BAppendix C

CMPUT 329 - Computer Organization and Architecture II

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What is Wrong with the Single Cycle Datapath

The clock cycle must have the same length for every instruction

Therefore the clock cycle cannot be shorter than the longest possible path

In our example, this path is the load instruction, it uses:

• the instruction memory, • the register file, • the ALU, • the data memory, and• the register file.

CMPUT 329 - Computer Organization and Architecture II

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What is Wrong with the Single Cycle Datapath

If we consider a machine with more complex instructions (p.e., floating-point arithmetics), or more powerful addressing modes, the single cycle penalty is unnaceptable.

The solution is to adopt a design with shorter clock cycles, but that requires multiple clock cycles per instruction.

CMPUT 329 - Computer Organization and Architecture II

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Mux

0

1

Mux

0

1

Mux

0123

PC

Signext.

Shiftleft 2

Readaddress

Writeaddress

Writedata

MemData

Instruction[31-26]

Instruction[25-0]

Instructionregister

Memory

Readregister 1Readregister 2WriteregisterWritedata

Readdata 1

Readdata 2

Registers 4

32

Mux

0

1

0

1

Mux

ALUresult

Zero

ALU

16

I[25-21]

I[20-16]

I[15-0]

[15-11]

A Multiple Cycle Datapath

CMPUT 329 - Computer Organization and Architecture II

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The Jump Instruction

j loop

Concatenate the 4 most significant bits of the PC with the 26 least significant bits of the IR[25-0] field of the instruction code and shift the result by two.

Write the resulting value in the PC.PC concat(PC[31-28],IR[25-0])<<2

2 10000OpCode address

000010 00 0000 0000 0001 0011 1001 000031 26 25 0

I-Type Instruction Format

CMPUT 329 - Computer Organization and Architecture II

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Values to be written into the PC.

Three possible values can be written into the PC according to the instruction executed:

For taken branches:PC PC + 4 + (sign-extend(IR[15-0]) << 2)

For jumps:PC concat(PC[31-28],IR[25-0])<<2

For all other instructions:PC PC + 4

CMPUT 329 - Computer Organization and Architecture II

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Steps to Execute EachInstruction Type

Instruction Type Step R-type load store branch jump

Fetch IR ← [ ]Memory PC PC ← + 4PC

Decode A ← [ [25Registers IR -21]] B ← [ [20Registers IR -16]]

Target ← + (PC sign- ( [15extend IR -0]) << 2) Execute

ALUopt ← A op B

ALUout ← + A sign- ( [15extend IR -0])

If ( == ) A Bthen PC← Target

PC ← ( [31concat PC -

28], [25IR -0]) << 2

Memory ( [15Reg R -11]) ← ALUout

Memdata ← [ ]Mem ALUout

[ ] Mem ALUout← B

Write -back

( [20Reg IR -16]) ←

memdata

Mux

0

1

Mux

0

1

Mux

0123

012

Mux

PC

Signext.

Shiftleft 2

Conc/Shiftleft 2

Readaddress

Writeaddress

Writedata

MemData

Instruction[31-26]

Instruction[25-0]

Instructionregister

Memory

Readregister 1Readregister 2WriteregisterWritedata

Readdata 1

Readdata 2

Registers 4

32

Mux

0

1

0

1

Mux

ALUresult

Zero

ALU

Target

16

4

2632

I[25-21]

I[20-16]

I[15-0]

[15-11]

Mux

0

1

Mux

0

1

Mux

0123

012

Mux

PC

Signext.

Shiftleft 2

Conc/Shiftleft 2

Readaddress

Writeaddress

Writedata

MemData

Instruction[31-26]

Instruction[25-0]

Instructionregister

Memory

Readregister 1Readregister 2WriteregisterWritedata

Readdata 1

Readdata 2

Registers 4

32

Mux

0

1

0

1

Mux

ALUresult

Zero

ALU

Target

16

32

TargetWrite

PCSource

ALUcontrol

IorDMemWrite

MemRead

IRWrite MemtoReg

ALUSelB

RegDst

RegWriteALUSelA

ALUOp

I[25-21]

I[20-16]

I[15-0]

[15-11]

4

26

32

PcWrite

Mux

0

1

Mux

0

1

Mux

0123

012

Mux

PC

Signext.

Shiftleft 2

ALUcontrol

Conc/Shiftleft 2

Readaddress

Writeaddress

Writedata

MemData

Instruction[31-26]

Instruction[25-0]

Instructionregister

Memory

Readregister 1Readregister 2WriteregisterWritedata

Readdata 1

Readdata 2

Registers 4

32

Mux

0

1

0

1

Mux

ALUresult

Zero

ALU

Target

ControlUnit

16

4

2632

PcWritePcWriteCond

IorD

MemWriteMemRead

IRWrite MemtoRegALUSelB RegDst

RegWriteTargetWriteALUSelA

PCSourceALUOp

I[25-21]

I[20-16]

I[15-0]

[15-11]

32

CMPUT 329 - Computer Organization and Architecture II

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Designing the Control Unit for the Multicycle Datapath

InstructionFetch

InstructionDecode

AddressComputation

ExecutionJump

CompletionBranch

Completion

MemoryRead

MemoryWrite

R-TypeCompletion

WriteBack

Load + Store R-type Branch Jump

Load Store

MemReadALUSelA=0

IorD=0IRWrite

ALUSelB=01ALUOp=00

PCWritePCSource=00

ALUSelA=0ALUSelB=11ALUOp=00TargetWrite

ALUSelA=1ALUSelB=10ALUOp=00

ALUSelA=1ALUSelB=00ALUOp=10

PCWritePCSource=10

ALUSelA=1ALUSelB=00ALUOp=01

PCWriteCondPCSource=01

MemReadALUSelA=1

IorD=1ALUSelB=10ALUOp=00

MemWriteALUSelA=1

IorD=1ALUSelB=10ALUOp=00

ALUSelA=1RegDst=1RegWrite

MemtoReg=0ALUSelB=0ALUOp=10MemRead

ALUSelA=1IorD=1

RegWriteMemtoReg=1

RegDst=0ALUSelB=10ALUOp=00

Load + Store R-type Branch Jump

Load Store

CMPUT 329 - Computer Organization and Architecture II

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Conventions

All outputs that are not explictly asserted, arede-asserted, i.e., they must be specified for thecorrect operation of the datapath.

If a signal that controls a multiplexor is not specifiedin a state, its value is don’t care, and the machinewill work properly regardless of the input that isselected.

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Finite State Machine Controller

State RegisterInput from InstructionRegister Opcode Field

17 DatapathControl Outputs

21 Outputs

10 Inputs

CombinatorialControl Logic