CMPUT 429/CMPE 382 - Computer Systems and Architecture1 CMPUT429 - Winter 2002 Topic5: Memory...

CMPUT 429/CMPE 382 - Computer Systems and Architecture

1

CMPUT429 - Winter 2002

Topic5: Memory TechnologyJosé Nelson Amaral


2

Address Decoding

1

19

1

18

1

16

1

17

1

15

0

14

0

12

0

13

0

11

0

10

0

8

0

9

0

7

0

6

0

4

0

5

0

3

0

2

0

0

0

1

F80001 1 11 1 1 11 1 1 11 1 1 11 1 1 11 FFFFF

Bank 3

1

19

1

18

1

16

1

17

0

15

0

14

0

12

0

13

0

11

0

10

0

8

0

9

0

7

0

6

0

4

0

5

0

3

0

2

0

0

0

1

F00001 1 11 0 1 11 1 1 11 1 1 11 1 1 11 F7FFF

Bank 2

1

19

1

18

0

16

1

17

1

15

0

14

0

12

0

13

0

11

0

10

0

8

0

9

0

7

0

6

0

4

0

5

0

3

0

2

0

0

0

1

E80001 1 01 1 1 11 1 1 11 1 1 11 1 1 11 EFFFF

Bank 1

1

19

1

18

0

16

1

17

0

15

0

14

0

12

0

13

0

11

0

10

0

8

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9

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0

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0

3

0

2

0

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0

1

E00001 1 01 0 1 11 1 1 11 1 1 11 1 1 11 E7FFF

Bank 0


3

Address Decoding on a Microprocessor System

A0

A1

A14 O0

O1

O7CS

OE

• • •

A0

A1

A14

• • •

D0

D1

D7

• • •

D0

D1

D7

• • •

A0

A1

A19

A0

A1

A14 O0

O1

O7CS

OE

• • •

A0

A1

A14

• • •

D0

D1

D7

A0

A1

A14 O0

O1

O7CS

OE

• • •

A0

A1

A14

• • •

D0

D1

D7

A0

A1

A14 O0

O1

O7CS

OE

• • •

A0

A1

A14

• • •

D0

D1

D7

SE0000_L

SE8000_L

SF0000_L

SF8000_L

A19

A18

A17

A15

A16

HIMEN_L1Y0

1Y1

1Y2

1Y3

1G

1A1B

A0

A1

A19

D0

D1

D7

READ

WRITE

74x139

microprocessor 27256 27256 2725627256


4

Types of Memories

Read/Write Memory (RWM):

the time required to read orwrite a bit of memory is independent of the bit’s location

once a word is writtento a location, it remains stored as long as power is appliedto the chip, unless the location is written again.

the data stored ateach location must be refreshed periodically by reading it andthen writing it back again, or else it disappears

we can store and retrieve data

Random Access Memory (RAM):

Static Random Access Memory (SRAM):

Dynamic Random Access Memory (DRAM):


5

Random Access Memories (RAMs)

A Random-Access Memory (RAM) is so called to contrast with its predecessor, the Serial-Access Memory. In a serial accessmemory, memory positions become available for reading ona sequential fashion. Therefore to read an specific memoryposition, the reader must wait a variable time delay for thememory position to became available.

In principle, in a RAM, all positions of the memory can be read on a random fashion with approximately the same delay for all positions.

However, modern RAMs allow burst accesses that favor sequential accesses (complete them in less time).


6

Static-RAM Control Inputs

The outputs of memory chips are often connected to a three-state bus, a bus that can be driven by many devices. Therefore each memory chip should drive thebus only when commanded to do so by the control logic.

Output Enable (OE): Enable the output into the data lines

Chip Select (CS): Used in connection with OE to simplify the design of a multiple chip system.

Write Enable (WE): When asserted, the data inputs are written to the selected memory location.

The following control inputs are typically used to controla Static-RAM.


7

A 2nb SRAM

Addressinputs

An-1

A0A1

Datainputs

DINb-1

DIN0DIN1

controlinputs

CSOEWE

Dataoutputs

DOUTb-1

DOUT0DOUT1

2n b SRAM


8

SRAMs(Static Random Access Memories)

A0

A1

A12IO0

IO1

IO7

OE

CS1

• • •

A0

A1

A12

• • •

D0

D1

D7

2764

HM6264

WE

CS2

A0

A1

A14IO0

IO1

IO7

OE

WE

• • •

A0

A1

A14

• • •

D0

D1

D7

2764

HM62256

CS

A0

A1

A16IO0

IO1

IO7

OE

CS1

• • •

A0

A1

A16

• • •

D0

D1

D7

2764

HM628128

WE

CS2

A0

A1

A18IO0

IO1

IO7

OE

WE

• • •

A0

A1

A18

• • •

D0

D1

D7

2764

HM628512

CS


9

Accesses to SRAM

Read An address is placed on the address inputs while CS and OE are asserted. The latch outputs for the selected memory locations are delivered to DOUT.

Write An address is placed on the address inputs and a data word is placed on DIN; then CS and WE are asserted. The latches in the selected memory location open, and the input word is stored.

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

DOUT3 DOUT2 DOUT1 DOUT0

3-to-8decoder

2

1

0

A2

A1

A0

0

1

2

3

4

5

6

7

DIN3 DIN0DIN2 DIN1

WE_LCS_L

OE_L

WR_L

IOE_L

0

1

1

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

DOUT3 DOUT3 DOUT3 DOUT3

3-to-8decoder

2

1

0

A2

A1

A0

0

1

2

3

4

5

6

7

DIN3 DIN3DIN3 DIN3

WE_LCS_L

OE_L

WR_L

IOE_L

0

1

1


14

SRAM with Bi-directional Data Bus

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

IN OUTSELWR

DIO3 DIO2 DIO1 DIO0

WE_LCS_L

OE_L

WR_L

IOE_L

microprocessor


15

Internal Address Decoding

To avoid high complexity in the decoding logic,all memories (EPROMs, SRAMs, and DRAMs) usetwo-dimensional decoding which reduces the decoder size to approximately the square root of the number of addresses.

The memory cells are organized in a two-dimensionalarray. Some address lines are used to select a rowand the others are used to select a column. Thecell selected by the whole address is at the intersectionof the row and the column.


16

Static-RAM Read Timing

tAA (access time for address): how long it takes to get stable

output after a change in address.

tACS (access time for chip select): how long it takes to get stable

output after CS is asserted.

tOE (output enable time): how long it takes for the three-state

output buffers to leave the high-impedance state when OE and CS are both asserted.

tOZ (output-disable time): how long it takes for the three-state

output buffers to enter high-impedance state after OE or CS are negated.

tOH (output-hold time): how long the output data remains

valid after a change to the address inputs.


17

Static-RAM Read Timing

stable stable stable

valid valid valid

tAA tOZ

tAA

tOE

tACS

tOZ tOE

Max(tAA, tACS)

tOH

ADDR

CS_L

OE_L

DOUT

WE_L = HIGH


18

Static-RAM Write Timing

tAS (address setup time before write): all address inputs must be

stable at this time before both CS and WE are asserted.

tAH(address hold time after write): all address inputs must be held

stable until this time after CS or WE is negated.

tCSW (chip-select setup before end of write): CS must be asserted

at least this long before the end of the write cycle.

tWP (write pulse width): WE must be asserted at least this long

to reliably latch data into the selected cell.

tDH (data hold time after the end of write): All data inputs must

be held stable until this time after the write cycle ends.

tDS (data setup time before end of write): All of the data inputs

must be stable at this time before the write cycle ends.


19

Dynamic Memory Cell

An SRAM cell has a bi-stable latch that requires from four to six transistors to be built.

To deliver the higher memory density required for computer systems, a single transistor memory cellwas developed.

1-bit DRAM cell

word line

bit line


20

Writing 1 in a Dynamic Memories

To store a 1 in this cell, a HIGH voltage is placed onthe bit line, causing the capacitor to charge through the on transistor.

1-bit DRAM cell

word line

bit line


21

Writing 0 in a Dynamic Memories

To store a 0 in this cell, a LOW voltage is placed onthe bit line, causing the capacitor to discharge through the on transistor.

1-bit DRAM cell

word line

bit line


22

Destructive Reads

To read the DRAM cell, the bit line is precharged to a voltage halfway between HIGH and LOW, and then the word line is set HIGH. Depending on the charge in the capacitor, the precharged bit line is pulled slightly higher or lower.A sense amplifier detects this small change and recovers a 1 or a 0.

1-bit DRAM cell

word line

bit line


23

Recovering from Destructive Reads

The read operation discharges the capacitor.Therefore a read operation in a dynamic memory mustbe immediately followed by a write operation of the samevalue read to restore the capacitor charges.

1-bit DRAM cell

word line

bit line


24

Forgetful Memories

The problem with this cell is that it is not bi-stable:only the state 0 can be kept indefinitely, when the cell is in state 1, the charge stored in the capacitorslowly dissipates and the data is lost.

1-bit DRAM cell

word line

bit line


25

Refreshing the Memory

Vcap

0V

HIGHLOW

VCC

time

0 stored

1 written refreshes

The solution is to periodically refresh the memorycells by reading and writing back each one of them.


26

Internal Structure of a 64K 1 DRAM

Rowdecoder

256 256array

Column latches,multiplexers,

and demultiplexerscontrolRAS_L

CAS_LWE_L

A0-A7

columnaddress

latch, mux, anddmux control

rowaddress

DOUT DIN

Step 1: Apply row address

1

Step 2: RAS go from high to low and remain low2

Step 4: WE must be high

4

Step 3: Apply column address

3Step 5: CAS goes from high to low and remain low

5

Step 6: OE goes low

6

Step 7: Data appears

7

Step 8: RAS and CAS return to high

8

Read Cycle on an Asynchronous DRAM

Write Cycle on an Asynchronous DRAM


29

Improved DRAMs

Central Idea: Each read to a DRAM actuallyreads a complete row of bits or word line fromthe DRAM core into an array of sense amps.

A traditional asynchronous DRAM interfacethen selects a small number of these bits to bedelivered to the cache/microprocessor.

All the other bits already extracted from the DRAMcells into the sense amps are wasted.


30

Fast Page Mode DRAMs

In a DRAM with Fast Page Mode, a page is defined asall memory addresses that have the same row address.

To read in fast page mode, all the steps from 1 to 7 ofa standard read cycle are performed.

Then OE and CAS are switched high, but RAS remains low.

Then the steps 3 to 7 (providing a new column address,asserting CAS and OE) are performed for each newmemory location to be read.

A Fast Page Mode Read Cycle on an Asynchronous DRAM


32

Enhanced Data Output RAMs (EDO-RAM)

The process to read multiple locations in an EDO-RAMis very similar to the Fast Page Mode.

The difference is that the output drivers are not disabledwhen CAS goes high.

This distintion allows the data from the current read cycleto be present at the outputs while the next cyclebegins.

As a result, faster read cycle times are allowed.

An Enhanced Data Output Read Cycle on an Asynchronous DRAM


34

Synchronous DRAMs (SDRAM)

A Synchronous DRAM (SDRAM) has a clock input. It operatesin a similar fashion as the fast page mode and EDO DRAM.However the consecutive data is output synchronously on thefalling/rising edge of the clock, instead of on command byCAS.

How many data elements will be output (the length of the burst) is programmable up to the maximum size ofthe row.

The clock in an SDRAM typically runs oneorder of magnitude faster than the access time forindividual accesses.


35

SDRAM Burst Read Cycle


36

DDR SDRAM

A Double Data Rate (DDR) SDRAM is an SDRAMthat allows data transfers both on the rising andfalling edge of the clock.

Thus the effective data transfer rate of a DDR SDRAM is two times the data transfer rate ofa standard SDRAM with the same clock frequency.


37

The Rambus DRAM (RDRAM)

Multiple memory arrays (banks)Rambus DRAMs are synchronous and transfer data on both edges of the clock.


38

SDRAM Memory Systems

Complex circuits for RAS/CAS/OE.

Each DIMM is connectedin parallel with the memorycontroller.(DIMM = Dual In-line Memory Module)

Often requires buffering.

Needs the whole clockcycle to establish valid data.

Making the bus wider ismechanically complicated.


39

RDRAM Memory Systems


40

Internal RDRAM Organization


41

RDRAM Banks SDRAM Banks


42

Further Reading

To learn more about the differences betweenSDRAM systems and Rambus DRAM systemsfor personal computers, visit these websites:

http://www.hardwarecentral.com/hardwarecentral/reviews/1787/1/http://www.pcguide.com/ref/ram/tech_SDRAM.htm

Crisp, Richard, “Direct Rambus Technology: The New Main Memory Standard,” IEEE Micro, 17(6): 18-28, Nov/Dec, 1997.

CMPUT 429/CMPE 382 - Computer Systems and Architecture1 CMPUT429 - Winter 2002 Topic5: Memory...

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