CMPUT 229 - Computer Organization and Architecture I

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CMPUT229 - Fall 2006

Computer Organization and Architecture I

Li-Yan Yuan

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Hennessy, John L., Patterson, David A., Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann Pub., San Mateo, CA. (H&P)

Patt, Yale N., and Patel, Sanjay J., Introduction to Computing Systems: from bits & gates to C & Beyond, McGrawHill Press, 2001. (P&P)

Goodman, James and Miller, Karen, A Programmer’s View of Computer Architecture with Assembly Language Examples from the MIPS RISC Architecure, Oxford University Press, 1993. (G&M)

Bryant, Randal E., O’Hallaron, David, Computer Systems: A Programmer’s Perspective, Prentice Hall, 2003. (B&H)

In Your Course Package

Hennessy, John L., Patterson, David A., Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann Pub., San Mateo, CA. (H&P)

Bryant, Randal E., O’Hallaron, David, Computer Systems: A Programmer’s Perspective, Prentice Hall, 2003. (B&H)

Patt, Yale N., and Patel, Sanjay J., Introduction to Computing Systems: from bits & gates to C & Beyond, McGrawHill Press, 2001. (P&P)

Goodman, James and Miller, Karen, A Programmer’s View of Computer Architecture with Assembly Language Examples from the MIPS RISC Architecure, Oxford University Press, 1993. (G&M)

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Additional Optional Reading

An easy to follow reference to MIPS Assembly:

Waldron, J., Introduction to RISC Assembly Language Programming, Addison-Wesley, ISBN 0-201-39828-1.

An excellent reference book for the C Language:

Harbison, Samuel P., and Steele Jr., Guy, C: A Reference Manual, Prentice Hall, 4th Edition, 1995.

A more recent and complete book on MIPS Assembbly:

Britton, Robert L., MIPS Assembly Language Programming, Prentice Hall, Upper Saddle River, NJ, 2004.

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Contents

Computer organization and instruction sets

Assembly language (MIPS and SPIM)Number systems and binary arithmeticsDigital Logic and logic gatesExceptions and interruptsInput and output programmingMemory hierarchy

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Instructor: Prof. Li-Yan YuanOffice: Athabasca 3-56Phone: 492-7171email: yuan@cs.ualberta.caOffice Hours: MWF14:00-14:00

www.cs.ualberta.ca/~yuan/courses/229

http://ugweb.cs.ualberta.ca/~c229

Admin. Information

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Important Dates

September 18(Monday) : lab classes start this week

October 27 (Friday ） : mid-term examDecember 6 (Wednesday) : last day of classesDecember 15 (Wednesday) : final exam (tentative)

Assignments and Labs to be posted later

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Grade Distribution

Course work will carry the following weights towards your final grade:

Five (5) Lab. Assignments: 25% Five (5) Assignments: 10%

Midterm Exam: 25%Final Exam: 40%

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Late Submission PolicyFor Labs:

There is no late submission for labs!All deadlines are “drop-dead deadlines”!

Deferred exams will be scheduled before Feb. 2, 2007, and will be different from the final given on the scheduled date.

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NO Late Submissions!!!!

Did I mention?

None. At all.

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Computer Organization

Memory

(See CullerSinghGupta, pp. 32)

Input/Output

CPU

Bus

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Computer Organization

P-Pro bus (64-bit data, 36 bit address, 66 MHz)

CPU

InterruptControler

256-KBL2

Bus interface

PCIBridge

PCII/O

Cards

PCII/O

Cards

PCII/O

Cards

PC

I B

us

PCIBridge

PCII/O

Cards

PCII/O

Cards

PCII/O

Cards

PC

I B

us

MemoryController

Memory Interleave Unit

1-, 2-, 4-wayInterleaved

DRAM(See CullerSinghGupta, pp. 32)

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Example of SMP machine:Pentium “quad pack”

P-Pro bus (64-bit data, 36 bit address, 66 MHz)

CPU

InterruptControler

256-KBL2

Bus interface

CPU

InterruptControler

256-KBL2

Bus interface

CPU

InterruptControler

256-KBL2

Bus interface

CPU

InterruptControler

256-KBL2

Bus interface

PCIBridge

PCII/O

Cards

PCII/O

Cards

PCII/O

Cards

PC

I B

us

PCIBridge

PCII/O

Cards

PCII/O

Cards

PCII/O

Cards

PC

I B

us

MemoryController

Memory Interleave Unit

1-, 2-, 4-wayInterleaved

DRAM(See CullerSinghGupta, pp. 32)

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How to ask your computer to perform a task?

Ask your friend or little sister/brother do it for you Use a graphic tool such as a web browserWrite a high level program such as C, JavaWrite an assembly language programWrite a sequence of ONEs and ZEROs

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What can be recognized by a computer ?

English article or Chinese article ? Windows, Macintosh, or Linux ? C or Java A sequence of 1s and 0s

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Converting Source into Executable Files

Henn-Pat, pp. A-4

COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED

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A More Complete Story

Sourcefile Compiler

Assemblerfile

ObjectfileAssembler

Linker

Sourcefile Compiler

Assemblerfile

ObjectfileAssembler

Sourcefile Compiler

Assemblerfile

ObjectfileAssembler

Programlibrary

Programlibrary

Executablefile

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Converting Source into Executable Files

Henn-Pat, pp. A-8

COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED

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The Linker

Henn-Pat, pp. A-18COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED

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When to use Assembly Language?

When you don’t have the tools to program in higher level:new embedded processorscompilers that check deadlines for real time

system do not exist yet

When the tools fail:Compilers still generate sub-optimal code

When you are building the tools:Compiler designer/builders must know

assembly well

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Anatomy of an Object File

Size and positionof other pieces.

Machine Code

Binary DataRepresentation.

References that must changeif the program is moved

in memory.

Associate addresseswith external label.

Unresolved references.

Compilation informationto allow mapping of

addresses to source code.

Henn-Pat, pp. A-13COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED

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How to distinguish one computer from others

PC, Mac, Server, mainframe Windows, Macintosh, Unix, Linux AMD, Intel, Sun, IBM Virtual machines for Java, Prolog, etc

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Instruction Set

An instruction set (or instruction set architecture ISA) includes a set of machine codes (instructions) of a particular CPU design

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Instruction Set

ISA is part of the computer architecture Datatypes Instructions registers Addressing mode Memory architecture Interrupt and exception Intput and output

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Instruction Set

PDP-11Motorola 68000MIPSIBM 700/7000SPARCX86 (Pentium, AMD64)Java virtual machines

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Type of instruction sets

CISC ( Complex Instruction Set Computer) Support many complicated instructions complete a task in as few lines of instruction

as possible RISC (Reduced Instruction Set Computer)

use simple instructions that can be executed within one clock cycle.

Pay penalty in the unusual cases but speed up for most simple instructions

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Example: Multiplying two numbers in memory

M[2,3] = M[2, 4] X M[5,2]

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M[2,3] = M[2, 4] X M[5,2]

CISC Approach MULT 2:3, 5:2

RISC Approach LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3 A

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CISC

Emphasis on hardware support multi-clock complex

instructionsMemory-to-memory LOAD and STORE

incorporated in instructionsSmall code sizesHigh cycles per second transistors

used for storing complex instructions

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RISC

Emphasis on softwareSingle-clock reduced instruction onlyRegister to register LOAD and STORE

are independent instructionsLow cycles per secondLarge code sizesSpends more transistors on memory

registers

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The Performance

Time time cycles instructions

Program cycle instruction program= X X

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Instruction Set

PDP-11Motorola 68000MIPSMacBookSPARCX86 (Pentium, AMD64)CISC

RISC

RISCRISC

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MIPS

Microprocessor without Interlocking Pipeline

Designed by John HenessySGI graphics workstations and

servers

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Basic Architecture of MIPS

32 registers memory organization

each byte with its own address 32 bit

I/O Organization

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SPIM Simulator

SPIM is a simulator that runs programs for the MIPS R2000/R3000 RISC computers

Advantages using SPIM Self contains, system independent, stable software, Supports X-windows, with a debugger