CMPE222 Project

Synthesis Optimization------ analysis of DC & DW

Zhenrong Wang , Mingcui Zhou @EEInstructor: Prof. Wakefield

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OutlineOutline

• Preparation for Synthesis: source code

• HDL level Optimization

• Optimization using Design_analyzer constraints & DesignWare

• Depth study of Synthesis Optimization

----look into DesignWare *

• Build your own synthesis Library (Optional)

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(I) HDL Level Optimization

Using FIR 3 Tap • 3 latency version: combine status

(wait, load) and (shift, output)• Simulator: Modelsim 5.5 SEb

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Output verification

• 2 latency version : wait and combine all the calcuation sta

tes into one

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HDL level Optimization

• Compare compiling results:

Power Area Delay Total

2latency 6.96768 80242 9.6 5.367

3latency 9.89287 78825 9.61 7.493

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Reason for difference

• Less status for less Power

• More combined calculation hinder reuse of adders and multipliers

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Conclusion for HDL Optimization

Conciseness may not be the best

but it’s good approach!

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(II) Adding Constraints

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Wishing for the best result?

If constraints

( Max area == 0 && Max delay == 0

&& Power ==0 )

Compiling time = hours long;

Result = WORSE;

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Understand how it works

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Foundation Library

Design Library (.syn, etc)

contains the circuit descriptions that are immediately usable by the Synopsys tools.

Synthetic Library (.sldb)

links the circuits in a design library to the Synopsys Synthesis tools

/projects/cadlab/synopsys/2001.08/dw

/dw0*/lib Design library

/projects/cadalb/synopsys/2001.08

/libraries/syn Synthetic Library

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Default Synthesis Library

• standard.sldb• List name of default:

“Synthetic Operator”

“Synthetic Model”

“Implementations”

“binding relationship of each level”

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Synthetic Library Structure

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The standard.sldb of synopsys

• See what contains in the synopsys default synthesis library (different to users with different license)

• > cd /projects/cadlab/synopsys/2001.08

/library/syn/• >Source your_synopsys.rc• >dc_shell //enter dc_shell• dc_shell> report_synlib standard.sldb

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Contents of .sldb

• Synthetic operator type ADD_TC_CI_OP add ADD_TC_OP add Synthetic model desciprtion DW01_add design_library: DW01 HDL parameter: width =...• Synthetic model Implimentation DW02_mult sim v csa leg =

"(A_width>=1) &

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Examples of tracing component

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Bounding of each level• Synthetic Model• DW02_mult …• b2 bound_operator: MULT_UNS_OP • Pin Associations (module, oper):• A, A• B, B• … …• ---------------------------------------------------------------------------• Module Implementations Attributes/Parameters• --------------------------------------------------------------------------• • DW02_mult sim v csa leg = "(A_width>=1) &&…

How constraints works?

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Implementation Selection

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How to optimize

• To characterize the implementations for comparison, the synthesis tool creates a pre-optimized model for each one, in the user’s target technology. The timing and area characteristics of the models serve as the basis for implementation selection.

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Content of technology .db

• Main parts

• Area

• time

• cell(OR2I) {• area : 2;• cell_footprint : "or2";• pin(A) {• direction : input;• capacitance : 1;• } … …• {• intrinsic_rise : 0.18;• intrinsic_fall : 0.65;• rise_resistance : 0.223;• fall_resistance : 0.0083;•

What if we choose both: max area==0&&delay==0

Tools optimize timing first by default!

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One constraint Each time(1)

2-latency version Typical db

Dynamic Power

Cell Area Arrival Time

Total

Default 6.9676 80242 9.6 5.367

Area 7.0365 80708 9.61 5.457

Timing 7.603 86439 9.61 6.315

Fanout 6.9093 78333 9.6 5.195

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One constraint each time (2)

3-latency version Typical db

Dynamic Power

Cell Area Arrival Time

Total

Default 9.8928 78825 9.61 7.493

Area 9.4758 73453 9.61 6.688

Timing 9.4939 77421 9.56 7.268

Fanout 9.4045 77548 9.62 7.015

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Tips

• Area constraint has the more impact on the optimization compared to others

• High-level behavioral optimization reduces the area, power a lot.

• Fanout constraint reduce the timing but increase the dynamic power

• Default optimization is, in common case, good enough for timing optimization

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III DesignWare

Best case for non-DW

& DW

Dynamic Power

Cell Area

Arrival Time

Total

DW 6.78 60933 9.6 3.966

Non-DW 9.4758 73453 9.61 6.688

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Advantages of using DW

• It offers many different design descriptions (implementations) for a given function;

• users let the synthesis tools choose which implementation to use in any given context.

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See datasheet of DW

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Check information in datasheet

• symbols• Ports description• Parameter• Implimentations …

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Setup environment for DW

• you must set two dc_shell variables: synthetic_library and link_library.

• Add in .synopsys_dc.setup

“ … synthetic_library = dw01.sldb dw02.sldb;

link_library = { typical.db dw01.sldb dw02…}

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How are DesignWare Foundation Components Used?

• Component instantiation:

• Operator Inferencing

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Instantiate Example

// Instantiating DW02_multp in Verilog

• module adder(a, b, tc, out);

• parameter wordlength = 24;

• input [wordlength-1:0] a, b;

• … …

•

// instantiate DW01_addDW02_multp #(wordlength)U1(a,b,tc,out);

endmodule

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example

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Results after Instantiating

Using DW_multp/wall DesignWare db(3 latency)

Dynamic Power

Cell Area Arrival time

Total

Default 2.9248 54882 9.58 1.537

Area 2.9062 49729 9.55 1.38

Timing 2.9274 54353 9.42 1.498

Fanout 2.9319 55208 9.50 1.537

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Set model/implementation

always @(in1 or in2) begin :b1

/* synopsys resource r0:

map_to_module = ”DW01_add”,

implementation = ”cla”,

ops = ”a1”; */

sum <= in1 + in2; //synopsys label a1

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Disabling Selected Synthetic Modules and Implementations

• Tools use the first one if there’s models with same names

• Disable using models in synthetic lib:

set_dont_use standard.sldb/DW01_addsub

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Developing Synthetic Library