CMP 305: VLSI Very Large Scale Integration · PDF fileDevelop an understanding of the...

CMP 305: VLSIVery Large Scale Integration Design

Amr Wassal

Computer EngineeringCairo University

Spring 2013

Adapted from1.Digital Integrated Circuits, Second Edition, ©2003, J. Rabaey, A. Chandrakasan, B. Nikolic2.Mary Jane Irwin, Vijay Narayanan’s slides3.Synopsys University Courseware , Copyright © 2010 Synopsys, Inc. Developed By:Vazgen Melikyan

Credits & Acknowledgments Slides are adapted from:

1.Digital Integrated Circuits, Second Edition, ©2003, J. Rabaey, A. Chandrakasan, B. Nikolic

2.Mary Jane Irwin, Vijay Narayanan’s slides

3.Synopsys University Courseware , Copyright © 2010 Synopsys, Inc. Developed By:Vazgen Melikyan

Course is partially sponsored by:

VLSI Design, Spring 2013 Amr Wassal 2

Intended Learning Outcomes

1. Develop an understanding of the VLSI-related industries and their dynamics and economics.

2. Learn about the different technologies for digital design.

3. Acquire the design skills and learn the flow for digital VLSI design.

4. Understand the design metrics and the interplay among design trade-offs, and technology issues.

5. Get introduced to the concept of IP reuse and using it as a means to close the productivity gap.



Suggested References

No Specific Textbook

References1. “Modern VLSI Design: IP-Based Design,”

Wayne Wolf, Prentice Hall, 4th Edition, 2008.

2. “Digital Integrated Circuits,” J. Rabaey, A. Chandrakasan and B. Nikolic, Prentice Hall, 3rd

Edition, 2008.3. “Application-Specific Integrated Circuits,” M. Smith,

Addison-Wesley Professional, 2008.

Course Requirements & GradingSubject to change:

• Tutorials: 5 % - individual effort

• Midterm: 10 % - individual effort

• Final: 60 % - individual effort

• Project: 20 % - group effort

• Lab: 5 % - individual effort

• Office hours: by email appointment a_wassal at yahoo.com

Email subject must start with [CMP305]

• TAs:Engs. Omar El-Seddeek and others



Course Outline• Semiconductor Industry and Technology

Overview

• MOS Transistor, IC Design Flows

• Logic Families, Standard Cells

• Timing in Digital Systems

• Front-end Design Flow

• Back-end Design Flow

• Design-for-Testability (DFT)

• Packaging, Interconnection and Signal Integrity

• Low-Power Design


Industry & Technology Overview

• Introduction to the semiconductor industry

• Functional Structure of a Fabless Company

• Manufacturing Process

• Design Rules






• Design Rules


Semiconductors TAM

World GDPUS$62T

Applications: Goods embedding electronics and ICT services

US$10’s Trillions

Electronic GoodsUS$1,000B

Electronic Components

Semiconductor Components

US$300B

EDAUS$4B

• Per annum size of Semiconductor market is US$300B in 2010

• Drives the whole world economy

• The locomotive that powered the economy of many tigers


Semiconductors Industry Segments:By End-User Market

Computing

Telecom/Wireless

Consumer

Automotive

Military and Aerospace

Medical

Industrial/Process Control/Measurement

and more…

• Total available market of ~$300 Billions in 2010.


Semiconductors Industry Segments:By Business Model

• Integrated Device Manufacturer (IDM) Intel, AMD, IBM, LSI Login, Sony, TI, Infineon, Toshiba,

Samsung, NEC, Mitsubishi, Philips, Motorola,... etc. Has in-house manufacturing using its own Fabs besides its own

design capabilities (vertical integration).• Fabless

Marvell, Broadcom, Xilinx, PMC-Sierra, nVidia, ATI, Qualcomm,… etc.

Outsources manufacturing to (usually) a foundry. Focuses on products, IP, patents and licensing.

• Merchant Foundry TSMC, UMC, SMIC,… etc. Finds work from the pool of fabless companies. Requires careful scheduling, pricing and contracting to remain at

full utilization.


Semiconductors Industry Segments:By Role in the Supply-Chain• Design house (IDM, Fabless):

Intel, IBM, LSI Login, Sony, TI, Infineon, Toshiba, Samsung, NEC, Mitsubishi, Philips, Motorola,... vs. Marvell, Broadcom, Xilinx, PMC-Sierra, nVidia, ATI, Qualcomm,… etc.

• Manufacturing (IDM, Foundries): Intel, IBM,… vs. TSMC, SMIC, Global Foundries,… etc.

• Assembly/Testing: Amkor, Siliconware Precision, Advanced Semi Engineering,… etc.

• EDA Vendor: Synopsys, Cadence, Mentor Graphics, Magma (Synopsys),… etc.

• IP Vendor: ARM, Virage, Artisan, Denali, MIPS, Rambus, Synopsys,

Cadence,… etc.• Design Services:

Wipro, TATA Elxsi, HCL Technologies,… etc.• Fab Equipment Vendor:

Applied Material, ASML, KLM-Tencor, Novellus, Hitachi,… etc.


Semiconductors Industry Segments:By Product

Discretes

Logic

DRAM Memory

Flash Memory

Other Memories

Analog

Optoelectronics

Sensors/MEMS

DSP

Microcontrollers

Microprocessors

CPLDs/FPGAs

ASICs/ASSPs

Tour the Fab

• Videos 1, 2 & 3



Semiconductor Industry - Revisited

• Which role in the semiconductors industry can be readily adopted in the Egyptian industry?

• Which business model to use?

• Why do that?

• What careers to expect?

• Is there any risk?

• Is there any reward?


Semiconductor Industry in Egypt• Mentor Graphics (EDA Multi-national)

• SysDSoft (Now Intel – Siemens Acquisition)

• Si-Ware Systems (Fully Egyptian)

• Newport Media Inc.

• Si-Vision and MEMS-Vision

• Swiftronix (Synopsys affiliated)

• Hittite (US)

• Varkon Semiconductors

• SilMinds

• Mipex

Did I miss anyone?

Other Related Companies• PCB Manufacturing and Assembly AOI

BURAQ

• Electronic systems manufacturing Al-Kharafy

Bio-Business

Valeo

• Morroco Sizable operation for ST-Microelectronics

• Kingdom of Saudi Arabia Sizable research activities







• Design Rules


Functional Structure of a Fabless Company

• Pros and cons of not owning the Fab

Focus on product development rather than technology development.

Limited by available commercial technologies and foundry capacities.

• Often a matrix organization

Rows are business units

Columns are pooled functions


Functional Structure of a Fabless Company (cont.)

• Functional pools support

CAD/EDA tools and IT

PCB/Hardware

Testing or Validation

Layout (Physical Design)

Technology / IP Acquisition

Assembly/Packaging

Product Engineering/ Production

• Business Units own

Design• System

• Digital

• Mixed Signal/Analog.

Verification• System

• Digital

• Mixed Signal/Analog.

Marketing

Applications Engr’g

What about MEMS?

• Videos 4 & 5







• Design Rules

Technology Trends:Basic Active Electronic Devices

First point contact transistor (germanium), 1947John Bardeen and Walter Brattain

Bell Laboratories

Audion (Triode), 1906Lee De Forest

1906 1947


Computing Devices Then…

EDSAC, University of Cambridge, UK, 1949


Technology Trends (cont.)

Intel Pentium II, 1997Clock: 233MHz

Number of transistors: 7.5 MGate Length: 0.35

First integrated circuit (germanium), 1958Jack S. Kilby, Texas Instruments

Contained five components, three types:transistors resistors and capacitors

1958 1997


Advances in Integration

If automobile speed had increased similarly over the same period, we could now drive from Cairo to Shanghai in 20-30 seconds.

Intel 4004(1971)

108 KHz2,300 transistors

Intel Pentium 4 (2000)

1.5 GHz42 million transitors


“Intel Net Corporate Worth will double every 18 months”

Moore’s Law

• “Cramming More Components onto Integrated Circuits” Gordon Moore, Electronics, 1965

• # of transistors on cost-effective integrated circuit doubles every 12-18-24 months.


“Computing Power will double every 18 months”

Technology Generations (or Nodes)

• We refer to the smallest feature size or Critical Dimension (CD).

• 10um 5um 2um 1um 0.8um 0.5um 0.35um 0.25um 0.18um 0.13um 90nm 65nm 45nm 32nm 22nm

• Possible through the magic of device scaling

• Desirable due to manufacturing economics (wafer and batch processing)

• Usually limited by lithography, implies new patterning technology, equipment for each node. $$$$$$


Critical DimensionCD = Pmin / 2

= k1 . λ / NA

CD is the critical dimension

Pmin/2 is the minimum half pitch

k1 is a process factor

λ is the wavelength of the exposure light

NA is the numerical aperture of the projection optics.


Basic Structure of Computers: Technology Trends (cont.)


Advances in Integration - 2007

• Intel Teraflop Chip 2007

• An 80-core ManyCore processor.

• http://techresearch.intel.com/articles/Tera-Scale/1449.htm


Technology is constantly on the move!• Num. of transistors is not limiting factor

Currently ~ 1 billion transistors/chip Problems:

• Too much Power, Heat, Latency• Not enough Parallelism

• 3-dimensional chip technology? Sandwiches of silicon “Through-Vias” for communication

• On-chip optical connections? Power savings for large packets

• The Intel® Core™ i7 microprocessor (“Nehalem”) 4 cores/chip 45 nm, Hafnium hi-k dielectric 731M Transistors

Shared L3 Cache - 8MB

L2 Cache - 1MB (256K x 4)

Nehalem


Moore’s Law over 10 years 210/1.5 ≈ 100

Platform Based DesignSystem Level Synthesis

IP Based DesignHigh Level Synthesis.

RTL / Logic Synthesis

Physical Synthesis

Manual Design

Methodology

Networks on a ChipCGRA

System on a Chip

Architecture

Algorithm on a Chip

Controller on a Chip

SSI / MSI

2010

2000

1990

1980

1970

108 X

106 X

104 X

102 X

X

Sub-system

IPs

ArithmeticRegister

Std. Cells

Polygons

Design ElementGranularity

The granularity of reusable objects increases by 100 X every decade

-- Moore’s EDA LawVLSI Design, Spring 2013 Amr Wassal 33


Review: CMOS Inverter

VDD

Vout

CL

Vin

Full rail-to-rail swing high noise margins

Low output impedance

High input impedance

No direct path steady-state between power and ground no static power dissipation

Propagation delay a function of load capacitance and on resistance of transistors


CMOS Properties• Full rail-to-rail swing high noise margins

Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless

• Always a path to Vdd or GND in steady state low output impedance (output resistance in k range) large fan-out (albeit with degraded performance)

• Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current

• No direct path steady-state between power and ground no static power dissipation

• Propagation delay function of load capacitance and resistance of transistors.


Inverter in CMOS Process


A Modern CMOS Process

Dual-Well Trench-Isolated CMOS

p-

p-epi

p well n well

p+n+

gate oxide

Al (Cu)

tungsten

SiO2

SiO2

TiSi2

field oxide


VDD VDD

VinVout

M1

M2

M3

M4

Vout2

Review: CMOS Buffer


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