ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 1

CMOS THz-ID: A 1.6mm2 Package-LessIdentification Tag Using Asymmetric Cryptographyand 260-GHz Far-Field Backscatter Communication

Muhammad Ibrahim Wasiq Khan, Student Member, IEEE, Mohamed I. Ibrahim, Student Member, IEEE,Chiraag Juvekar, Member, IEEE, Wanyeong Jung, Member, IEEE, Rabia Tugce Yazicigil, Member, IEEE,

Anantha Chandrakasan, Fellow, IEEE, and Ruonan Han, Senior Member, IEEE

Abstract— This paper presents an ultra-small, high-securityidentification tag that is entirely built in a CMOS chip withoutexternal components. The usage of backscatter communicationsat 260 GHz enables full integration of a 2×2 patch antennaarray. For chip compactness and minimum interference causedby direct wave reflection, the backscatter signal is frequency-shifted by 2 MHz and radiated with cross-polarization from thesame antenna array. Such a configuration also, for the first timefor RF tags, enables beam-steering for enhanced link budget.For authentication and secure wireless data transmission, thetag also integrates a compact elliptic-curve-cryptography (ECC)dedicated processor, which is based on a narrow-strong privateidentification protocol. The presented tag has a peak powerconsumption of 21 µW and can be powered by a chip-wide arrayof photodiodes and a DC-DC converter. Using a low-cost 65-nmbulk CMOS technology, the THz ID chip has an area of only1.6 mm2 and demonstrates measured downlink speed of 100 kbpsand upload speed of 2 kbps across 5 cm distance from thereader. The tag-reader authentication/communication protocolis fully demonstrated using external tag power and partiallydemonstrated using the tag-integrated photo-voltaic powering.The tag size is the smallest among all prior RFIDs using far-field communications.

Index Terms—RFID, terahertz, CMOS, package-less, far-field,identification tag, elliptic-curve-cryptography, backscatter com-munication, beam-steering, security

I. INTRODUCTION

Radio-frequency identification (RFID) tags have beenwidely adopted in tracking, authentication, localization,supply-chain management and so on [1]. At present, commer-cial RFID chips rely on external antenna or inductor packagingto facilitate efficient coupling of the RF waves. That, however,significantly increases the overall size of the tag, making itimpossible to be attached to small objects such as medicalpills, tooth implants and semiconductor chips. The associatedauthentication and recording of manufacturing data, therefore,can only be realized indirectly through special treatments

This is the extended version of a paper originally presented at the IEEESolid-State Circuit Conference (ISSCC), San Francisco, CA, USA, Febru-ary 2020. This work is supported by National Science Foundation (Grant No.SpecEES ECCS-1824360).

Muhammad Ibrahim Wasiq Khan, M. I. Ibrahim, Anantha Chandrakasanand R. Han are with the Department of Electrical Engineering and Com-puter Science, Massachusetts Institute of Technology (MIT), Cambridge,MA 02139, USA. Chiraag Juvekar was with MIT and is now with AnalogDevices Inc., Boston, MA 02110, USA. Wanyeong Jung was with MIT, andis now with the Department of Electrical Engineering and Computer Science,Korea Advanced Institute of Technology, Daejeon, South Korea. Rabia TugceYazicigil was also with MIT and is now with the Department of Electricaland Computer Engineering, Boston University, Boston, MA 02215, USA.

(e.g. holographic patterns) on the goods packages, whichleave loopholes for counterfeiting. Another barrier for RFIDapplications is the additional cost associated with the chippackaging, which takes up to two thirds of the total tag cost[2], [3]. That makes RFID technologies much less competitivethan, for example, printed barcodes for low-cost products (e.g.a 50-cent candy bar) [1]. Lastly, it is noteworthy that pervasiveelectronic tagging raises serious privacy concerns related toinadvertent and malicious tracking of the tagged assets. Othersensitive data related to, for example, finance and personalhealth, are also increasingly generated by RFIDs. However,high-security encryption and authentication protocols normallyrequire intensive computing, making reliable data protectiondifficult to realize in power/hardware-constraint RFID opera-tion environments.

Typical RFID

THz-ID Sesame

Seed

Fig. 1: Cryptographic THz-ID tag: a size comparison and its potentialapplications.

In order to enable secure and ubiquitous asset tagging, fully-passive, particle-sized cryptographic chips without externalpackaging are highly desired. However, the recently demon-strated prototypes [4]–[8] that took the above path face eithersize, energy, communication or security limitations. In [4], a9-mm2 sensor node (volume=27 mm3) is implemented outof a stacked packaging of multiple functionality layers forphoto-voltaic powering, battery, antenna, etc, which increasesthe overall cost. In [5], a 116×116 µm2 monolithic radiochip is demonstrated, but it relies on near-field inductivecoupling at 5.8 GHz, which severely limits the operation rangeto ∼1 mm. In comparison, far-field tag interrogation usingresonant antennas effectively increases the range. Using thisprinciple, a pad-less chip with 24-GHz downlink and 60-

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 2

GHz uplink boosts the range to 50 cm [6], but the chip-integrated transmitter (Tx) and receiver (Rx) antennas alsoincrease the chip size to 3.7×1.2 mm2. While this is alreadyan impressive form factor, to fully enable the applicationsdescribed previously, a further miniaturization is desired. It isalso noteworthy that the above three works [4]–[6] also do notsupport cryptographically secure identification. To this end, [7]demonstrates a secure authentication tag, but the chip requiresan 8-mm2 external antenna; moreover, only a symmetric-keycryptography is realized due to the limitations of size andenergy.

In this paper, we present a package-less, monolithic tagchip in CMOS, that has a size of 1.2×1.3 mm2 (shown inFig. 1) [9]. To enable far-field operation with such smallform factor, the downlink/uplink carrier frequency is pushedinto the the low terahertz (THz) regime (260 GHz). That,along with a Tx-Rx antenna sharing technique, allow foran on-chip integration of a 2×2 antenna array and a tag-side, beam-steering capability. An operation range of 5 cmis demonstrated, which makes barcode-reader-like applica-tions possible. Meanwhile, an ultra-low-power elliptic-curve-cryptography (ECC) dedicated processor is integrated in theTHz-ID chip, which provides high-security compact asym-metric encryption. The whole chip consumes a peak powerof 21 µW, which is provided by an array of chip-integratedphotodiodes. The paper is organized as follows: in Section II,the overall architecture of the chip is described. Details of theTHz downlink and uplink circuits are given in Section III.Then, Section IV presents the design of the ECC securityprocessor. The photo-voltaic powering scheme is discussed inSection V. After showing the experiments and demonstrationsin Section VI, we conclude the paper in Section VII withcomparisons with the prior state-of-the-arts.

II. TAG HARDWARE ARCHITECTURE

The architecture of the tag chip is shown in Fig. 2. Theincident 260-GHz wave (red) from the reader is coupled toa 2×2 array of on-chip patch antennas. The THz signal witha particular linear polarization received by each antenna isextracted from two sets of antenna feeds with a power-splittingratio of ∼1:1. Half of this power, used for the downlink, isrectified to baseband via four THz square-law detectors. Theother half of the input power is used for the back-scatter uplinkcommunication. It is noteworthy that a strong, direct reflectionof the incident downlink wave, due to the large surface ofthe object to be tagged, is inevitable. It is, therefore, criticalto eliminate the interference of such reflected waves to theactual data-modulated signal, which is back-scattered by thechip. To this end, single-sideband (SSB) frequency mixing isadded to the back-scattering process, so that the final carrierfrequency for the uplink (fUL) is ∼2 MHz below that forthe downlink (fDL). Meanwhile, the chip is designed so thatthe polarization of the back-scattered wave (blue in Fig. 2) isalso rotated by 90, so that the tag reader’s receiver antennawith a linear polarization aligned with the back-scattered wavecan further suppress the directly reflected wave by >20 dB.The cross-polarization scheme also allows for re-using the

Cryptographic Processor

DC-DC

Converter

Downlink:

THz Square-Law

DetectorsPhotodiode Array

for Light-Power

Harvesting

Uplink: Frequency-

Shifting SSB Mixer

Multi-Functional

Patch Antenna

Element

LO Signal

Backscattered THz Wave for Uplink

(fUL=fDL-2MHz)

Incident THz Wave

for Downlink (fDL)

Fig. 2: Overall architecture of the THz-ID tag.

downlink antennas for uplink antennas, which reduces the tagarea by ∼2x. More details of the antennas will be given inSection III-A.

Both the downlink and the uplink utilize ON/OFF-shift-keying (OOK) modulation, and offer data rates at 100 kbpsand 2 kbps, respectively. The THz SSB mixers for the fre-quency shifting of the uplink carrier are driven by four 2-MHz local-oscillator (LO) signals generated by an integratedcryptographic processor. With independent, digital control ofthe phase in each LO, beam-steering for the THz uplinkwave is achieved. That enhances the link budget when thetag is not perpendicularly facing the tag reader. Moreover,without the beam-steering capability, the tag would act likea mirror and make the backscatter communication more proneto eavesdropping.

In our protocol, the cryptographic processor first sweepsthe uplink beam direction until reliable communication isestablished. Then it will work with the reader to performa narrow-strong private identification protocol [10] under apublic-key cryptography scheme (specifically elliptical-curvecryptograhy). It guarantees that any eavesdropper who doesnot possess the readers’s private key cannot identify which tagparticipates in the protocol by merely monitoring the wirelesslink.

The photo-voltaic powering of the tag is realized through alarge array of P-N photodiodes placed under and beside theantennas. To allow the incident light to reach the photodiodes,the patch and the ground plane of the antenna possess a fishnetpattern (Fig. 2). A DC-DC converter is implemented in orderto boost the photodiode output voltage to ∼1 V. A 8-MHzoscillator is integrated to provide the LO signal for the THzSSB mixers, as well as the clock signals for the DC-DCconverter and the cryptographic processor.

III. THZ DOWNLINK AND UPLINK

In this section, we describe the design of various tagcomponents that enable 260-GHz communication with verysmall power consumption and chip area.

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 3

A. Multi-Functional On-Chip Patch Antenna

To enable front-side radiation, the tag integrates 2×2 patchantennas that are shared between the downlink and uplink.To realize such sharing, a near-square shape is adopted forthe patch, so that its two dominant excitation modes i.e.TM010 and TM001 with orthogonal polarizations have the sameresonance frequency (∼260 GHz). As Fig. 3a indicates, toexcite a certain mode (TM010 in this case), we can eitheruse a differential feed symmetrically connected to the patchedge along the x-direction (i.e. Feed 1), or a single-endedfeed connected to the center of the patch edge along the y-direction (i.e. Feed 2). Therefore, when both feeds are used andthe downlink wave aligns with the TM010 mode of antenna,the received power is split into the two feeds for backscatter(Feed 1) and downlink demodulation (Feed 2), respectively.Accordingly, the THz SSB mixer has a differential input, whilethe THz square-law detector for the OOK de-modulation ofdownlink has a single-ended input (Fig. 3a).

Next, to radiate the uplink signal with orthogonal polariza-tion, the TM001 mode of the same antenna is used (Fig. 3b)and is excited by a single-ended feed (Feed 3) at the centerof the patch edge along the x-direction. Accordingly, the THzSSB mixer provides a single-ended output, as described laterin Section III-B. Note that the electrical field distribution of theassociated TM001 mode has a null at Feed 2, so the leakageof the uplink signal to the THz square-law detector is verysmall. Similarly, the received downlink signal does not leakinto the SSB mixer output either (Fig. 4a)1.

To ensure the reliability of both the downlink de-modulationand the backscattering, the power splitting ratio in Fig. 3a isset to about 1:1. The value of the ratio is controlled by thetermination impedances at Feed 1 and Feed 2 (i.e. Z1 and Z2

in Fig. 4a). To determine the optimal values of Z1 and Z2,we first derive the desired ratio of K=Z2/Z1. Note that forthe TM010 resonance mode, the distribution of the electricalfield (hence the local voltage with respect to ground) along x-direction approximately follows an anti-symmetric sinusoidalpattern (Fig. 4a), and can be expressed as [11]:

V (x) = V0 · sinπx

2LANT, (1)

where V0 is the maximum RMS voltage at the edge of theantenna, and LANT is the dimension of the antenna. Therefore,the power injected into Z1 and Z2, respectively, is:

P1 =4V 2

0

Z1(sin

πL1

2LANT)2 and P2 =

V 20

Z2, (2)

where L1 is the distance of each Feed 1 wire from the antennaedge center (Fig. 4a). For equal power splitting (i.e. P1=P2),the required ratio K is derived:

K =Z2

Z1=

1

4(sin πL1

2LANT)2. (3)

In our design, the value of L1/LANT , limited by the circuitfloorplan, is about 0.18, which leads to K ≈3. Next, to further

1We, however, note that the uplink signal injected at Feed 3 can couple backto the SSB mixer through a common-mode leakage in Feed 1. Techniques toprevent such leakage are described in Section III-B.

determine Z1 and Z2, we note that their optimal values shouldprovide matching between the entire downlink structure andthe incident plane wave. This scenario is emulated in a full-wave electromagnetic simulator, HFSS [12], with a far-fieldhalf-wave dipole antenna (Port 3 in Fig. 4a). The dipole hasa gain of 2 dB and is located at 2 cm from the on-chippatch antenna. The absolute values of Z1 and Z2 are thenswept (while keeping their ratio of K=3). When Z1=150 Ωand Z2=450 Ω, maximum total power transfer from the feeddipole to the two patch antenna ports (S13 & S23 in Fig. 4)is obtained, meaning that the wave reflection on the antennais minimum. Fig. 4b shows the simulated power transmissionco-efficient (including free-space propagation loss) when theabove optimal impedance values are applied.

Regarding the implementation of the patch antenna, itsradiator uses the top aluminium (Al-pad) layer of the CMOSprocess, and has a size of 271 µm in the x-direction and235 µm in the y-direction. These dimensions, along with theadditional feed ports, lead to the same resonant frequencyfor both TM010 and TM001 modes. The patch would havea square shape if only Feed 2 and Feed 3 were presentbut the differential Feed 1 necessitates a non-square shape.The ground plane of the antenna is made out of M3 layer.The antenna is also enclosed by a ground wall (M3 to topaluminum layer), which is 20-µm away from the patch at allsides. That reduces the coupling with neighboring electronicsand antennas while its effect on the antenna performanceis negligible. Using HFSS the peak directivity and radiationefficiency of the antenna in the simulation are 6.7 dBi and27%, respectively, in both resonant modes.

B. THz Frequency-Shifting Backscatter Module

Instead of using a dedicated Tx signal source on a tag[6], which is too power hungry to be practical for THz IDs,our uplink adopts an energy-efficient backscatter scheme forthe incident wave. As described in Section II, the backscattermodule applies a frequency shifting to the THz signal. Shownin Fig. 5, the backscatter module consists of a passive single-side (SSB) band mixer, two 90 Lange couplers and a balun.It takes the differential RF signal from the antenna, generatesits quadrature phases, and then mixes it with a set of 2-MHzquadrature LO signals. The mixer output is finally injectedback to the antenna. Next, details of the components in thebackscatter module are given.

1) Input Balun: In Fig. 3b, the TM001 mode excited by theSSB mixer output presents a common-mode electrical field atthe two wires of Feed 1. As a result, the mixer output willbe fed back to the mixer and undergoes an extra down-shiftby fLO in each round trip. Such loopbacks therefore causeexcessive signal loss and undesired LO harmonic spurs. Toavoid it, between Feed 1 of the antenna and the SSB mixerinput, a balun is inserted, which only allows the transmis-sion of differential signal from the antenna, and blocks thecommon-mode leakage from the mixer output. A return-path-gap-based balun introduced in [13] is used, which consists oftwo microstrip lines coupled via a slot in the ground plane(i.e. return-path gap or RPG, see Fig. 6a). The RPG slot,

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 4

VOUT

RX Mode (TM010)

Differential Mixer Input

RX Mode (TM010)

Common-Mode Detector Input

Downlink

Beamxy

z

Feed 2

THz SSB

Mixer

Square-Law

Detector

(a)

VOUT

TX Mode (TM001)

Common-Mode Mixer Output

Uplink

Beam

xy

z

Feed 2

THz SSB

Mixer

Square-Law

Detector

(b)

Fig. 3: Schematic of the multi-port patch antenna with excited (a) TM010 for downlink and (b) TM001 for uplink.

0

E

Feed 1 Z1

Feed 2

Z2

LANT

L1E0 x

y

0

Far-Field

Feed Dipole

V1

V2

(Port 3)

(Port 1)

(Port 2)

(a)

S13

S23

Expected Power

240 250 260 270 280

-70

-65

-60

-55

-50

-45

-40

Tra

ns

mis

sio

n C

oe

ffic

ien

t (d

B)

Frequency (GHz)

(b)

Fig. 4: (a) The electrical-field distribution of the TM010 mode in the multi-port antenna. (b) The simulated power transmission coefficients from a far-field feed dipole (2 cm away) to the two ports associated with the downlink,when they are terminated by Z1=150 Ω and Z2=450 Ω, respectively. Thedotted line shows the expected total received power, which includes the free-space propagation loss and the gains of two antennas. Ideally, it should be3-dB higher than S13 and S23 when the power transmissions to Port 1 and2 are equal and maximized.

closed by four quarter-wavelength slot resonators in the groundplane, only allows transmission (hence input-output coupling)of quasi-TE-mode wave, which is excited by a differentialsignal in the input microstrip lines. That is illustrated in theelectromagnetic simulation shown in Fig. 6b, and we cansee that the common-mode signal is effectively rejected. Thesimulated insertion loss for the differential mode is ∼1 dB

RF+ RF-

Balun

RF0

RF270

RF180

RF90

LO0

LO270 LO90

LO180R

F-L

O

90° Lange

Coupler

TL1

TL2

Patch Antenna

RF+ RF-

RF

-LO

Patch Antenna

The Loopback Leakage of RF-LO

Signal When No Balun is Used

Fig. 5: Schematic of the backscattering module consisting of a passive SSBmixer, a balun, and two 90 Lange couplers. The loopback effect with theabsence of the input balun is also shown.

and the rejection for the common mode is >10 dB from 240to 280 GHz. The balun is implemented using 2-µm-wide M9microstrip lines and slots in a shunted M1-M2 ground. Notethat a wire placed along the central line of the balun connectsthe SSB mixer output (fRF -fLO) and the antenna (Fig. 5);since the balun central line can be treated as the virtual groundfor the differential-mode transmission, the above wire does notinterfere with the balun operation.

2) Coupler: The Lange coupler that generates the quadra-ture phases for the input 260-GHz signal is shown in Fig. 7a.The electromagnetic simulation results are shown in Fig. 7b;at 260 GHz, the simulated insertion loss excluding the ideal3-dB power splitting factor is 1.2 dB, and the amplitude/phasemismatches at the two output ports are 0.5 dB and 0.5,respectively. The couplers are implemented using the M9 layer,with 3-µm-wide lines and 3-µm spacing among the lines. Thecouplers are also enclosed by a ground plane (with a spacingof 15 µm to provide the signal’s return path and to minimizethe coupling to surrounding structures.

3) Passive Single-Sideband Mixer: Although a double-sideband (DSB) mixer involves simpler hardware implemen-tation, we note that the generated upper and lower sidebands

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 5

Return-Path Gap

M9

M1-M9

λ/4 Slot

Resonator

M1-M2

PCM

PDM

ZL ZL

La

Lb

(a)

E-Field (a.u.)10 100 1000

Differential-Mode Transmission

Common-Mode Transmission

(b)

240 250 260 270 280-12

-10

-8

-6

-4

-2

0

Ins

ert

ion

Lo

ss

(d

B)

Frequency (GHz)

Differential Mode

Common Mode

(c)

Fig. 6: 260-GHz balun based on a return-path gap: (a) structure, (b) simulatedelectrical-field distribution, and (c) simulated insertion loss from the input toone load ZL.

30µm

90° Lange Coupler

From BalunFeed3RF-LO

TL1

TL2

(a)

AmplitudeMismatch

Insertion Loss

240 250 260 270 280-2

-1

0

1

2

(dB

)

Frequency (GHz)

-2

-1

0

1

2 Ph

ase E

rror (D

eg

ree

)

(b)

Fig. 7: (a) The structure of the 260-GHz Lange coupler in the backscattermodule. (b) Simulated insertion loss and output mismatch of the coupler.

RF0 RF90

RF180 RF270

LO0LO90

LO180LO270

RF-LO÷ 4

8-MHz

Oscillator

fLO = 2MHz

0o

90o

180o

270oData

Modulation

M1 M2

M3 M4

R1 R2

R3 R4

Fig. 8: Schematic of the 260-GHz passive SSB mixer.

are applied with opposite phases from the LO; in our tag,therefore, their associated uplink beams would point to differ-ent directions in the beam-steering. That lowers the securityand causes signal loss and interference. In our design, aSSB mixer based on passive quad switches is adopted to notonly suppress the upper-sideband of the output, but also tominimize the power consumption. Shown in Fig. 8, the 2-MHzquadrature LO signals of the mixer are from an 8-MHz on-chiposcillator cascaded by a divide-by-4 static frequency divider2.The phases of the RF and LO signals of the MOSFETs arearranged in the way that at the central current-summing node,the lower-sidebands of all branches add up constructively,while the upper-sidebands cancel. MOSFETs in 65-nm bulkCMOS process have poor switching performance at THz;although wider channel provides smaller ON-resistance, thereis also stronger coupling of THz signal from the channel tothe LO wire through the gate-channel capacitance. To blocksuch coupling, a set of 1.5-kΩ resistors (R1∼R4 in Fig. 8) areadded in series with the transistor gates, which improves themixer insertion loss from 15.5 dB to 13.5 dB in the simulation.Lastly, the OOK uplink modulation is realized by a data-controlled gating of the LO signals.

Shown in Fig. 7a, microstrip TL1 lines combine the drainnodes of the MOSFETs and TL2 is used to assist theimpedance matching to Feed 3 of the antenna. But TL2 fallsshort to provide ideal transformation and the limited space(due to the presence of the balun) hinders the placementof additional matching network components. This impedancemismatch leads to an insertion loss of 2 dB from the mixer toantenna Feed 3.

The simulated differential impedance of the whole backscat-tered module is very close to the desired 150 Ω (see Sec-tion III-A) without any additional matching network. If neces-sary, the impedance matching can be fine tuned by controllingthe lengths (La and Lb, see Fig. 6a) of the transmission linesconnecting the balun to the antenna and coupler, respectively.The simulated common-mode impedance of the backscatteringmodule is largely capacitive (4.2-347.4j Ω). The small realimpedance ensures that the radiation efficiency for uplinksignal is not affected by the loading at Feed 1.

In Fig. 9, we show the eletromagnetic-circuit co-simulationresults of the entire backscatter module. An overall conversionloss of 18 dB (including the 2-dB impedance mismatch loss) isachieved at fRF=260 GHz, at the expense of zero static DCpower. The conversion loss should be improved with moreadvanced CMOS technologies. The module also effectivelysuppresses the components at fRF+fLO and fRF±2fLO. Thecomponent at fRF+3fLO, due to its constructive summationat the mixer output node, appears at the output spectrum, with10-dB rejection ratio. In the future, this may be improved byadopting a polyphase N -path mixer structure. Also note thatthe phase noise of the backscattered signal, being the sum ofthe RF and LO phase noise, is not deteriorated by the ultra-low-power tag LO; because the simulated tag LO phase noise

2Although a divide-by-2 operation for a 4-MHz signal also provides the 2-MHz quadrature LO signal, the additional availability of LO phases (e.g. 45,135, 225, 315 in Fig. 8) provided in our divide-by-4 scheme is utilizedto demonstrate the beam-steering of uplink wave.

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 6

259.96 259.98 260.00 260.02 260.04

-80

-70

-60

-50

-40IF

Po

wer

(dB

m)

Frequency (GHz)

LSB Output fRF-fLO

(Conversion Loss: -18dB)

~10dB

fRF+3fLO

Input RF Carrier

Fig. 9: Simulated output spectrum of the THz backscatter module with a -30-dBm RF input (fRF =260 GHz) and quadrature LO signals at fLO=2 MHz.

VOUT

ABiasing Photodiode

Virtual RFGround

TL1

TL2

TL3

Patch

Antenna 2

Patch

Antenna 1

RF+ RF-

B

C1

C2

Fig. 10: Schematic of a photovoltaically-biased THz square-law detector pair.

is still smaller than that of the RF signal, due to the largedifference between the two signal frequencies (i.e. 2 MHzversus 260 GHz).

C. THz Downlink Circuits

For the de-modulation of the 260-GHz OOK downlinksignal, a THz square-law detector is used to first rectify theinput to baseband, then a low-power amplifier is used toboost the baseband signal to a few hundred mV, so that thesubsequent digital circuits can operate reliably (Fig. 2).

1) THz Square-Law Detector: To achieve zero DC powerand low flicker noise, our 260-GHz square-law detector isbased on a 2.4µm/65nm NMOS device with zero drainbias. Similar to other FET-based THz detectors [14], [15],the optimal responsivity and noise-equivalent power (NEP)occur at a gate bias around the threshold voltage VT ofthe transistor. Conventional VDD-powered circuits, due tothe tag’s energy harvesting operation, has large bias voltagefluctuation. Fortunately, in our CMOS process, the thresholdvoltage (VT≈0.4 V) is close to the light-insensitive, open-circuit voltage of a P-N photodiode (VPD≈0.47 V). Therefore,a simple photovoltaic-biasing circuit shown in Fig. 10 isadopted. Next, we note that any THz-power leakage to thebiasing photodiode and detector baseband output should beavoided. To this end, a dual-detector scheme shown in Fig. 10is used, which utilizes the property that the THz downlinksignals extracted respectively from the adjacent edges of twopatch antennas (see Fig. 2) are differential. As a result, inthe symmetric circuit topology in Fig. 10, virtual RF grounds

250 260 270

-500

-250

0

250

500

Imp

ed

an

ce

(

)

Frequency (GHz)

Ω

Re(Z)

Im(Z)

(a)

0.0 0.2 0.4 0.6 0.8

0.0

0.5

1.0

1.5

Re

sp

on

siv

ity

(k

V/W

)

VGS

(V)

10-12

10-11

10-10

10-9

10-8

NE

P (W

/Hz

1/2)

Biasing

Photo-diode

Voltage

(b)

Fig. 11: (a) Simulated impedance of the detector presented to Feed 2 of theantenna. (b) Simulated responsivity and NEP of the detector.

are formed at Node A and B. Furthermore, TL2 and TL3

are quarter-wavelength transmission lines; they transform thevirtual ground to high impedances at the drain and gate of theMOSFET and therefore, highly confine the THz wave withinthe device. It is noteworthy that since the two differential THzinputs carry the identical OOK envelope, the baseband outputfrom the two MOSFETs is in-phase, and is therefore combinedand extracted at Node B.

In Fig. 10, C1 (∼50 fF) creates an AC short and thereforefacilitates THz self-mixing in the diode-connected MOSFET.C2 (∼15 fF) provides DC isolation from the uplink backscattermodule, and together with TL1 (0.35λ) forms a matchingnetwork to present an impedance that is derived in Sec-tion III-A for equal power splitting. The insertion loss ofmatching network is 1 dB. TL1∼TL3 are 75-Ω coplanar-waveguide (CPW) transmission lines implemented using M9layer. As shown in Fig. 11a, the simulated overall impedanceof the detector circuit is close to the desired impedance valueof 450 Ω. Lastly, Fig. 11b shows that, at the photodiodebias voltage of ∼470 mV, the simulated responsivity andnoise equivalent power (NEP) are 1 kV/W and 32 pW/Hz1/2,respectively. Note that the NEP is limited by the channelthermal noise of the transistor. The noise voltage from thephotodiode, calculated in APPENDIX, is small, and does nottransfer to the transistor output, given that the transistor is inthe triode mode.

2) Ultra-Low-Power Amplifier: Shown in Fig. 12a, thedemodulated signal from the detector is injected into a chainof amplifiers through a high pass filter. The filter, consistingof a 5-pF capacitor and a 5.7-MΩ resistor, has a low cut-off at 5 kHz, and provides not only the input bias of theamplifier but also DC isolation from the THz detector. Theamplifier consists of three stages and two inverting buffers,and are separated by the same high-pass filters; this way theinevitable amplifier offset due to PVT variations and layoutasymmetry is not amplified and saturate the circuits near theamplifier output.

Each amplifier stage consists of an input NMOS differentialpair, which is preceded and followed by source-follower stagesacting as voltage shifters. To save power, all amplifier stagesare biased in the sub-threshold regime. The bias voltageVBIAS in Fig. 12a is generated from a cascode constant-gm

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 7

VDD

VBIAS

VOUT

VIN

0.12μ 60n

4μ 150n

1.2μ 120n

1μ 1μ

1μ 1μ

2μ 1μ

2μ 1μ

2.4μ 120n

0.12μ 60n

4μ 150n

1.2μ 120n

4μ 150n

1.2μ 120n

AMP AMP AMP

VDD VDD VDD

5pF

5.7MΩ

Buffer

VBIAS VBIAS VBIAS

(a)

VDD

RST

VBIAS0.8μ 120n

1.2μ300n

1.2μ300n

1.2μ300n

1.2μ300n

0.6μ300n

2.4μ300n

0.6μ300n

2.4μ300n

1.2μ300n

1.2μ300n

0.6μ300n

0.6μ300n

0.6μ300n

2.4μ300n

500kΩ

(b)

1k 10k 100k 1M 10M0

20

40

60

80

100

Gain

(d

B)

Frequency (Hz)

10n

100n

1µ

10µ Inp

ut R

efe

rred

No

ise (V

/Hz

1/2)

(c)

Fig. 12: The ultra-low-power amplifier in the tag downlink: (a) the schematicof the main amplifier chain, (b) the cascode constant-gm bias generationcircuit, and (c) the simulated voltage gain.

circuit (Fig. 12b). A reset signal RST from the tag’s DC-DCconverter is used to ensure that the biasing circuit jumps froman undesired meta-stable state to the normal state, when VDDramps up to ∼1 V. As shown in Fig. 12c, the simulated gainand the input-referred noise of the amplifier chain are 80 dBand 21 nV/Hz1/2, respectively. The whole amplifier-bufferchain, including the biasing circuit, consumes only 1.5 µW.

The high gain is to ensure reliable toggling of subsequentdigital circuits. It, however, also amplifies the noise, so whenthe THz detector is idle, the amplifier output has a low butnon-zero probability of falsely toggling the succeeding digitalbuffer. To mitigate its impact, before taking any downlinkmessage, the on-chip processor always first validates a 16-bit preamble in front of the message. When the THz detectoroutputs normal data in the downlink mode, the amplifier outputlevel is sufficiently far away from the digital trigger threshold,and the noise impact is suppressed.

IV. CRYPTOGRAPHIC SECURITY PROCESSOR

Fig. 13 shows the cryptographic processor which imple-ments a 128-bit secure ECC-based private ID scheme [10],[16]. The scheme is a 3-move protocol where the tag chipuses its private key and the reader’s public key in order toidentify itself to the valid readers. The scheme guarantees that

Gates Count Breakdown

DC-DC Converter

Tag Protocol

Finite State

Machine

Baseband

8-bit AES

Whitener

Dispatch StageμCode ROMs

μCode Decoder

R0

Dual-Modulus

ALU

coodin coodout

Execute Stage

ECC Core

Crypto Core

din 16doutclk rstn

256

256

256 256

THz Modulator

& Photodiodes

R1

R2

R3

R4

R5

SC

a24

RA

Constant

Register

0

1

Key

Store

RO-TRNG

Control

Data

Fig. 13: Block diagram of the processor on the THz ID.

any eavesdropper who does not possess the reader’s privatekey cannot identify which tag participates in the protocol bymerely monitoring the wireless link.

An important consideration in the choice of the authenti-cation protocol was the need to co-design it with the cryp-tographic accelerators to ensure a low footprint. Firstly, wenarrowed the choice of authentication protocols, to thosethat did not require any hash functions to reduce die-area.Secondly a protocol using x co-ordinate only arithmetic waschosen to enable a compact architecture for the ECC hardwareaccelerator (ECHA). Finally, Curve25519 was chosen since itallowed for an especially efficient x co-ordinate only Mont-gomery Ladder [17]. Since the authentication protocol requiresa secret-scalar multiplication, using the Montgomery Ladderhas the added benefit of providing side-channel resistance [18].

The chip has a ring-oscillator-based true-random-numbergenerator (RO-TRNG) with a 3.3kGE3 8-bit advanced en-cryption standard (AES) whitener and a compact 25kGECurve25519 ECHA to provide the randomness and crypto-graphic primitives used in the protocol. The ECHA is avery long instruction word (VLIW) machine with a 2.8kGEmicrocode ROM that implements the ID scheme. Our chosenauthentication protocol needs to support arithmetic over boththe base field as well as the scalar field. A dual-modulusALU with a 256-cycle multiplier was chosen to allow sharingthe entire datapath between both moduli. As explained above,Elliptic curve scalar multiplication (ECSM) is implementedusing a constant time 650k-cycle projective coordinate Mont-gomery ladder that is secure against simple power analysis.

3kGE represents a technology normalized area metric equivalent to the areaof a thousand minimum-sized NAND gates

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 8

THz Secure Tag THz Tag Reader

Set Beam

Direction

Antenna (φ,θ)

Echo Beam

Direction

Wakeup Beacon

Not

Aligned

Aligned

Check

Beam

Alignment

Dir

ec

tio

n O

pti

miz

ati

on

Authentication

Request

Challenge

AuthenticatedNot

Authenticated

Key GenerationCommit

Calculate and

Reponse

TRNG & AES

Whitener

Verify

ResponseAu

then

ticati

on

Pro

toco

l

Fig. 14: The security protocol between the THz secure tag and the tag reader.

Register savings in the ECHA design and optimized ECSMmicrocode results in 22% lower area and 18% lower cyclecount compared to [19]. Storing the entire ECSM state inregisters allows for low voltage operation down to 0.85V andimproves the energy efficiency of the core to 14.4µJ/ECSM.

Fig. 14 shows the flow of the direction optimization and theauthentication protocol between a THz secure tag and the THztag reader. When powered using light, the tag wakes up andsignals the same to the reader via a beacon. The beam directionis optimized by adjusting two antenna parameters, azimuthangle (φ) and elevation angle (θ), to maximize the link budgetfor data transmission. To this end, the whole space is dividedinto 25 possible angular positions: five in each azimuth andelevation directions with a step size of 45 from 0 to 180.The tag wakes up with φ=0 and θ=90 by default, and thenstarts scanning. It takes ∼20 ms (limited by uplink data rateof 2 kbps) to complete the exchange of one beam directionmessage between the reader and tag. The total time for thebeam search is therefore ∼500 ms.

All THz tags are initialized with a unique private and publickey pair (t, T=tP ) and the reader has the tag’s public key (T )registered in its database. The reader also has a private andpublic key pair (y, Y =yP ) and the reader’s public key Y isknown to all tags. If the reader requests authentication of theTHz tag, the tag commits a fresh random value (R1=r1P )where the randomness (r1) is generated using the RO-TRNGand the 8-bit AES whitener. The reader responds to tag’s

AL LayerPatch

P-Substrate

Deep N-Well

P-Well

N+

P+

N+P+

Anode (DC-DCConverter Input)

Cathode (GND)

Ground(M3)

Sidewall(M3-AL)

Silicon Photodiodes

P+

N+

P+

Fig. 15: Photodiodes placed below patch antenna with fishnet pattern

commit message with a random challenge (R2 = r2P ) that isutilized by the tag to compute a Diffie-Hellman share (r1r2P ).The tag then applies a one-way function to this share andcalculates its response. This response is then verified on thereader side through a similar computation to authenticate thetag.

V. INTEGRATED PHOTO-VOLTAIC POWERING

The antenna array, when incorporated on the tag chip,occupies most of the die area. In this section, we describe howthe silicon under the antennas, along with an integrated DC-DC converter, are exploited to perform photo-voltaic poweringfor the tag.

A. Photodiodes

The CMOS technology used for the chip provides a DeepN-well structure, normally for increased isolation betweenanalog and digital circuits. This feature is utilized in theTHz-ID tag, where silicon photodiodes are built based on avertical stack of N+, P-well, Deep N-well and P-substrate,as shown in Fig. 15. As a result, three P-N junctions areformed, which maximize the absorption of incident light. Forchip compactness, an array of shunted photodiodes are placedboth beside and underneath the antennas. Correspondingly, thepatch radiators and the ground planes of the antennas areimplemented with a fishnet pattern (Fig. 15). A simulationtool based on a finite-difference time-domain (FDTD) method,Lumerical [20], is used to examine the hole size of thefishnet pattern. The simulation results in Fig. 16a assume that25% area of antenna are holes to allow light transmission(refereed as fill factor of holes henceforth), and show thatthe through-hole light transmission for hole size smaller than4 µm undergoes significant plasmonic and scattering loss. Onthe other hand, the hole size should remain a small fractionof the THz wavelength, so that the THz-field distribution overthe antenna is not affected. As a result, a hole size of 8 µm,which leads to a through-hole light transmission rate of 92%is selected. For larger effective illumination area, the fill factorof the holes should increase. That, however decreases theequivalent conductivity of the antenna metal layers, and lowers

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 9

0 2 4 6 8 10

0

20

40

60

80

100

Hole Size (m)

Tra

ns

mis

sio

n (

%)

101 100

Light Intensity

AL Layer

M3 Layer

Plasmonic Loss

(a)

0 10 20 30 40 50 60 70 80

0

10

20

30

40

Ra

dia

tio

n E

ffic

ien

cy

(%

)

Fill Factor of Light Windows (%)

Selected in

This THz-ID Tag

(b)

Fig. 16: (a) FDTD-simulated light (λ=700 nm) transmission through differenthole size. The cross-sectional view of intensity distribution for the hole size of8 µm is also shown. (b) Simulated antenna radiation efficiency with differenthole opening fill factor while keeping 8-µm hole size.

the radiation efficiency, as is shown in the HFSS simulationin Fig. 16b. In the tag chip, a fill factor of 25% is used, whichslightly degrades the antenna efficiency from 31% to 27%.

B. DC-DC Converter

This component is needed to convert the loaded photodiodeoutput voltage at about 0.3 V to the chip supply at 1 V.It consists of two converters (start-up and main converters)that are connected between VIN and VOUT,I in parallel,switching clock generators, and other small blocks for control(Fig. 17). When the converter is powered by the photodiodefrom the cold state, the start-up converter (Fig. 18a) is firstturned on and generates 3x up-converted voltage at VOUT,I .When VOUT,I exceeds 0.8 V, it triggers the main converter togenerate the 1 V output. If the main converter raises VOUT,Iover 1 V, the output controller is triggered and turns on theoutput switch that connects VOUT.I and VOUT , starting powersupply to load circuits. The output controller also provides areset signal (RST in Fig. 17) to load circuits so as to initializethem properly during start-up. RST is being asserted duringthe whole start-up process, and is de-asserted after the outputswitch is on and VOUT is stabilized at 1 V.

For cold start, the start-up converter always operates when-ever photodiode power is available, but after triggering themain converter, its switching frequency is minimized for min-imum power waste (Signal Slow in Fig. 17). According to post-layout simulation results, the switching frequency changesfrom 8 MHz to 16 kHz (around 500× frequency reduction) andthe waste from switching loss is also proportionally reduced.

1:3 Start-up

Converter

1:5 Main

Converter

VIN

VOUT,I > 0.8?

Main ClkGen

Slow

EnClk

VOUT

Y

VOUT,S

VOUT,I

Output

ControllerVOUT,I > 1?

VOUT,IY

RST

Fig. 17: Block diagram of the on-chip DC-DC converter.

VOUT,SVIN

CLK

CLK

1.8pF

CLK

CLK

500n60n

1μ 60n

(a)

VIN

CLK

CLKCLK

CLK

CLK CLK

CLK

CLK

VOUT

14.6pF

(180° Phase Shifted)

CLK

CLK

4μ 60n

4μ 60n

4μ 300n

4μ 300n

(b)

Fig. 18: Schematics of (a) DC-DC converter startup circuit and (b) main DC-DC converter.

The main converter (Fig. 18b) is optimized for the powerconversion of the peak system power, which can be estimatedduring the design time by simulation. It has a higher conver-sion ratio of 1:5 to provide high enough voltage and currentto the load. For efficient power conversion during operation, ituses transmission gate switches instead of cross-coupled onesfor better conductance, and most of the available capacitors forthe converters are allotted to the main converter. For stable andefficient power output, a feedback loop controls the switchingfrequency of the main converter, so that the photodiode outputvoltage VOUT stays at the maximum power point under thelight intensity that is capable of providing the peak systempower.

After the main converter’s operation is stabilized, VOUToutput switch is turned on to connect converter’s VOUT tothe supply voltage of other blocks. For regulating the outputvoltage at 1 V, another control loop is attached at VOUTfor excess output power from the converter to bypass theload. Design optimization specialized for the tag enables themain converter to achieve a simulated conversion efficiency of60% during peak power conversion, only using a tiny space(0.096 mm2) between two patch antennas .

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 10

EC

C C

ryp

tog

rap

hic

Pro

ces

so

r

DC-DC

Converter

Downlink

Circuitry

Tri-Feed

THz Patch

Antenna

1.3

mm

Photodiodes

1.2mm

Cut Line

Deb

ug

Pad

s

Fig. 19: Chip micrograph

VI. EXPERIMENTAL RESULTS

The tag chip is fabricated using a TSMC 65-nm bulk CMOSprocess. The micrograph of the chip is shown in Fig. 19. Thechip has an area of 1.3×1.2 mm2. The two rows of pads,which can be cut, are for debugging purpose. In our testing,the chip is mounted and wire-bonded on a PCB.

A. Measurement Setup

First, a custom-designed THz-ID reader is constructed, as isshown in Fig. 20a. It communicates with the chip at a distanceof 5 cm using two WR-3.4 horn antennas. The antennas areplaced in the way that their E-planes are orthogonal to eachother, in order to match the cross-polarizations of the THz-IDantennas (Fig. 3). For the reader-to-tag downlink, an amplifier-multiplier chain (AMC) from Virginia Diodes Inc. (VDI) isused, which converts a 10.9414-GHz input signal to a 20-dBm output at 262.5936 GHz. The input of the VDI AMC isOOK modulated by the 100-kbps data generated from a FPGAboard (XEM 7001). According to the Friis formula [21], thepower impinging on the THz-ID chip is about -5 dBm.

For the tag-to-reader uplink, a VDI spectrum analyzerextender (SAX) mixes the tag-backscattered signal with the48th harmonic of its 5.4632-GHz LO, and downconverts to358 MHz. The signal is then amplified by 32 dB and observedon a spectrum analyzer. To close the communication loop,the signal is also further downconverted to 1 MHz, amplifiedby 60 dB and bandpass filtered. Finally, an envelop detectorcascaded by a comparator recovers the 2-kbps data and feedsto the FPGA (Fig. 20a). Fig. 20b shows the photograph of thesetup. The THz-ID reader head also includes an illuminationsource, which consists of a CREE XP-L-V6 LED and a lensthat converge the light to ∼1 cm2 spot on the PCB. Thechip PCB is mounted on a rotational stage, which is used forthe beam-steering measurement. In the uplink and downlinkmodes, the tag consumes 13 µW of power; that includes 4 µWof static leakage power of the digital circuits. In the mostpower-hungry security mode, when the cryptographic proces-sor is running RO-TRNG and AES, the power consumptionrises to 21 µW.

B. Characterization of the Circuits

First, to characterize the 260-GHz backscatter module in abasic continuous-wave mode, the chip is externally poweredand clocked (at fLO=2 MHz) via the debugging pads. With theincident wave generated by the VDI AMC, a down-convertedspectrum shown in Fig. 21 is obtained from the VDI SAX.The tone at 358 MHz is the expected signal backscatteredby the THz-ID. It has a SNR of 36 dB at 1-kHz bandwidth,indicating the feasibility of an uplink with the designed 2-kbps data rate. The tone at 362 MHz is the upper-sidebandimage due to the limited image rejection (∼10 dB) of theSSB mixer in the tag. The central tone at 360 MHz is thereader-generated 262.5-GHz signal directly reflected from thechip and its surroundings. Note that although this signal isalready attenuated by ∼25 dB due to the cross-polarizationof the reader antennas, it is still >30 dB higher than thetag-backscattered signal in Fig. 21. That in turn justifies ourbackscatter scheme using cross-polarization and frequencyshifting. The scheme ensures that the phase noise of thedirectly-reflected signal is below the reader’s thermal noisefloor, hence does not degrade the uplink SNR. The schemealso avoids the saturation of the reader’s baseband amplifiercaused by the undesired reflected tone with large power.

Then, with OOK modulation to the VDI AMC, the tagdownlink output is measured via a debugging pad. Pulse-widthmodulation is adopted for the encoding of the system, whereduty cycle <45% represents bit 0 and >55% represents bit 1.In our measurement setup, the reader uses 40% duty cycle forbit 0 and 75% for bit 1. The results in Fig. 22 indicate thatthe tag downlink correctly recovers the original data createdby the FPGA in the THz reader (Fig. 20a). To achieve thegate bias of the downlink MOSFET detector, ambient lightingis found to be sufficient in the testing.

Next, we test the beam-steering capability of the THz-IDchip. Note that it is different from conventional beam-steeringof phased arrays, due to the unique back-scattering operationof the chip, and the co-location of the reader’s transmitter andreceiver. Shown in Fig. 23a, the goal of the beam-steeringof this tag is to ensure that when the chip does not face thereader perpendicularly, its backscattered wave can still be re-directed towards the reader. Fig. 23a indicates that, with achip tilting angle of θ and on-chip antenna spacing of λ/2, thefollowing phase gradient (in degree) should be applied in orderto compensate the total propagation-path difference related tothe waves handled by the two patch antennas:

ϕA − ϕB = 2 · (λ2

sin θ) · 360

λ= (sin θ) · 360 (4)

This is verified in our experiment, where the LO phaseof each THz SSB mixer is digitally controlled by the on-chip processor. Fig. 23b shows the backscatter-wave power,which is received by the reader in the measurement, at varyingchip tilting angle θ. Two tag phase-gradient settings requestedby the reader, ϕA=ϕB and ϕA-ϕB=180, are tested. Themeasured peak responses of the reader occur at θ=0 andθ=30, respectively, which well agree with (4). This alsoshows that the maximum beam-steering angle (in both azimuthand elevation directions) is ±30. It should be noted here that,

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 11

0 1

100kbps

10.9414GHz

AM Source

CMOS THz-ID

WR-3.4 Cross-

Polarized Horn Antennas (25dBi)

VREF

+

-

358MHz

1MHz

VDI-SAX

Mixer

BPF

262.5936

GHz

Envelop

Detector

Amplifier

(32dB)

Amplifier

(60dB) Debugging

VDD Buffer

VDI-AMC-573

FPGA

(XEM 7001)

Oscilloscope

Spectrum

Analyzer

357MHz Source

5.4632GHz Source

IF

LO

5cm

260-GHz Reader RX 260-GHz Reader TX

(a)

VDI SAX

VDI-AMC

Horn Antennas

THz-ID Chip

THz Reader

Head with

LED Light

Source

3D-

Printed

Holder

LED

Torch

Horn

Antennas

(b)

Fig. 20: (a) Diagram of the testing setup. Note that when light powering is used, the debugging VDD is disconnected. (b) Photos of the testing up with andwithout a LED torch for photovoltaic powering of the CMOS chip. The power electronics inside the LED torch, which generates large switching noise, isby-passed in the setup.

PCB-Reflected

Carrier

Backscattered

Signal

SNR=36dB

@ RBW=1kHz

Fig. 21: Measured spectrum of the backscattered signal

Data Sent by the THz Reader

Data Recovered by the Tag

Fig. 22: Measured downlink wavefrom from the tag.

φA=φB

θ

d λ=

sinθ 2

THz-ID

Reader

φA φB

φA

φB

φA=φB φA=φB+2d

=φB+sinθ

360o

λ360

o.

(a)

0 60-85

-75

-65

-55

Po

wer

Receiv

ed

by R

ead

er

(dB

m)

20

Tilt Angle

40

(Degree)

Setting 1 Setting 2

θ

(b)

Fig. 23: (a) Phase-shifting (ϕA-ϕB) conditions in the tag to ensure thatthe backscattered wave points to the reader when the tag is tilted by θ.(b) Measured backscattered-wave power, which is received by the reader, atdifferent chip tilting angle θ. Here, two digital settings of ϕA-ϕB are applied.

when an antenna is tilted, the effective aperture decreases by afactor of cos θ. At θ=30, ∼1.2 dB two-way power loss shouldoccur. However, in the measurements we received almost thesame peak power in both settings. This can be attributed toeither a better alignment in Setting 2 or measurement error.

We also verified the protocol and the cryptographic functionwith an external power and the tag internal clock (Fig. 24a).

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 12

-5

0

5

10

Do

wn

lin

k D

ata

0.00 0.02 0.04 0.06-5

0

5

10

Up

lin

k D

ata

9.2 9.4 9.6Time (s)

Wakeup

Beacon

Direction

Response

Direction

Confirmation

Authentication

Request

Key

Generation

Challenge

Response

(a)

THz Reader Downlink Data

Downlink Data at the Tag

THz Reader Uplink Data

Uplink Data at the Tag

(b)

THz Reader Downlink Data

Downlink Data at the Tag

Uplink Data at the Tag

THz Reader Uplink Data

(c)

Fig. 24: (a) Measured downlink and uplink data in the protocol. Zoom-inviews of dotted regions representing the phases of (b) direction response andconfirmation, and (c) challenge and response message.

When the reader receives the tag’s beacon message, the FPGAstarts a feedback loop to request a change of uplink beamangle until the SNR is maximized. The measured waveformsassociated with this operation are shown in Fig. 24b. Then thereader sends a trigger to the chip to start the authenticationprocess described in Section IV. Fig. 24c shows the measuredwaveforms of the challenge-response protocol that the tagtakes towards the end of the authentication process, in order toidentify itself to the valid reader. In Fig. 24b, when THz readeris transmitting data, tag’s downlink circuit recovers exact samedata and during idle time random output pulses are observed,as explained in Section III-C. Due to the preamble validationin the processor, those random pulses are rejected.

Lastly, with external LED illumination and photodiodepowering, the time-domain behavior of the DC-DC converter,measured via the tag’s power supply pads, is shown in

Start-up

converter ON

Main converter enabled

Output switch ON to start

to supply other blocks

VOUT (Internal)

VOUT (External)

Output regulated at ~1V

RFID operation starts

(a)

DC-DC Converter Output

THz Reader Uplink Data

Main converter

enabled

Start-up

converter ON

Switch applied for

circuit operations

Tag Wakeup

Beacon

(b)

Fig. 25: (a) Measured startup behavior of the DC-DC converter. (b) Measuredstartup behavior of THz-ID with optical powering.

Fig. 25a. The first waveform presents the operations of theDC-DC converter, where the first peak shows the operationof the start-up converter, and the second peak shows that themain converter is activated once the internal voltage of thecircuit rises to 0.8 V. Subsequently, the output switch loadsthe main converter output VOUT (external) with other circuitblocks of the tag, which is shown by the second waveform.The high-frequency fluctuations on VOUT lines after the outputvoltage reaches ∼ 1 V indicates that the on-chip processor isactivated. In Fig. 25b, the chip is entirely power-autonomousand interrogated by the THz reader. It can be seen that, whenthe converter-startup is completed, the on-chip processor sendsa tag-wakeup beacon signal through its 260-GHz backscatteruplink, and the signal is successfully received and recovered byour reader. Since the downlink amplifier consists of transistorsoperating in the sub-threshold regime, the large photoelectriceffect causes bias drift of the amplifier and excessive noise,which prevents the completion of the entire security protocolin the test. The static current of the processor also increaseswith the illumination. In the future development iterations, weshould be able to optically power the complete protocol byenclosing the downlink and processor circuitry with a coverformed by the Al-pad layer and sidewalls formed by M1-to-Alstack.

VII. CONCLUSIONS

In this paper, we demonstrate a new application of THzCMOS electronics, which utilizes its advantages in compact

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 13

size and packageless chip integration. We also show thatsilicon THz transceivers, which are long considered to bepower hungry, can be applied in ultra-low-power systems, if abackscattering communication scheme is adopted. Meanwhile,our work demonstrates the feasibility of integrating asym-metric cryptography, such as elliptic-curve encryption, on apassive tag. A comparison of our work with the prior state-of-the-arts is given in TABLE I. Our presented tag is built entirelyon a low-cost CMOS chip, and is around 3× smaller than thesmallest package-less, far-field chip reported previously [6]. Italso offers multi-antenna beam-steering functionality for thefirst time in RFIDs. Compared to [7], the asymmetric public-key cryptography provides higher-level security, and makesthe THz-ID tag suitable for privacy-sensitive applications.TABLE II compares the proposed ECC hardware acceleratorwith prior work implementing prime-field ECC at a 128-bitsecurity level. The proposed design consumes the least energyper ECSM and occupies minimum normalized area.

The presented work demonstrates the feasibility of securityID tags with ultra-small size and cost, which is expected toempower a wide range of new applications in manufacturing,logistics, anti-counterfeiting, and so on. To fully make theseapplications practical, a few more technologies should bedeveloped. For example, to allow for embedding of the taginside opaque materials, energy harvesting directly from theTHz wave is desired. That requires high-speed rectifier devicesin CMOS process. To this end, the poly-gate-separate Schottkydiodes in CMOS, which have ∼2-THz cutoff frequency andare used in THz imaging [24], could possibly meet the aboveneeds. Secondly, although the size and cost requirements forthe THz-ID reader, compared to the tags, are much morerelaxed, it is still highly preferred that the reader front-end isimplemented using silicon integrated circuits. Rapid advancesare being made in this area. For example, in [25], the 200-to-255-GHz power amplifier using 130-nm SiGe BiCMOSprocess (fmax≈500 GHz) is already capable of generating20 mW of power, which is only 7 dB away from the VDIAMC used in our tag reader. In light of recent developments ofhigh-speed and high-power SiGe and CMOS processes [26]–[29] with up to 720-GHz fmax and up to 7.1-V breakdownvoltage, achieving radiation power of 100 mW in the sub-THzregime is no longer unimaginable.

ACKNOWLEDGMENT

The authors acknowledge Virginia Diodes Inc. (VDI) fortheir generous support of some of the testing instruments. Wethank Prof. Donhee Ham and Dr. Houk Jang at Harvard Uni-versity, Prof. Tomas Palacios, Prof. Nicholas Fang and XinhaoLi at MIT for providing assistance during our experiments.We are also grateful for Dr. Jenshan Lin at National ScienceFoundation for funding this project.

APPENDIX: NOISE VOLTAGE OF AN OPEN-CIRCUITPHOTODIODE UNDER ILLUMINATION

In the downlink THz MOSFET detector (Fig. 10), an open-circuit photodiode under illumination is used to provide thegate bias of the transistor. The net output current of the

photodiode, although is zero, should be treated as the sumof two opposite current flows [30]. One is the photocurrent Ipgenerated by the illumination, and the other is the diffusioncurrent Id due to the forward bias of the diode:

Id = −Ip = I0(eV0Vt − 1), (5)

where I0 is the reverse saturation current of the p-n junction,Vt is the thermal voltage (Vt=kT /q≈26 mV at 300 K), and V0is the open-circuit photodiode voltage. The respective noisefluctuations associated with the above currents are uncorre-lated, so the total equivalent noise current power spectraldensity of the device is [30], [31]:

i2n/∆f = 4q(|Ip|+ I0) ≈ 4q|Ip|. (6)

The open-circuit noise voltage of the photodiode is thenconsidered to be the product of (6) and the diode differentialresistance at the bias (Rd=Vt/|Ip|):

v2n = i2n·R2d = 4q|Ip|·

(Vt|Ip|

)2

∆f = 4qV 2t

|Ip|∆f = 4kTRd∆f

(7)Interestingly, the generated noise is the same as thermal noiseof a resistor equal to Rd of the photodiode, and decreases withlarger illumination. Hence, its noise contribution to the outputnoise voltage of the MOSFET detector in Fig. 10 is:

v2n,det = g2m · v2n · r2ds = g2mr2ds · 4kTRd∆f, (8)

where gm and rds are the transconductance and output resis-tance of the MOSFET. Note that (8) is much smaller than theMOSFET’s own channel thermal noise (v2n,ch = 4kTrds∆f ):for the MOSFET biased in the triode mode (Fig. 10), thesimulated gm and rds are 1.4 µS and 7.7 kΩ, respectively, andIp in normal tag operation is ∼0.1 µA (hence Rd≈260 kΩ).Therefore, vn,ch is ∼11 nV/Hz1/2, while vn,det in (8) is∼0.7 nV/Hz1/2.

REFERENCES

[1] R. Want, “An Introduction to RFID Technology,” IEEE PervasiveComputing, no. January-March, pp. 25–33, 2006.

[2] G. Swamy and S. Sarma, White Paper: Manufacturing Cost Simulationsfor Low Cost RFID Systems. MIT Auto-ID Center, 2003.

[3] H. Pristauz, “RFID Chip Assembly for 0.1 Cents?” OnBoard Technol-ogy, no. September, pp. 46–49, 2006.

[4] L.-X. Chuo, Y. Shi, Z. Luo, N. Chiotellis, Z. Foo, G. Kim, Y. Kim, A. Gr-bic, D. Wentzloff, H.-S. Kim, and D. Blaauw, “A 915MHz AsymmetricRadio Using Q-Enhanced Amplifier for a Fully Integrated 3x3x3mmˆ3Wireless Sensor Node with 20m Non-Line-of-Sight Communication,” inIEEE International Solid-State Circuits Conference (ISSCC), 2017, pp.132–134.

[5] B. Zhao, N. C. Kuo, B. Liu, Y. A. Li, L. Lotti, and A. M. Niknejad, “A5.8GHz Power-Harvesting 116µmx116µm “Dielet” Near-Field Radiowith On-Chip Coil Antenna,” in IEEE International Solid-State CircuitsConference (ISSCC), 2018, pp. 456–458.

[6] M. Tabesh, M. Rangwala, A. Niknejad, and A. Arbabian, “A Power-Harvesting Pad-Less mm-Sized 24/60GHz Passive Radio with On-ChipAntennas,” in IEEE Symposium of Very-Large-Scale Integrated Circuits(VLSI), 2014.

[7] C. Juvekar, H.-M. Lee, J. Kwong, and A. Chandrakasan, “A Keccak-Based Wireless Authentication Tag with per-Query Key Update andPower-Glitch Attack Countermeasures,” in IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 290–292.

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 14

TABLE I: SUMMARY OF THE THZ-ID PERFORMANCE AND COMPARISON WITH OTHER STATE-OF-THE-ART RFIDS IN CMOS

References CMOSProcess

CarrierFreq. (GHz) Modulation Data Rate Peak

Power Security Range Beam-Steering

Area(mm2)

This Work 65 nm 260 PWM 100%ASK

DL: 100kbpsUL: 2kbps 21µW Yes (Elliptic

Curve) 5cm Yes 1.6

[4]†ISSCC’17 180 nm 0.915 PPM DL: 62.5kbps

UL: 30.3kbps 2mW No 20m No 9†

[5]ISSCC’18 65 nm 5.8 DL: <4% ASK

UL: HIMILDL: 5MbpsUL: 4kbps 10µW No 1mm No 0.01

[6]VLSI’14 65 nm DL: 24

UL: 60DL: 75% ASK

UL: PPMDL: 6.5MbpsUL: 1.2Mbps 11mW‡ No 50cm No 4.4

[7]§ISSCC’16 130nm 0.433 DL:PPM

UL:PWM 125kbps 16µWYes

(Symmetric) 5mm No 64§

†Assembly of multiple functional layers (photo-voltaic powering, battery, antenna, etc.) is used. ‡The calculated value in [4] is cited.§PCB-level components including off-chip coupler are required.

TABLE II: COMPARISON OF ELLIPTIC CURVE HARDWARE ACCELERATORS

Reference CMOSProcess

TechnologyNormalized Area

CycleCount

ECSMEnergy

[22]CRASH’05 350 nm 31kGE 1.1M 550µJ

[19]CHES’15 130 nm 33kGE 811.2k 56µJ

[23]ISSCC’18 65 nm 65.5kGE+ 4kB

SRAM 496k 17.6µJ

This Work 65 nm 25kGE 650k 14.4µJ

[8] T. Chi, H. Wang, M.-Y. Huang, F. F. Dai, and H. Wang, “A Bidirec-tional Lens-Free Digital-Bit-In/-Out 0.57mmˆ2 Terahertz Nano-Radioin CMOS with 49.3mW Peak Power Consumption Supporting 50cmInternet-of-Things Communication,” in IEEE Custom Integrated CircuitsConference (CICC), 2017.

[9] M. I. Ibrahim, M. I. W. Khan, C. S. Juvekar, W. Jung, R. T. Yazicigil,A. P. Chandrakasan, and R. Han, “THzID: A 1.6mmˆ2 Package-LessCryptographic Identification Tag with Backscattering and Beam-Steeringat 260GHz,” in IEEE Intl. Solid-State Circuits Conference (ISSCC),2020, pp. 24–26.

[10] J. Hermans, R. Peeters, and C. Onete, “Efficient, Secure, Private Dis-tance Bounding without Key Updates,” in Proc. 6th ACM Conf.SecurityPrivacy Wireless Mobile Network, 2013, pp. 207–218.

[11] C. Balanis, Antenna Theory, Third Edition. Wiley-Interscience, 2005.[12] “High Frequency Structure Simulator (HFSS) User Guide.” [Online].

Available: http://www.ansys.com/[13] C. Wang and R. Han, “Dual-Terahertz-Comb Spectrometer on CMOS

for Rapid, Wide-Range Gas Detection with Absolute Specificity,” IEEEJournal of Solid-State Circuits, vol. 52, no. 12, pp. 3361–3372, 2017.

[14] E. Ojefors, U. R. Pfeiffer, A. Lisauskas, and H. G. Roskos, “A 0.65 THzFocal-Plane Array in a Quarter-Micron CMOS Process Technology,”IEEE Journal of Solid State Circuits, vol. 44, no. 7, pp. 1968–1976,2009.

[15] M. I. W. Khan, S. Kim, D. W. Park, H. J. Kim, S. K. Han, and S. G. Lee,“Nonlinear Analysis of Nonresonant THz Response of MOSFET andImplementation of a High-Responsivity Cross-Coupled THz Detector,”IEEE Transactions on Terahertz Science and Technology, vol. 8, no. 1,pp. 108–120, 2018.

[16] R. Peeters and J. Hermans, “Wide strong private rfid identification basedon zero-knowledge,” IACR Cryptology ePrint Archive, vol. 2012, p. 389,2012.

[17] P. L. Montgomery, “Speeding the pollard and elliptic curve methods offactorization,” Mathematics of computation, vol. 48, no. 177, pp. 243–264, 1987.

[18] M. Joye and S.-M. Yen, “The montgomery powering ladder,” in Inter-national workshop on cryptographic hardware and embedded systems.Springer, 2002, pp. 291–302.

[19] M. Hutter, J. Schilling, P. Schwabe, and W. Wieser, “NaCl’s Crypto boxin Hardware,” in Intl. Workshop on Cryptographic Hardware andEmbedded Systems (CHES), Saint-Malo, France, 2015, pp. 81–101.

[20] Lumerical, “FDTD Product Reference Manual.” [Online]. Available:www.lumerical.com

[21] H. T. Friis, “A Note on a Simple Transmission Formula,” Proceedingsof the IRE and Waves and Electrons, vol. 34, no. 5, pp. 254–256, 1946.

[22] J. Wolkerstorfer, “Scaling ECC Hardware to a Minimum,” in Cryp-tographic Advances in Secure Hardware (CRASH), Leuven, Belgium,2005, pp. 207–214.

[23] U. Banerjee, C. Juvekar, A. Wright, A. Arvind, and A. P. Chandrakasan,“An Energy-Efficient Reconfigurable DTLS Cryptographic Engine forEnd-to-End Security in IoT Applications,” in IEEE International Solid-State Circuits Conference. San Francisco, CA: IEEE, 2018.

[24] R. Han, Y. Zhang, Y. Kim, D. Y. Kim, H. Shichijo, E. Afshari, and K. K.O, “Active terahertz imaging using schottky diodes in CMOS: Array and860-GHz pixel,” IEEE Journal of Solid-State Circuits, vol. 48, no. 10,pp. 2296–2308, 2013.

[25] M. H. Eissa and D. Kissinger, “A 13.5dBm Fully Integrated 200-to-255GHz Power Amplifier with a 4-Way Power Combiner in SiGe:C BiC-MOS,” in IEEE International Solid-state Circuits Conference (ISSCC).San Francisco, CA: IEEE, 2019, pp. 82–84.

[26] B. Heinemann, H. Rucker, R. Barth, F. Barwolf, J. Drews, G. G.Fischer, A. Fox, O. Fursenko, T. Grabolla, F. Herzel, J. Katzer, J. Korn,A. Kruger, P. Kulse, T. Lenke, M. Lisker, S. Marschmeyer, A. Scheit,D. Schmidt, J. Schmidt, M. A. Schubert, A. Trusch, C. Wipf, andD. Wolansky, “SiGe HBT with fT/fmax of 505 GHz/720 GHz,” in IEEEInternational Electron Device Meeting, San Francisco, CA, 2016, pp.51–54.

[27] S. N. Ong, S. Lehmann, W. H. Chow, C. Zhang, C. Schippel, L. H. Chan,Y. Andee, M. Hauschildt, K. K. Tan, J. Watts, C. K. Lim, A. Divay,J. S. Wong, Z. Zhao, M. Govindarajan, C. Schwan, A. Huschka,A. Bcllaouar, W. Loo, J. Mazurier, C. Grass, R. Taylor, K. W. Chew,S. Embabi, G. Workman, A. Pakfar, S. Morvan, K. Sundaram, M. T.Lau, B. Rice, and D. Harame, “A 22nm FDSOI Technology Optimizedfor RF/mmWave Applications,” in IEEE Radio Frequency IntegratedCircuits Symposium, 2018.

[28] H. Lee, S. Rami, S. Ravikumar, V. Neeli, K. Phoa, B. Sell, and Y. Zhang,“Intel 22nm FinFET (22FFL) Process Technology for RF and mmWaveApplications and Circuit Design Optimization for FinFET Technology,”in 2018 IEEE International Electron Devices Meeting (IEDM). SanFrancisco, CA: IEEE, 2018, pp. 316–319.

[29] H. J. Lee, S. Morarka, S. Rami, Q. Yu, M. Weiss, G. Liu, M. Armstrong,C.-Y. Su, D. Ali, B. Sell, and Y. Zhang, “Implementation of HighPower RF Devices with Hybrid Workfunction and OxideThickness in22nm Low-Power FinFET Technology,” in IEEE International ElectronDevices Meetings (IEDM), San Francisco, CA, 2019, pp. 610–613.

[30] A. Van Der Ziel, “Noise in Solid-State Devices and Lasers,” Proceedingsof the IEEE, vol. 58, no. 8, pp. 1178–1206, 1970.

[31] U. F. Gianola, “Photovoltaic Noise in Silicon Broad Area p-n Junctions,”Journal of Applied Physics, vol. 27, no. 1, pp. 51–54, 1956.

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 15

Muhammad Ibrahim Wasiq Khan (S’17) re-ceived the B.E. degree in electrical engineeringfrom National University of Science and Technology(NUST), Islamabad, Pakistan in 2012, with highesthonors and Rector’s bronze medal. He receivedM.Sc. degree in electrical engineering from Ko-rea Advanced Institute of Science and Technology(KAIST), Daejeon, South Korea in 2016, where heworked on THz detectors and THz imaging systemsbased on CMOS technology. Currently, he is a Ph.D.candidate at the Electrical Engineering and Com-

puter Science (EECS) department at Massachusetts Institute of Technology(MIT). He is working on CMOS based THz identification tags and THzenergy harvesting systems. His research interests include mm-wave and THzintegrated wireless systems.

Mohamed I. Ibrahim (S’15) received the B.Sc.(with honors) and M.Sc. degrees in electrical en-gineering from Ain Shams University, Cairo, Egypt,in 2012 and 2016, respectively. From 2012 to 2016,he was teaching and research assistant at the sameUniversity. During this period, he was developingmetamaterial inspired antennas and microwave pas-sive structures. Since September 2016, he has beena graduate Ph.D. candidate at the Electrical Engi-neering and Computer Science (EECS) departmentat Massachusetts Institute of Technology (MIT). He

is working on CMOS integrated quantum enhanced sensing and informationprocessing systems, and terahertz wireless systems. His research interestsinclude RF integrated circuit design, microwave passive planar structures, andnovel electromagnetic materials and devices.

Chiraag Juvekar Chiraag Juvekar (S’12-M’18) re-ceived the B.Tech and M.Tech degrees in electricalengineering from the Indian institute of TechnologyBombay, Mumbai, India, in 2012. He received thePh.D. and S.M. degrees in Electrical Engineeringand Computer Science at the Massachusetts Insti-tute of Technology, Cambridge, in 2014 and 2018,respectively.

In 2014, he worked in the Embedded ProcessingLab in Texas Instruments, Dallas, TX, designingauthentication circuits using emerging memories. He

is currently a Hardware Security Architect and Researcher with the SecurityCenter of Excellence at Analog Devices, Boston, MA. His research focuses onlow power system design, hardware security and neural network acceleration.Mr. Juvekar was a recipient of the MIT Presidential Fellowship in 2012 and theQualcomm Innovation Fellowship in 2016. He is a recipient of the ChorafasFoundataion Award for 2018 and the 2018 Jin-Au Kong Award for the BestPhD Theses in Electrical Engineering at MIT.

Wanyeong Jung (S’13-M’18) received his B.S. de-gree from Seoul National University, Seoul, Korea,in 2012 and the M.S. and Ph.D. degree in electricalengineering from the University of Michigan, AnnArbor, MI, USA, in 2014 and 2017, respectively. Hewas a Research Intern with the NVIDIA Research,Austin, TX, USA, in 2016. From 2017 to 2019, hewas a Postdoctoral Associate with the MicrosystemsTechnology Laboratories in the Massachusetts Insti-tute of Technology, Cambridge, MA, USA. Since2019, he has been an Assistant Professor with the

School of Electrical Engineering, Korea Advanced Institute of Science andTechnology, Daejeon, Korea. His current research interests include low-powercircuits and systems, energy-efficient edge computing, and Internet of Things(IoT).

Rabia Tugce Yazicigil received the B.S. degree inElectronics Engineering from Sabanci University in2009, the M.S. degree in Electrical and ElectronicsEngineering from Ecole Polytechnique Federale deLausanne (EPFL) in 2011, and the Ph.D. degree inElectrical Engineering from Columbia University in2016. She was a Postdoctoral Research Associatein the EECS Department of MIT from 2016 to2018. She is currently an Assistant Professor ofElectrical and Computer Engineering Department atBoston University and a Visiting Scholar at MIT. Her

research interests lie at the interface of integrated circuits, signal processing,security, bio-sensing, and wireless communications to innovate system-levelsolutions for future energy-constrained applications. She is the recipient ofa number of awards, including the “Electrical Engineering CollaborativeResearch Award” for her PhD research on Compressive Sampling Applicationsin Rapid RF Spectrum Sensing (2016), second place at the Bell Labs Future XDays Student Research Competition (2015), Analog Devices Inc. outstandingstudent designer award (2015), and 2014 Millman Teaching Assistant Awardof Columbia University. She served as the Vice Chair of the Rising Stars 2020workshop at the IEEE International Solid-State Circuits Conference (ISSCC)and she is member of the 2015 MIT EECS Rising Stars cohort. She alsoserves on the Technical Program Committee (TPC) of IEEE ISSCC and TPCof IEEE European Solid-State Circuits Conference (ESSCIRC).

Anantha P. Chandrakasan received the B.S, M.S.and Ph.D. degrees in Electrical Engineering andComputer Sciences from the University of Cali-fornia, Berkeley, in 1989, 1990, and 1994 respec-tively. Since September 1994, he has been with theMassachusetts Institute of Technology, Cambridge,where he is currently the Vannevar Bush Professorof Electrical Engineering and Computer Science.

He was a co-recipient of several awards includingthe 2007 ISSCC Beatrice Winner Award for Edito-rial Excellence and the ISSCC Jack Kilby Award

for Outstanding Student Paper (2007, 2008, 2009). He received the 2009Semiconductor Industry Association (SIA) University Researcher Award andthe 2013 IEEE Donald O. Pederson Award in Solid-State Circuits, an honorarydoctorate from KU Leuven in 2016, the UC Berkeley EE DistinguishedAlumni Award in 2017, and the 2019 IEEE Solid-State Circuits SocietyDistinguished Service Award. In 2015 he was elected to the National Academyof Engineering and in 2019 he was elected to the American Academy of Arts& Sciences

His research interests include ultra-low-power circuit and system design,energy harvesting, energy efficient RF circuits, and hardware security. He is aco-author of Low Power Digital CMOS Design (Kluwer Academic Publishers,1995), Digital Integrated Circuits (Pearson Prentice-Hall, 2003, 2nd edition),and Sub-threshold Design for Ultra-Low Power Systems (Springer 2006).

He is an IEEE Fellow. He has served in various roles for the IEEEISSCC including Program Chair, Signal Processing Sub-committee Chair, andTechnology Directions Sub-committee Chair. He served as the ConferenceChair of ISSCC from 2010 till 2018. He serves as the Senior TechnicalAdvisor to the Conference starting ISSCC 2019. He was the Director ofthe MIT Microsystems Technology Laboratories from 2006 to 2011. FromJuly 2011 - June 2017, he was head of the MIT Department of ElectricalEngineering and Computer Science. Since July 2017, he has been Dean ofthe MIT School of Engineering.

ACCEPTED TO IEEE JOURNAL OF SOLID-STATE CIRCUITS 16

Ruonan Han (S’10-M’14-SM’19) received theB.Sc. degree in microelectronics from Fudan Univer-sity in 2007, the M.Sc. degree in electrical engineer-ing from the University of Florida in 2009, and thePh.D. degree in electrical and computer engineeringfrom Cornell University in 2014. He is currently anassociate professor with the Department of ElectricalEngineering and Computer Science, MassachusettsInstitute of Technology, Cambridge, MA, USA. Hiscurrent research interests include microelectroniccircuits and systems operating at millimeter-wave

and terahertz frequencies. He was a recipient of the Cornell ECE Director’sPh.D. Thesis Research Award, Cornell ECE Innovation Award, and twoBest Student Paper Awards of the IEEE Radio-Frequency Integrated CircuitsSymposium (2012 and 2017). He was also recipient of the IEEE MicrowaveTheory and Techniques Society (MTT-S) Graduate Fellowship Award, andthe IEEE Solid-State Circuits Society (SSC-S) Predoctoral AchievementAward. He has served as an associate editor of IEEE Transactions on Very-Large-Scale Integration System (2019∼), IEEE Transactions on QuantumEngineering (2020∼), a guest associate editor for IEEE Transactions onMicrowave Theory (2019) and Techniques, and also serves on the TechnicalProgram Committee (TPC) of IEEE RFIC Symposium and the 2019 SteeringCommittee and TPC of IEEE International Microwave Symposium. He isthe IEEE MTT-S Distinguished Lecturer (2020-2022). He is the winner ofthe Intel Outstanding Researcher Award (2019) and the National ScienceFoundation (NSF) CAREER Award (2017).