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CMOS Technology

9/22/2014 Slide No.1

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CMOS Process

9/22/2014 Slide No.2EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

Fig.2-1 Cross sectionof an n-well CMOSprocess

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A Modern CMOS Process

p-well n-well

p+

p-epi

SiO 2

AlCu

poly

n+

SiO 2

p+

gate-oxide

Tungsten

TiSi 2

Fig.2-2: Cross section of modern Dual-Well Trench-Isolated CMOS Process

9/22/2014 Slide No.3

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oxidation

optical mask

process step

photoresist coating photoresist removal (ashing)

spin, rinse, dry acid etch

photoresist

stepper exposure

development

Typical operations in a singlephotolithographic cycle (from [Fullman]).

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Photo-Lithographic Process

9/22/2014 Slide No.4EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGNFig.2-4 Typical operations in a single photolithographic cycle (from[Fullman99])

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Patterning of SiO2

Si-substrate

Si-substrate

(a) Silicon base material

(b) After oxidation and deposition of negative photoresist

(c) Stepper exposure

Photoresist SiO 2

UV-light

Patterned optical mask

Exposed resist

Si-substrate

Si-substrate

SiO 2

Si-substrate

Si-substrate

SiO 2

SiO 2

(d) After development and etching of resist, chemical or plasma etch of SiO 2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasma

etch

9/22/2014 Slide No.5EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

Fig.2-5 Process steps for patterning of SiO2

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CMOS Process at a Glance

Define active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

9/22/2014 Slide No.6EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

Fig.2-6 Simplified Process sequence for the

manufacturing of a n-dual-well CMOS circuit

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CMOS Process Walk-Through

9/22/2014 Slide No.8EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

(g) After polysilicon deposition and etch

poly(silicon)

(h) After n+ source/drain and p+ source/drain implants.These steps also dope the polysilicon.

p + n +

(i) After deposition of SiO2 insulator and contact hole etch

SiO 2

Fig.2.7 (contd.)

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CMOS Process Walk-Through

.

(k) After deposition of SiO2 insulator, etching of vias ,deposition and patterning of second layer of Al.

9/22/2014 Slide No.9EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

Al SiO 2

Al

(j) After deposition and patterning of first Al layer.

Fig.2.7 (contd.)

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Packaging Requirements

9/22/2014 Slide No.10

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Electrical: Low parasiticsMechanical: Reliable and robustThermal: Efficient heat removalEconomical: Cheap

Packaging Requirements

9/22/2014 Slide No.11EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

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Bonding Techniques

Lead Frame

Substrate

Die

Pad

Wire Bonding

9/22/2014 Slide No.12EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

Fig.2-11:

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Tape-Automated Bonding(TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Die

Solder BumpFilm + Pattern

Sprockethole

Polymer film

Leadframe

Testpads

9/22/2014 Slide No.13EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

Fig.2-12: Tape-Automated Bonding

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Flip-Chip Bonding

Solder bumps

Substrate

Die

Interconnect

layers

9/22/2014 Slide No.14EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

Fig.2-13: Flip-chip Bonding

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Package-to-BoardInterconnect

(a) Through-Hole Mounting (b) Surface Mount

9/22/2014 Slide No.15EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

Fig.2-14:Board-mounting Approaches

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Package Types

9/22/2014 Slide No.16EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

Fig.2-15: An overview of commonly usedpackage types: 1-Bare die; 2-DIP;3-PGA; 4-Small-outline IC; 5-Quad flat pack;6-PLCC; and 7-Leadless carrier.

1

2

3

4

6

5

7

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Package Parameters

9/22/2014 Slide No.17EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

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Multi-Chip Modules

9/22/2014 Slide No.18EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

Fig.2-17: Avionics processor module

Courtesy of Rockwell Collins, Inc.

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Your Questions,

if any , .

Thanks for your attention !!

9/22/2014 Slide No.19EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

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Circuit Under Design & itsLayout View

V DD V DD

V in V out

M 1

M 2

M 3

M 4

V out 2

9/22/2014 Slide No.20EEE C443 / EEE F313 / INSTR F313 ANALOG & DIGITAL VLSI DESIGN

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The Manufacturing Process

For a great tour through the IC manufacturing processand its different steps, checkhttp://www.fullman.com/semiconductors/semiconductors.html