CMOS Manufacturing Processbwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/... · p-epi SiO2 AlCu...
Transcript of CMOS Manufacturing Processbwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/... · p-epi SiO2 AlCu...
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Digital Integrated Circuits EE141Manufacturing Process
CMOSManufacturing
Process
Digital Integrated Circuits EE141Manufacturing Process
CMOS Process
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Digital Integrated Circuits EE141Manufacturing Process
A Modern CMOS Process
p-well n-well
p+
p-epi
SiO2
AlCu
poly
n+
SiO2
p+
gate-oxide
Tungsten
TiSi2
Dual-Well Trench-Isolated CMOS Process
Digital Integrated Circuits EE141Manufacturing Process
Circuit Under Design
This two-inverter circuit (of Figure 3.25 in the text) will bemanufactured in a twin-well process.
VDD VDD
Vin Vout
M1
M2
M3
M4
Vout2
3
Digital Integrated Circuits EE141Manufacturing Process
Circuit Layout
Digital Integrated Circuits EE141Manufacturing Process
The Manufacturing Process
For a great tour through the process and its different steps, checkhttp://www.fullman.com/semiconductors/semiconductors.html
http://bwrc.eecs.berkeley.edu/Classes/IcBook
For a complete walk-through of the process (64 steps), check theBook web-page
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Digital Integrated Circuits EE141Manufacturing Process
oxidation
opticalmask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single photolithographic cycle (from [Fullman]).
Photo-Lithographic Process
Digital Integrated Circuits EE141Manufacturing Process
Patterning of SiO2Si-substrate
Si-substrate Si-substrate
(a) Silicon base material
(b) After oxidation and depositionof negative photoresist
(c) Stepper exposure
PhotoresistSiO2
UV-lightPatternedoptical mask
Exposed resist
SiO2
Si-substrate
Si-substrate
Si-substrate
SiO2
SiO2
(d) After development and etching of resist,chemical or plasma etch of SiO2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Hardened resist
Chemical or plasmaetch
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Digital Integrated Circuits EE141Manufacturing Process
CMOS Process at a GlanceDefine active areasEtch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
Digital Integrated Circuits EE141Manufacturing Process
CMOS Process Walk-Through
p+
p-epi (a) Base material: p+ substrate with p-epi layer
p+
(c) After plasma etch of insulatingtrenches using the inverse of the active area mask
p+
p-epi SiO2
3SiN
4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)
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Digital Integrated Circuits EE141Manufacturing Process
CMOS Process Walk-ThroughSiO2
(d) After trench filling, CMPplanarization, and removal of sacrificial nitride
(e) After n-well and VTp adjust implants
n
(f) After p-well andVTn adjust implants
p
Digital Integrated Circuits EE141Manufacturing Process
CMOS Process Walk-Through
(g) After polysilicon depositionand etch
poly(silicon)
(h) After n+ source/drain andp+source/drain implants. These
p+n+
steps also dope the polysilicon.
(i) After deposition of SiO2insulator and contact hole etch.
SiO2
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Digital Integrated Circuits EE141Manufacturing Process
CMOS Process Walk-Through
(j) After deposition and patterning of first Al layer.
Al
(k) After deposition of SiO 2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.
AlSiO2
Digital Integrated Circuits EE141Manufacturing Process
Advanced Metalization
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Digital Integrated Circuits EE141Manufacturing Process
Advanced Metalization
Digital Integrated Circuits EE141Manufacturing Process
Jan M. Rabaey
Design Rules
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Digital Integrated Circuits EE141Manufacturing Process
3D Perspective
Polysilicon Aluminum
Digital Integrated Circuits EE141Manufacturing Process
Design Rules
� Interface between designer and process engineer
� Guidelines for constructing process masks� Unit dimension: Minimum line width
» scalable design rules: lambda parameter» absolute dimensions (micron rules)
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Digital Integrated Circuits EE141Manufacturing Process
CMOS Process Layers
Layer
PolysiliconMetal1
Metal2Contact To PolyContact To DiffusionVia
Well (p,n)
Active Area (n+,p+)
Color Representation
YellowGreen
RedBlueMagentaBlackBlackBlack
Select (p+,n+) Green
Digital Integrated Circuits EE141Manufacturing Process
Layers in 0.25 µm CMOS process
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Digital Integrated Circuits EE141Manufacturing Process
Intra-Layer Design Rules
Metal2 4
3
10
90
Well
Active3
3
Polysilicon2
2
Different PotentialSame Potential
Metal1 3
32
Contactor Via
Select2
or6
2Hole
Digital Integrated Circuits EE141Manufacturing Process
Transistor Layout
1
2
5
3
Tran
sist
or
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Digital Integrated Circuits EE141Manufacturing Process
Via’s and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
Digital Integrated Circuits EE141Manufacturing Process
Select Layer
1
3 3
2
2
2
WellSubstrate
Select3
5
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Digital Integrated Circuits EE141Manufacturing Process
CMOS Inverter Layout
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
Digital Integrated Circuits EE141Manufacturing Process
Layout Editor
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Digital Integrated Circuits EE141Manufacturing Process
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
Digital Integrated Circuits EE141Manufacturing Process
Sticks Diagram
1
3
In Out
VDD
GND
Stick diagram of inverter
• Dimensionless layout entities• Only topology is important• Final layout generated by
“compaction” program