CMOS LNA for wireless biomedical telemetry

R.L. Moreno and E.C. Rodrigues

Abstract: A low-noise amplifier (LNA) fabricated in a standard 0.35mm AMS CMOS process isdescribed. The LNA is part of a telemetry system which is part of a R&D project for biomedicalapplications. The goal is to build a low-power 174–230MHz RF transmitter–receiver suitable formeasuring blood pressure on a patient body. The low noise amplifier is composed of transistorsonly, which allows full integration on a standard CMOS process. The LNA has been measured tohave a noise figure of 2.6dB and a 21.7dB gain at 200MHz. The input IP3 is �12dBm.

1 Introduction

Wireless biomedical telemetry devices send medical datafrom patients to central monitoring points. CMOStechnology progress and the continuous reduction of devicesizes had made possible the implementation of integratedcircuits for wireless biomedical telemetry devices usingCMOS technology [1, 2].

In some biotelemetry applications it is necessary toprovide long-lasting continuous monitoring of physiologicalparameters such as blood pressure. These demands lead tothe requirement of sophisticated and totally integratedsystems. Long-lasting systems implanted in the human bodyrequire a reliable, small, cheap and unlimited supply system.Batteries do not show the best characteristics because oftheir lifetime limitations, and because of their power andchemical stability. Therefore a contactless power supply isnecessary for the implanted system and the best approach isan RF wireless power supply using inductive coupling [1].

The implementation of an implanted fully integrated RFbiotelemetry system to measure blood pressure poweredwith inductive coupling must also contain the RFtransmitter to transmit pressure information to an externalreceiver. The implementation presents some challenges,such as an integrated pressure sensor, an integratedmicroinductor for the transmitter, an integrated micro-inductor for the inductive system [7], and an integratedexternal receiver to be implemented in a portable system,such as a wrist watch.

The system under development shown in Fig. 1 has apiezoresistive pressure sensor of low offset voltage and lowdrift. It generates a voltage (VOS) proportional to appliedpressure [3]. The sensor is implemented with a postproces-sing technique employing CMOS technology [4]. The VOSsignal is converted to frequency in the conditioner circuit(VPIM).

The electronic interface presents a new signal condition-ing architecture for piezoresistive pressure sensors, based on

the requirements imposed by the wireless telemetry system.Additionally, the interface must present low powerconsumption and an output independent of the powersupply. Also, the interface must compensate temperaturecoefficients, allow offset cancellation, and provide sensitivityand signal cancellation adjustments [5, 6].

The signal is transmitted out of the patient’s body usingVPIM-AM modulation [6], selected owing to its low powerconsumption. The reception antenna, used to power thesystem, was implemented using electrodeposited microin-ductors on silicon [7]. The circuit receives external powerthrough an inductive coupling.

The signal from the implanted device is received by anexternal receiver (Fig. 1) currently under development [8].The LNA amplifies the weak signal from the antenna byintroducing as low noise as possible.

In wireless biomedical telemetry receivers with highdesign constraints the LNA design is critical because itshould provide enough gain to the low-power signals thatarrive at the antenna; it should not degrade the signal-to-noise ratio [8].

This work presents a low-noise amplifier, an essentialcomponent in the receiver, for wireless biomedical telemetryapplications in the 174–230MHz range [9].

2 Low-noise amplifier

Figure 2 shows the architecture of the two-stage push–pulllow-noise amplifier that was developed. The first stagesupplies the LNA direct gain and the second stage acts as abuffer to match a 50ohm load [10, 11].

Figure 2 shows a sinusoidal signal source Vin at the LNAinput. This source is not part of the integrated circuit and isused to simulate the signal captured by the antenna. Thereis also a 50ohm resistor Rs that represents the antennaimpedance. Capacitor CIN couples the signal to the input ofthe first stage, thus avoiding any change on the bias point.Capacitor COUT is used at the output to avoid change in thebias level of the second stage due to an external load.

The first stage (Fig. 2) is formed by transistors M1, M2(a push–pull amplifier) and transistor MIREF1 which actsas a current source. This amplifier uses the current reusemethod [7]. Similarly, the second stage is formed bytransistors MS1, MS2 and MIREF2.

The first amplifier stage has an operation pointguaranteed by the comparator circuit COMP1. The biascircuit (Fig. 2) adjusts the voltage level VINOP at theamplifier input (M1 and M2) to assure an operation point

R.L. Moreno is with the Microelectronics Group, Universidade Federal deItajub!a, Av. BPS 1303, Pinheirinho, Itajub!a, MG, 37500-903, Brazil

E.C. Rodrigues is with the Laboratory of Integrated Systems, PolytechnicSchool, University of S*ao Paulo, Brazil

E-mail: moreno@iee.efei.br

r IEE, 2005

IEE Proceedings online no. 20045132

doi:10.1049/ip-cds:20045132

Paper first received 26th May 2004 and in revised form 4th January 2005

IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5, October 2005 401

with the aid of a control performed by comparator COMP1(Fig. 3). This voltage is supplied by the Vref 2 circuit. Thegoal is to bias the amplifier at its highest gain point. Thevoltage reference Vref 1 provides the biasing of transistorMIREF1, thus establishing the current consumption of thefirst amplifier.

The bias point, on the high-gain region of the secondstage, is guaranteed by the DC level (VOUTOP ) at the outputof the first stage and by the action of comparator COMP2.This comparator controls the biasing of transistor MIREF2so that the DC level at the output of the second stagebecomes equal to Vref 3.

When compared with an amplifier having a transistor oftransconductance gm, the push–pull amplifier formed bytransistors M1 andM2 or MS1 andMS2 (Fig. 2) presents alarger transconductance gmM1

þ gmM2or gmMS1 þ gmMS2 [10].

Therefore the gain, for the same bias current, is larger. Asshown in Section 3, to obtain low-noise figure the inputamplifier must have a large transconductance.

3 Low-noise amplifier circuit

Figure 4 shows the complete LNA diagram, including thetwo stages and their biasing circuitry. The currents suppliedby transistors MIREF1 and MIREF2 are 3mA. Transis-tors MP1 and MN1 form a voltage divider that generatesthe MIREF1 bias voltage Vref 1.

The first-stage comparator Comp1 is formed by transis-tors MC1–MC4, MPOL1, MPOL2, MR1 and MR2(Fig. 4). Transistors MPOL1 and MPOL2 provide theinput voltage bias, while transistors MC1–MC4 form avoltage comparator (Comp1 in Fig. 2). The voltagecomparator sets the output voltage of the first stage to1.2V, which is provided by transistors MN3 and MP3(Vref2 in Fig. 4). Transistors MR1 and MR2 work asresistors to isolate the AC signal from the DC bias at theinput. The feedback path formed by comparator Comp1,transistors MPOL1, MPOL2, MR1 and MR2 controls thedrain current of transistor MIREF2.

The second-stage comparator Comp2 is formed bytransistors MOP1–MOP4, and MI1–MI4 (Fig. 4). The biassource Vref3, in Fig. 4 provides the DC output level (drainof transistors MS1 and MS2).

The feedback path formed by comparator Comp2controls the drain current of transistor MIREF2, assuringthe stability of the operating point of the second amplifier.

Resistor R3 and capacitor CB4 were included to increasethe phase margin of the second amplifier by reducingvariations on MIREF2 control voltage.

In this project each feedback was individually adjusted toprovide at least 451 of phase margin, enough to maintainthe stability of each amplifier.

Transistors CB1–CB8 implement capacitors used tocancel any noise oscillations that may occur at the referencesources.

Capacitors CIN and COUT avoid the influence of externalvoltages on the DC-bias point of the amplifiers in stages 1and 2, respectively.

4 Low-noise amplifier design

A noise system is shown on Fig. 5 [8, 12, 13]. The system tobe modelled is a common-source CMOS amplifier. In thiscase the noise sources of Fig. 5 can be modelled as [8, 12, 13]

V 2RS ¼ 4kTRSDf ð1Þ

V 2Rg ¼ 4kTRgDf ð2Þ

circuit to be implanted on patient’s body

transmittercircuit

PIM-AMto savebattery

conditioningcircuit

200 MHz

VOS

power supply

voltage-to-pulse

internalmodulationconverter

energytransmitter

circuit

mixeretc.

LNA

external receiver

internalvoltage

regulator

piezoresistive pressure sensor

VPIM

VPIM-AM

Fig. 1 Telemetry system under development

VCC VCCVCC

VCCMIREF1

M1

M2

Vin

RS

Vref1

Vref2

CB1

CIN

first stage

MS1

MS2

MIREF2

RL

Vref3comp2CB2

COUT

second stage

Vinop

Voutop

+−

comp1

bias

Fig. 2 Basic CMOS low-noise amplifier

first-stage input direct voltage first

-sta

ge o

utpu

t dire

ct v

olta

ge

operation point

Vinop

Voutop

Fig. 3 DC transfer characteristic of first amplifier stage

402 IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5, October 2005

V 2N ¼ 4kT go2C2

gs=gm ð3Þ

I2N ¼ 4kT ggm ð4Þ

gm ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2ID

mCox

2

WL

rð5Þ

o ¼ 2pf ð6Þwhere

k is Boltzmann’s constantT absolute temperatureDf bandwidth noiseRs 50-ohm resistanceRg series gate MOS resistance

V 2RS

noise generated by 50-ohm resistance

V 2N

induced gate MOS noise

I2N thermal noise in MOS transistor

Cgs MOS gate–source capacitance,

g constant in range 2–3 for short-channel MOSdevices

mCox process constantW MOS channel widthL MOS channel lengthID transistor bias current

Modern CMOS process provides a very low gate-sheetresistance. For this reason this the noise contribution is notsignificant [12, 14]. The influence of the gate noise can bereduced by the use of a parallel arrangement of transistorsM1, M2, MIREF1, MIREF2, MS2 and MS1 (Fig. 4).

Considering the frequency range of this amplifier,thermal noise is the most relevant one [15], and the inducedgate MOS noise is not significant.

Low-noise amplifiers are characterised in terms of theirnoise figure rather than input-referred noise. Noise figureNF is defined as the ratio of the input signal-to-noise ratioSNRIN to output signal-noise ratio SNROUT [12]. For theamplifier used on this LNA, and using the most relevantnoise sources, it can be shown that NF is given by [8]

NF ¼ 10 log10 1þ gRS gmM1

þ gmM2ð Þ

� �ð7Þ

where g is 2/3 for long-channel MOS devices and in the 2–3range for short-channel MOS devices.

To obtain the required value of noise figure a 3mA biascurrent IDMIREF 1 ¼ IDMIREF 2 ¼ 3mA and adopted. Thevalue of gm adopted allowed a gain of 21.7dB and a noisefigure of 3dB. Proper precautions were taken in the RFsignal interconnections. To avoid coupling noise betweenRF and biasing additional GND lines were used (Fig. 6).

0

0

0

MC1

MRI2

0

CB2

MOP4

0

CB4

MP0L1

CB1

MOP1

MI2

0

MOP3

CIN

CB5

Comp2

CB3

MS1bias

Vref1

Vout

R3

MI3

0

CB6

MC4

VCC

VCC

VCCVCC

VCCVCC

VCCVCC

VCC

VCC

VCC

VCCVCC

VCC

MP3

0

MP1

MR2 Vref2

Comp1

Vref3

0

MPOL2

MOP2

0

0

MC2

CB7

Vin

0

MC3

0

MN1

0

0

M1

0

MN3

MS2

CB8

MI4

MRI1MI10

MIREF2

0

M2

MR1

push−pull amp.2

push−pull amp.1

COUT

Vinop

Voutop

MIREF1

Fig. 4 Complete low-noise amplifier

Vin

RsRg noiseless

circuit

VoutVRS

2 VRg

2VN

2

_ + _ + _ +

IN2

++

__

Fig. 5 Small-signal noise model

IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5, October 2005 403

The whole project was developed using Mentor Graphicstools.

5 Experimental results

The circuit was fabricated using AMSs (Austria MikroSysteme) 0.35mm CMOS process with an area of1.67� 1.42mm2 (Fig. 7). To compose the layout, properprecautions were taken in the RF signal path. All RF signalconnections were made with metal 2 and to avoidundesirable coupling the RF signal was accompanied by alarger metal 1 connected to GND. Figure 8 shows the chipinside a sealed box, which was used to reduce environmentalinfluences.

To perform the characterisation of the circuit using testequipment, input and output matching were implementedusing external inductors.

The first test on a sample was intended to verify thecircuit operation. By using a spectral analyser it wasobserved that the output signal was at least 20dB largerthan the input signal when measured at 200MHz (LNAoperation frequency).

The input signal power ranged from �50 to �10dBm.Figure 9 shows the circuit output when excited by an input

signal of �38dBm. For any amplitude of the input signal,the output signal presents a single 200MHz line with theexpected gain.

The second test was applied to obtain the S-parametersusing a network analyser. The equipment was calibratedand the input signal level adjusted to �22dBm, since thisvalue does not cause any saturation at the output of theamplifier.

The S-parameters are used to represent transmission andreflection coefficients on two-port networks. They are usedto describe the behaviour of a system working at highfrequencies, where other parameters would be difficult toobtain; S11 represents input reflection, S22 output reflection,S21 direct gain and S12 reverse gain [14].

The S-parameters obtained by the network analyser arepresented in Figs. 10–13. At 199.625MHz, S21 (Fig. 10) isequal to 21.7dB and S11 (Fig. 11) to �9.3dB, thusindicating good input impedance matching. ParametersS12 (Fig. 12) is equal to �33.6dB and S22 (Fig. 13) to�5.3dB.

Figure 14 shows that the IP3 is equal to �12dBm. Toobtain this result two signals of frequency 194.0 and198.4MHz were applied at the input of the circuit.

The noise figure is shown in Fig. 15 (2.7dB at 200MHz).The results obtained demonstrate good correspondencewith the theoretical values.

Table 1 compares measured and simulated values. Themeasured S11 and S22 parameters are quite far from thesimulation results, partly caused by the matching circuit.

To date, just a few LNAs in CMOS working at 200MHzhave been reported [16, 19, 22], as presented in Table 2;other LNAs are presented in [10, 17, 18, 20, 21]. Although

feedback of RF signal implemented

on metal-3 layer

RFsignal

metal-2 layer connected to GND

Fig. 6 RF signal isolation using GND Lines

Fig. 7 Microphotograph of low-noise amplifier

VOUT

VCC

VIN

Fig. 8 Prototype and test board

cursor: Vin=−38.8dBm

Vout=−17.15dBm

Fig. 9 LNA response when excited by 200 MHz signal

404 IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5, October 2005

some were designed for higher frequencies, they are allincluded for comparison with this work in terms of noisefigure, IP3 and S-parameters. The noise figure of this work(2.7dB) is close to the lowest reported. The other results ofthis work are in the expected range. The presented CMOSLNA competes with other amplifiers without on-chipinductors or bipolar transistors [16, 17, 19].

At the running frequency of 200MHz, the measured NFwas close to the value predicted by simulations. Thesimulator (ACCUSIM by Mentor Graphicss) used theBSIM3V3-model parameters provided by AMSs, which isvery suitable for short-channel CMOS devices [23]. Thismodel has proved to be very suitable for this LNA since the

cursor30

20

10

0

c+21.69 dB

199.625 MHZdB

Fig. 10 S21 parameter

cursor

−10

−5

0

c

−9.24 dB199.625 MHZ

dB

Fig. 11 S11 parameter

cursor

−10

−20

−30

0 −33.56 dB199.625 MHZ

dB

Fig. 12 S12 parameter

cursor

−10

−5

0

c

−5.29 dB

199.625 MHZ

dB

Fig. 13 S22 parameter

0−10−20−30−40−70

F1=194 MHZF2=198.4 MHZ

2F1−F2=189.6 MHZ

−50

−30

−10

10

Pou

t, dB

m

Pin, dBm

−12dBm

F1

2F1−F2

Fig. 14 IP3 measurement

4.0

3.5

3.0

2.5

2.0120 170 220

frequency, MHz

270 320

NF

, dB

Fig. 15 LNA noise figure

Table 1: LNA experimental performance summary

Parameter Measuredresult

Simulatedresult

Specification

Power supply 3.3V 3.3V 3.3V

S21 21.7dB 20.8dB 410dB

S11 �9.2dB �13.2dB –

S12 �33.6dB �70.5dB –

S22 �5.3dB �10.3dB –

NF 2.7dB 2.5dB o3dB

IP3 �12 �15dBm 4�15dBm

1dB compressionpoint

�25 �28dBm –

IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5, October 2005 405

induced gate noise (not modelled by the BSIM3V3 model)is on important at 174–230MHz [15].

6 Conclusions

This work has described the design and implementation ofan LNA on CMOS process. The main application of thisamplifier is to perform voltage amplification of small signalsunder a low-noise constraint, which is very important inbiotelemetry systems. The amplifier does not use any tuninginductor, thus using only standard CMOS technology, anddemonstrates a gain of 21.7dB and a noise figure of 2.7dB.

7 Acknowledgments

The authors would like to thank the Funda-c*ao de Amparoa Pesquisa do Estado de S*ao Paulo FAPESP (The State ofS*ao Paulo Research Foundation), Conselho Nacional deDesenvolvimento Cientifico CNPq (National Council forScientific and Technological Development) and Coordena-c*aode Aperfei-coamento de Pessoal de N!ıvel Superior CAPESfor the financial support for the research work.

8 References

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2 Moreno, R.L., and Rodrigues, E.C.: ‘A CMOS low-noise amplifierfor biomedical telemetry applications’. Proc. Conf. on Design, Test,Integration and Packaging of MEMS/MOEMS, DTIP 2003,Mandelieu-La Napoule, France, 2003, pp. 95–98

3 Prieto, D.H., and Rodrigues, E.C.: ‘Experimental results of animplemented configuration for low offset voltage and its temperaturedrift reduction in piezoresistive pressure sensors’. Proc. Int. Conf. onMicroelectronics and Packaging, Campinas, SP Brazil, 1999, pp.249–252

4 Baltes, H.B.: ‘CMOS as sensor technology’, Sensors Actuators, A,1993, 37–38, pp. 51–56

5 Ramirez, J., and Rodrigues, E.C.: ‘A CMOS signal conditioningcircuit for piezoresistive pressure sensors’. IEEE Int. Symp. on Circuitsand Systems, ISCAS 2002, Scottsdale, AZ, 2002, Vol. 2, pp. 592–595

6 Ramirez, J.: ‘Interface Eletronica em tecnologia CMOS para sensoresde press*ao piezoresistivos utilizados em biotelemetria’. PhD thesis,

Polytechnic School, S*ao Paulo University, S*ao Paulo, Brazil, June2003

7 Lasso, J.H.: ‘Caracteriza-c*ao de Microindutores CMOS e Eletrode-positados em Cobre para aplica-c *oes em Biotelemetria’. PhD thesis,Polytechnic School, S*ao Paulo University, S*ao Paulo, Brazil, March2003

8 Moreno, R.L.: ‘Projeto, Implementa-c*ao e Teste de um Amplificadorde Baixo Ru!ıdo (LNA) para ser utilizado em um sistema debiotelemetria’. PhD thesis, Polytechnic School, S*ao Paulo University,S*ao Paulo, Brazil, November 2002

9 Life Sciences Advanced Biotelemetry Systems (LS-ABTS), Engineer-ing Specification, 11 January 1995

10 Karanicolas, A.N.: ‘A 2.7V 900MHz CMOS LNA and mixer’, IEEEJ. Solid-State Circuits, 1996, 31, (12)

11 Litmanen, P., Ik.al.ainen, P., and Halonen, K.: ‘A 2.0-GHz submicronCMOS LNA and a downconversion mixer’. Proc. of 1998 Int. IEEESymp. on Circuits and Systems, ISCAS 98, 1998, pp. 357–59

12 Razavi, B.: ‘RF microelectronics’ (Prentice Hall, 1998)13 Park, S., and Kim, W.: ‘Design of a 1.8GHz low-noise amplifier for

RF front-end in a 0.8mm CMOS tecnologoy’, IEEE Trans. ConsumerElectron., 2001, 47, (1), pp. 10–15

14 Lee, T.H.: ‘The design of CMOS radio frequency integrated circuits’(Cambrige University Press, 1998)

15 Scholten, A.J., Tromp, H.J., Tiemeijer, L.F., Tiemeijer, R., Havens,R.J., de Vreede, P.W.H., Roes, R.F.M., Woerlee, P.H., Montree,A.H., and Klaassen, D.A.M.: ‘Accurate thermal noise model for deep-submicron CMOS’. Digest of Int. Electron Devices Meeting, 1999,pp. 155–158

16 Huang, T., Zencir, E., Yuce, M., Dogan, N., Liu, W., and Arvas, E.:‘A 22-mW 435MHz silicon-on-insulator CMOS high-gain LNA forsubsampling receivers’. Proc. of 2003 Int. Symp. on Circuits andSystems, ISCAS 2003, 25–28 May 2003, Vol. 1, pp. I-417–I-420

17 Leroux, P., Janssens, J., and Steyaert, M.: ‘A 0.8dB NF ESD-protected 9mW CMOS LNA operating at 1.23GHz’, IEEE J. Solid-State Circuits, 2002, 37, pp. 760–765

18 Bruccoleri, F., Klumperink, E.A.M., and Nauta, B.: ‘Generating two-MOS-transistor amplifiers leads to new wideband LNAs’, IEEE J.Solid State Circuits, 2001, 36, (7), pp. 1032–1040

19 Deiss, A., Pfaff, D., and Huang, Q.: ‘A 200-MHz sub-mA RF frontend for wireless hearing-aid applications’, IEEE J. Solid-State Circuits,2000, 35, pp. 977–986

20 Janssens, J., Crols, J., and Steyaert, M.: ‘A 10mW inductorless,broadband CMOS low-noise amplifier for wireless communications’.Proc. Conf. on Custom Integrated Circuits, 1998, pp. 75–78

21 Shahani, A.R., Shaeffer, D.K., and Lee, T.H.: ‘A 12-mW widedynamic range CMOS front-end for a portable GPS receiver’, IEEE J.Solid-State Circuits, 1997, 32, pp. 2061–2070

22 Piazza, F., and Huang, Q.: ‘A 170MHz front-end for ERMES pagerapplications’, IEEE J. Solid-State Circuits, 1995, 30, pp. 1430–1437

23 BSIM3V3.2.2 MOSFET Model, Users’ Manual Department ofElectrical Engineering and Computer Sciences, University of Califor-nia, Berkeley, 1999. Web site: http://www-device.eecs.berkeley.edu/Bbsim3

Table 2: Comparasion of CMOS LNAs reported in literature

Paper ref. This work 10 16(*) 17 18 19 20 21 22

Frequency [MHz] 200 900 435 1230 900 200 900 1575 170

Technology 0.35mmCMOS

0.5mmCMOS

SOICMOS

0.25mmCMOS

0.35mmCMOS

0.8mmBiCMOS

0.5mmCMOS

0.35mmCMOS

1.2mmBiCMOS

Supply [V] 3.3 2.7 3.3 1.5 3.3 2 3.0 1.5 3

S11 [dB] �9.2 – �21 �11 – – – – –

S12 [dB] �33.6 �32.4 – �31 �30 – �41 �52 –

S22 [dB] �5.3 – – �11 – – – – –

S21 [dB] 21.7 15.6 80 20 11 17.5 14.8 17 22.3

IIP3 [dBm] �12 �3.2 – �11 14.7 �20 �4.7 �6 –

NF [dB] 2.7 2.2 2.1 0.8 4.4 3.7 2.3 3.8 6.2

(*) simulated results

406 IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5, October 2005