CMOS Layout
description
Transcript of CMOS Layout
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side view top view
diffusionpoly
metalcuts
CMOS Layout
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A View of Interconnect Layers
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Intel 4004 (1971)
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Pentium II (1996)
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Silicon in 2010
Die Area: 2.5x2.5 cmVoltage: 0.6 VTechnology: 0.07 m
Density Access Time(Gbits/cm2) (ns)
DRAM 8.5 10DRAM (Logic) 2.5 10SRAM (Cache) 0.3 1.5
Density Max. Ave. Power Clock Rate(Mgates/cm2) (W/cm2) (GHz)
Custom 25 54 3Std. Cell 10 27 1.5
Gate Array 5 18 1Single-Mask GA 2.5 12.5 0.7
FPGA 0.4 4.5 0.25
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CMOS Inverter Layout
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Layout
4-input NAND gate
Out
In1 In2 In3 In4
In3
In1
In2
In4
In1 In2 In3 In4
VDD
Out
GND
VDD
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Standard Cell Design Methodology
Example “stick diagram”
VDD
VSS
Well
signalsRouting Channel
metal1
polysilicon
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Different Layouts are Possible
Different layouts for x =
a c b a b c
xx
GND
VDDVDD
GND
(a) Input order {a c b} (b) Input order {a b c}
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The Barrel Shifter
Sh3Sh2Sh1Sh0
Sh3
Sh2
Sh1
A3
A2
A1
A0
B3
B2
B1
B0
: Control Wire
: Data Wire
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4x4 barrel shifter
BufferSh3Sh2Sh1Sh0
A3
A2
A1
A0
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Logarithmic Shifter
Sh1 Sh1 Sh2 Sh2 Sh4 Sh4
A3
A2
A1
A0
B1
B0
B2
B3
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A3
A2
A1
A0
Out3
Out2
Out1
Out0
0-7 bit Logarithmic Shifter
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Latches
D
D
In
(a) Schematic diagram
(b) Non-overlapping clocks
Pseudo-static Latch
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Edge-Triggered Register (Master/Slave)
D
InA
B
Overlapping Clocks Can Cause
• Race Conditions
• Undefined Signals
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Non-Overlapping Clocks
D
In
t12
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Dynamic Register
DIn
Input Sampled
Output Enable
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CL
CL CL
this circuit can use the entire clock cycle – no wasted time - a form of retiming
straightforward implementation
1
1
2
2
Registers and intervening logic
Switches and/or gates compute new values to store on next clock cycle
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bit bit'
rd or wr
(rd or wr)'
rd/wr'sensing amplifier
Memory – Static Register Cells
8-transistor cell
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data-in data-out'
wr
rd
dedicated busses forreading and writing
dynamic charge storagemust be refreshed
Memory – Dynamic Register Cells
4-transistor cell
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data-in data-out'
wr
rd
+5V
no p-type transistors yield
a very compact cell
pre-charge data-out' togenerate 1 outputs
Memory – Dynamic Register Cells (cont'd)
3-transistor cell
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storage capacitoris one end of transistor
charge sharing with
bus capacitance
(Ccell << Cbus)
extra demands onsense amplifier todetect small changesin bus charge
precharge tointermediate voltage level
destructive read(must immediatelywrite back)
Memory – Dynamic Register Cells (cont'd)
1-transistor cell
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bit1 bit2 bit3
read1
read2
programmable logic array structure
(exploits distributed NOR gate structure)
Read-only Memory Cells
To store constants or other invariant data
Popular for control implementation
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row-bus1
row-bus2
bus1
bus2 bus1'
bus2'
Multi-ported Register Cells
Add more input and output transistors (similar for all variations)
Not usually done for 1-transistor cells
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addressof word(n+m bits)
decoder
multiplexer ( 2m :1)
memorycell array
2m k-bit words per row
n
m
2n rows
k bits wide (k bits/word)
2n by 2m*k bits
Random access memory
Decoding logic to select word
Attempt to make critical lines (data lines) as short as possible
Square aspect ratio rather than rectangular
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decoder
n
bit bit'
rd/wr(row select)
memorycell array
+5V
Decoders
Decoder looks like AND-plane of ROM(all input combinations) usually replicated
throughout array
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word1word2word3word4
bit1 bit2
from a decoder
note: bits of word in row are interleaved
Multiplexers
Decode address into one-hot control signals
Each bit passes through single n-device or pass gate
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encoder
contentaddressable
memorycell array
n
2n rows
m bits
m
Content-Addressable Memory
Compares input to all entries in memory in parallel applications: pattern recognition, TLBs, etc.
Require and encoder to indicate where a match occurred perform inverse function of decoders take a one-hot collection of signals and encodes them
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Content-Addressable Memory Cells
Read and write like normal 6T memory cell
Match signal is precharged to 1, pulled to 0 if no match send data on bit' and data' on bit for matching match remains 1 if and only if all bits in word match
rowselect
match
bit bit'