CMOS Analog Design May 21.ppt - UFSC
Transcript of CMOS Analog Design May 21.ppt - UFSC
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 1
CMOS ANALOG DESIGN USING ALL-REGION MOSFET MODELING: PART I
Carlos Galup-Montoro, Márcio Cherem Schneider
Federal University of Santa Catarina Brazil
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 2
CONTENTS
� Two-terminal MOS structure
� Unified charge control model (UCCM)
� Drain current
� Pinch-off and threshold voltage
� Small-signal parameters
� Noise and mismatch compact models
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 3
VG
G
B
+ + + + + + + + +
QI
QG
--- -- -- -
-QB- -- ---- - - - - --
-
TWO-TERMINAL MOS STRUCTURE
gate-to-bulk voltage
oxide capacitance per unit area
surface potential
inversion charge per unit area
bulk charge per unit area
flat-band potential
( ) ( )G ox G FB s I BQ C V V Q Qφ′ ′ ′ ′= − − = − +
oxC′
IQ′
BQ′
sφ
FBV
GV
+
φφφφs
_
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 4
MOSFET SMALL-SIGNAL EQUIVALENT CIRCUIT
Ggb
G
dQC
dV
′′ =
1
1 1gb
c ox
C
C C
′ =
+′ ′
I Ii
s t
dQ QC
dφ φ
′ ′′ = − ≅ −
2
oxb
s t
CC
γ
φ φ
′′ ≅
−
c b i
C C C′ ′ ′= +
body-effect coefficient γ
thermal voltage (26 mV @ 300K)
t
kT
qφ =
CMOS Analog Design Using All-Region MOSFET Modeling 5
Determination of
Potential balance
0ssa Q
I
φ φ′ =
=
THE LINEARIZATION SURFACE POTENTIAL φsa
GV
s saφ φ=
BQ′
+_
bC′+
_
0IQ′ =
0iC′ =
oxC′
( )( ) 1sa t
G FB sa sa sa tV V sgn e
φ φφ φ γ φ φ −− = + + −
( )( ) ( )
/1
1 12sgn 1
sa t
sa t
G b
sa oxsa sa t
edV Cn
d C e
φ φ
φ φ
γ
φ φ φ φ
−
−
−′= = + = +
′ + −
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ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 6
UNIFIED CHARGE CONTROL MODEL (UCCM)-1
n+ n+
p
VSVG VD
1 tC I
ox I
dV dQnC Q
φ ′= −
′ ′
( )
ox b ox
G
C C nC
n n V
′ ′ ′+ =
=
Ii
t
QC
φ
′′ = −
I ox sdQ nC dφ′ ′=
S C DV V V≤ ≤
s i
C i ox b
d C
dV C C C
φ ′=
′ ′ ′+ +
1
1
I
ox t
Q
nC φ
′− <
′�
�
WI
SI
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 7
7
1 tC I
ox I
dV dQnC Q
φ ′= −
′ ′ Integrating between VC and VP
yields UCCM
lnIP I IP C t
ox IP
Q Q QV V
nC Qφ
′ ′ ′−− = +
′ ′
UNIFIED CHARGE CONTROL MODEL (UCCM)-2
IP ox t
II
ox t
Q nC
nC
φ
φ
′ ′= −
′′ =
′−
Thermal charge
Normalized inversion charge density
( 1 ln )P C t I I
V V q qφ ′ ′− = − +Normalized UCCM
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 8
8
IC s t
I
dQdV d
Qφ φ
′= −
′
( )I i C sdQ C dV dφ′ ′= −
CdVsdφ
GVI
i
t
QC
φ
′′ = −
IdQ′+ _
DRAIN CURRENT: PAO-SAH MODEL
s t CID I I
I
d dVdQI WQ WQ
dy Q dy dy
φ φµ µ
′′ ′= − − = −
′
D
S
V
D I CV
WI Q dV
Lµ ′= − ∫
,
( , )
G S
Dmd I D G
D V V
I Wg Q V V
V Lµ
∂′= = −
∂
driftI diffI
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 9
DRAIN CURRENT: CHARGE-SHEET MODEL
I ox sdQ nC dφ′ ′=
( )2 2
2
IS ID
D t IS ID
ox
Q QWI Q Q
L nC
µφ
′ ′−′ ′= − −
′
s ID I t
d dQI WQ W
dy dy
φµ µ φ
′′= − +
drift diffusion drift diffusion
2
2
tS ox
I C n Sφ
µ ′=Normalization (specific) current
2
2
tSH ox
I C nφ
µ ′=Sheet normalization (specific) current
WS
L=
D F R S f r SH f rI I I I i i SI i i = − = − = −
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10
Long-channel MOSFET ),(),( DGSGRFD VVIVVIIII −=−=
IF: forward current IR: reverse current
IF=
IR=
FORWARD AND REVERSE CURRENTS
(Forward) Saturation
D F R FI I I I= − ≅
Triode
D F RI I I= −
Triode for VDS→0
; F R D F R FI I I I I I≅ = − <<
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 11
MASTER DESIGN EQUATION
2
2
ISF drift diff t IS
ox
QWI I I Q
L nC
µφ
′′= + = −
′
ms IS
Wg Q
Lµ ′= − Pao-Sah model
( )1
2 /
msF ms t
ox t
gI g
C n W Lφ
µ φ
= +
′
( )( )
/1
/
thDsat WI
W LI I
W L
= +
or
( ) ( )/ 2ms ox tthg W L nCµ φ′=
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 12
ASPECT RATIO VS. CURRENT EXCESS
( )( )
/1
/
thDsat WI
W LI I
W L
= +
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WEAK, MODERATE, STRONG INVERSION
D F R S f rI I I I i i = − = −
( ) ( ) ( ) ( ) ( )2 2 1 1
f r IS D IS D IS D f ri q q q i′ ′ ′= + ⇒ = + −
WI MI SI
1 100fi< <1fi < 100 fi<
0.4 9Iq′< < 9 Iq′<0.4Iq′ <
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 14
14
Common-source characteristics
( )1 2 ln 1 1P S t f fV V i iφ − = + − + + −
UNIFIED I-V RELATIONSHIP (UICM)
since
D S f r S f
f r
I I i i I i
i i
= − ≅
>>
1,00E-09
1,00E-08
1,00E-07
1,00E-06
1,00E-05
1,00E-04
1,00E-03
0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00 3,00E+00 3,50E+00 4,00E+00 4,50E+00
10-3
10-6
10-9
VS = 0 V
3.0
2.5
2.0
1.5
0.5 1.0
0 1 2 3 4 VG (V)
ID (A) VD = VG
WI
MI
SI
VD
ID
VGVS
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 15
THE PINCH-OFF CHARGE DENSITY
The channel charge density corresponding to the
effective channel capacitance times the thermal
voltage, or thermal charge, defines pinch-off
( )IP ox b t ox t
Q C C nCφ φ′ ′ ′ ′= − + = −
The name pinch-off is retained herein for historical
reasons and means the channel potential
corresponding to a small (but well-defined)
amount of carriers in the channel.
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 16
THE PINCH-OFF VOLTAGE VP
The channel-to-substrate voltage (VC) for which the
channel charge density equals the pinch-off charge
density is called the pinch-off voltage VP.
UCCM is asymptotically correct in weak inversion if
in weak inversion
( ) ( )2 / 2 /( 1)sa F C t sa F C tV V
I b t ox tQ C e C n eφ φ φ φ φ φφ φ− − − −′ ′ ′− = = −
2 1 ln1
P sa F t
nV
nφ φ φ
= − − + −
2P sa F
V φ φ≅ −
0 2 2 T FB F F
V V φ γ φ≅ + +
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 17
THE THRESHOLD VOLTAGE VT0
Equilibrium threshold voltage VT0, for VC=0, gate voltage for which Q’I = Q’IP = -nC’oxφt
(gate voltage for which VP=0 )
2P sa F
V φ φ≅ −
G FB sa ox sa tV V Cφ γ φ φ′− = + −Recalling that
it follows that
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 18
Pinch-off voltage and slope factor as functions of VG [0.18 µm CMOS technology].
VP[V]
PINCH-OFF VOLTAGE AND SLOPE FACTOR
0G TP
V VV
n
−≅
( )0 1 3 2 ln 1 3 1P SV V − = = + − + + − if=3 at pinch-off
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 19
SATURATION VOLTAGE
Saturation voltage
(VDSsat): VDS at which
the ratio ID ISq q ξ′ ′ =
,
Saturation voltage versus inversion level
( )( )1ln 1 1 1DSsat t fV iφ ξ
ξ
= + − + −
( )1 ξ− is the saturation level
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 20
( )21 1
f S
ms S IS f
S t
di IWg I Q i
dV Lµ
φ′= − = − = + −
BmbDmdSmsGmgD VgVgVgVgI ∆+∆+∆−∆=∆
Calculation of gms
TRANSCONDUCTANCES
0mg ms md mb
g g g g− + + =
D F R S f rI I I I i i = − = −
( ) ( ) ( )2 2
( 1 ln )
f r IS D IS D
P C t I I
i q q
V V q qφ
′ ′= +
′ ′− = − +
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 21
Transconductance
-to-current ratio 11
2
)()(
)(
++=
rfRF
tdms
iI
g φ 1≅
( )
2
f ri≅
WI (if <1)
SI (if >>1)
TRANSCONDUCTANCE-TO-CURRENT RATIO
n
ggg mdms
mg
−=
msmg
gg
n=
in saturation:
10-4 10-2 100 102 104if
tox = 28 nm (IS = 26 nA)
model
102
101
100
gms/IF
tox = 5.5 nm (IS = 111 nA)
Seqüência1
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 22
PARAMETER EXTRACTION
( ) ( )max
/ 1/m D tg I nφ=
( ) ( )
( )
IS D IS D
IS D
IP ox t
Q Qq
Q nC φ
′ ′′ = =
′ ′−
max
2
2
m m
D D IS ID
g g
I I q q
=
′ ′+ +
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 23
INTRINSIC CAPACITANCES
( )1gb ox gs gd
nC C C C
n
−= − −
VDS= 1 V
( )2
2 1 2
3 11
ISgs o x
IS
qC C
q
α
α
′+=
′++
( )
2
2
2 2
3 11
IDgd ox
ID
qC C
q
αα
α
′+=
′++
( 1)bd gdC n C= −( 1)bs gsC n C= −
1
1
ID
IS
q
qα
′+=
′+ox oxC WLC′=
bg gbC C=
( )
2 3
3
4 3
15 11
IDsd ox
ID
qC nC
q
α α α
α
′+ += −
′++( )
2
3
4 1 3
15 11
ISds ox
IS
qC nC
q
α α
α
′+ += −
′++
A set of 9 independent MOSFET capacitances
Channel linearity factor
( ) / dg gd m sd dsC C C C C n− = = −
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 24
SMALL-SIGNAL MOSFET MODEL
G
DS
B
DBmd DB sd
dvg v C
dt+
GBmg GB m
dvg v C
dt−
SBms SB ds
dvg v C
dt+
Cgs
Cbs
Cgd
Cbd
Cgb
( ) / dg gd m sd dsC C C C C n− = = −
CMOS Analog Design Using All-Region MOSFET Modeling 25
INTRINSIC TRANSITION FREQUENCY
( ) ( )2 2
mg msT
gs gb gs gb
g gf
C C n C Cπ π= =
+ +
( )22 1 1
2
tT ff i
L
µφ
π≅ + −
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26
NOISE & MISMATCH
� The spontaneous fluctuations over time of the current and voltage inside a device, which are basically related to the discrete nature of electrical charge, are called electrical noise.
� Time-independent variations between identically designed devices in an integrated circuit due to the spatial fluctuations in the technological parameters and geometries are called mismatch.
� Mismatch (spatial fluctuation) and noise (temporal fluctuation) are similar phenomena, both being dependent on the process, device dimensions, and bias.
� Mismatch can be seen as “dc noise”.
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CMOS Analog Design Using All-Region MOSFET Modeling
THERMAL NOISE EXCESS FACTOR-1
For VDS→0, the transistor is equivalent to a resistor and
where gms (=gmd) is the equivalent conductance of the transistor
In weak inversion
For a saturated transistor (gms>>gmd) in weak inversion
CMOS Analog Design Using All Region MOSFET Modeling 27
2
24 4d IS
ms
i WLQkT kTg
f Lµ
′= − =
∆
( )2
4 42 2
IS IDd ms mdQ Q g gi W
kT kTf L
µ′ ′+ +
≅ − =∆
2
2dms
ikTg
f=
∆
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THERMAL NOISE EXCESS FACTOR-2
In general, the channel thermal noise is written as
γ is the excess noise factor and its value is 2/3 for a long-channel
saturated transistor in strong inversion.
for a short-channel transistor
where Le and Lesat are the electric length of the channel in the
linear and the saturation regions, respectively. Considering that
Lesat= Le-∆L, where ∆L is the channel shortening due to CLM, then
we can write
for short-channel transistors it is possible that γ >1 due to the CLM
effect.
CMOS Analog Design Using All Region MOSFET Modeling 28
2
4dms
ikT g
fγ=
∆
2
e Ishort
esat I
L Q
L WQγ =
′
21 I
short
e e IS
QL
L WL Qγ
∆≅ +
′
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CMOS Analog Design Using All-Region MOSFET Modeling 29
THERMAL AND 1/F NOISE
10n 100n 1µ 10µ 100µ 1m 10m
1E-15
1E-14
1E-13
1E-12
1E-11
1E-10
1E-9 (Not=2.6x107cm
-2)
Thermal Noise
Simulated
(Typ.NMOS model)
Measured
1/f Noise
Simulated(a)
Simulated(b)
Measured
SID
/ID
2
Drain Current [A]
Normalized flicker and thermal PSD at f=1Hz for saturated NMOS-T (W/L=200/5)
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CMOS Analog Design Using All-Region MOSFET Modeling30
CORNER FREQUENCY
Noise corner frequency (frequency at which the PSD of the 1/f
noise equals the PSD of the thermal noise)
100n 1µ 10µ 100µ
100
1k
10k
100k
Corner frequency fc
Calculated from measured gm
Calculated from estimated gm
Measured
Co
rne
r F
req
ue
ncy
f c
[Hz]
Drain Current ID [A]
2
Fc T
t
Kf f
nq
π
φ≈
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FK SPICE NLEV 2,3
1/f noise constant
PELGROM’S MODEL OF MISMATCH
� In most applications: the standard deviation of the difference
between the threshold voltages of two identical transistors
(∆VT0=VT1-VT2) is
CMOS Analog Design Using All Region MOSFET Modeling 31
( )( )
0
number of acceptors under gate/ ( )T d A ox
ox
V q q WLx N WLCWLC
σσ ′= =
′
( ) ( )0 0
22
d A VTT T
ox
q x N AV V
C WL WLσ σ∆ = = =
′
2 d AVT
ox
q x NA
C=
′
ISCAS 2010
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 32
MISMATCH – EXPERIMENTAL RESULTS
Dependence of mismatch on inversion level - Linear: � (VDS=50mV);
Saturation: � (VDS=1V) regions. Model :—
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 33
CMOS ANALOG DESIGN USING ALL-REGION MOSFET MODELING: PART II
Carlos Galup-Montoro, Márcio Cherem Schneider
Federal University of Santa Catarina Brazil
CONTENTS
� The intrinsic gain stage
� The source-coupled pair
� The two-transistor current mirror
� A self-biased current source
� A folded cascode amplifier
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 35
SUMMARY OF MAIN DESIGN EQUATIONS - 1
2 / 2SH ox t
I C nµ φ′=
( )/S SHI I W L=
( )D F R S f rI I I I i i= − = −Specific (normalization)
current
0.35 um CMOS technology
70 nA
25 nA
SHN
SHP
I
I
≅
≅
Forward and reverse currents
VDD
VT0
+
3ISH
/ 1W L =
25% SI±
Sheet specific current
D F S fI I I i≅ = saturation
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 36
SUMMARY OF MAIN DESIGN EQUATIONS-2
( )21 1S
m f
t
Ig i
nφ= + −Saturation
/ds D A
g I V=( )1 3DSsat t fV iφ= + +
( ) ( )( )
( ) ( )1 1 1 ln 1 1P S D
f r f r
t
V Vi i
φ
−+ = + − + + −
UICM
0G TP
V VV
n
−≅
A EV V L=
Gate transconductance
DS DSsatV V>
Output conductance
ID
VDS
dsg
AV
m Gg V∆
DSsatV
0
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 37
THE INTRINSIC GAIN STAGE - 1
Vmax
Vmin
maximum output swing
VDSsat1
VDSsat2
VDD
VDD
vo
viVTH
vo=vi
Av
( )011 1
1
1 2 ln 1 1TH Tf f
t
V Vi i
n φ
−≅ + − + + −
From UICM we find the dc voltage VTH at the input:
VDD
VI
M1
+
IB
CL
ID
I
L
M2
VO
VDD
ID
VO
IBVG
M1 M2
Output characteristics
Voltage transfer characteristic1 1 1
1
; BD B F R f
S
II I I I i
I= ≅ − ≅
0
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling
CLgogmvg
vi
+
vgvo
0
1 1
1 /
oV m V
i o L b
vA g A
v g sC s ω
= = − =
+ +
V-I converter (transconductor) followed by an I-V converter
(output impedance)
THE INTRINSIC GAIN STAGE - 2
1
1
Bds
A
Ig
V=
1 10
1
m mV
o ds
g gA
g g
− −= =
1 1
A EV V L=
10
1 1
2
1 1
AV
t f
VA
n iφ= −
+ +
38
|AV|dB
ωωuωb0
-20 dB/dec
|AV0|
Voltage gain vs frequency
/
/
b o L
u m L
g C
g C
ω
ω
=
=
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 39
CLgogmvg
vi
+
vgvo
0
1
1
EV
t
V LA
n ECFφ= −
+
minD WI m tI I g nφ= =
( ) ( )/ 1 1 / 2D WI WI fECF I I I i= − = + −
1
2
m
ox t
gW
L C ECFµ φ=
′Power-area tradeoff
How long can L be?
Sizing and biasing: W, L, IB
ECFCIN and transit time are both proportional to L2 (for constant W/L)!
THE INTRINSIC GAIN STAGE - 3
1 1
2
f
D t m
iI n gφ
+ +=
m u Lg Cω= ⋅
( )min min/D D DECF I I I= −
Design example Specifications: 0, ,u L V
C Aω
How do we choose if ?
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 40
2 21
4 4 1ch F m cms ms
ox
i K g fkTg kTg
f WLC f fγ γ
= + ≅ + ′∆
2chi
Bias-dependent factor
Thermal 1/fMOST noise model
2
Fc T
t
Kf f
nq
π
φ≅
Corner frequency
2 1/ 21
3 1 1fiγ
= − + +
1/2 (WI) 2/3 (SI)
2000
Tc
ff ≅ 0.35 um CMOS
technology
2 /chi f∆
cf f
Noise current generator
Input-referred noise model
2 2
2
1n ch
m
e i
f g f=
∆ ∆
2ne
Noiseless MOST
- +
THE INTRINSIC GAIN STAGE - 4
CMOS Analog Design Using All-Region MOSFET Modeling
2 /chi f∆
cf f
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 41
VSS
IT
+vG1
-
M1 M2
I1 I2
+vG2
-
First order analysis:
� Ideal current source
� M1 & M2 in saturation → I1 & I2 independent of drain voltage;
1 2
1 2
1 2 0
S S S
r r
n n n
I I I
i i
≅ =
≅ =
= =
1 2
1 2
1 2
T
OD
G G id
I I I
I I I
V V V
+ =
− =
− = 1 1 2 2
/ /
/ /
t T S od OD S
S S
i I I i I I
i I I i I I
= =
= =
Normalization
THE SOURCE-COUPLED PAIR -1
1 2 1 2 t odi i i i i i= + = −
1 12 2
ln 1 1 1 12 2
id t od t od
t
t od t od
V i i i i
n
i i i i
φ
+ −= + − + +
+ −+ − + −
0 84 12-4-8-12
1
it=1000100
10<1
I1/IT
I2/IT
id
t
V
nφ
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 42
VSS
IT
+vG1
-
M1 M2
I1 I2
+vG2
-
02 01 2 1; T T T S S SV V V I I I= + ∆ = + ∆
2
STG OS T
m S
IIV V V
g I
∆∆ = = ∆ −
Offset voltage VOS = ∆VG =VG2- VG1 such that
∆ ID= I2- I1=0
Simple model
( )0S mD
G T
D S D
I gIV V
I I I
∆∆≅ + ∆ − ∆
The differential input voltage at the input required for ∆ ID =0 is
THE SOURCE-COUPLED PAIR - 2
0( , )
D S f r S G T SI I i i I f V V V = − = −
0
( )0 0
0
@D D D DD S G T S m G T S
S G T S
I I I II I V V I g V V V
I V V I
∂ ∂ ∂∆ ≅ ∆ + ∆ + ∆ = ∆ + ∆ − ∆
∂ ∂ ∂
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 43
VSS
IT
+vG1
-
M1 M2
I1 I2
+vG2
- ( ) ( )( )
2 2
2 2
22
STOS T
m S
IIV V
g I
σσ σ
∆ = ∆ +
2
STG OS T
m S
IIV V V
g I
∆∆ = = ∆ −
( )( )22 2
2
2;
SVT IST
S
IA AV
WL I WL
σσ
∆∆ ≅ ≅Pelgrom’s
model
( )2
2 22
2
VT ISTOS
m
A AIV
WL g WLσ
= +
1 1
2 2
fT Dt
m m
iI In
g gφ + + = =
Uncorrelated ∆∆∆∆ VT & ∆∆∆∆ IS
Reminder
ISA Aβ=
THE SOURCE-COUPLED PAIR - 3
(I) (II)
(I) is dominant over (II) for
21 1 VT
f
t IS
Ai
n Aφ+ + <
0580 ( +0.8 V) for 32 mV,
8 mV m, 2 % m
f G T t
VT
i V V n
A Aβ
φ
µ µ
< < =
= ⋅ = ⋅
( ) 22 mV for 16µm & 100OS fV WL iσ ≅ = <
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 44
THE TWO-TRANSISTOR CURRENT MIRROR - 1
VDD
ii
+vG
-
iovo
+-
M1 M2
1:1
M1: i→v converterM2: v→i converter
Basic principle VG1=VG2; VS1=VS2; vout>VDsat → io≅ii
iD
vD
locus vD=vG
vG
vo
iD1
iD2
o i o i o i
i i A E
i i v v v vi
i i V V L
− − −∆= ≅ ≅
Error due to difference in VD values Error due to mismatch
0
0
0
1
D D DS T
D D S T
S mT
S D
I I II V
I I I V
I gV
I I
∆ ∂ ∂≅ ∆ + ∆
∂ ∂
∆≅ − ∆
( )( )
( )2 22 2
2 2 2
2 2
1D Sm mT VT IS
D D S D
I Ig gV A A
I I I WL I
σ σσ
∆ ∆ = ∆ + = +
( )( )0 , 1 / D S f G T S D A D Dsat
I I i V V V V V V V≅ − + >
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 45
THE TWO-TRANSISTOR CURRENT MIRROR - 2
( )( )1 1 2 2 1
1 1 1 2 1
A gs gb gs gb db B
A gs gb db ovd
C C C C C C C
C A C C C C
= + + + + +
= + + + +
1:A2mg v
1
1
m
ds
g
g+
ii
+
v
-
io
CA
CB
iiio
M1 M2
VDD
( )1
1
1 2
o A B
i m T
I C CA As
I s g fτ
τ π
+ +≅ = ≈
+
ii
io
M1 M2i1
i21:A
( )
( )
2
2 2 2 22 21 2
1 1
2 2 2 2 2
1 1
m mo i
m m
o i
g gi i i i A
g g
i A i i Ai
= + + =
= + +
Uncorrelated noise sourcesNoise analysis
ac analysis
The effect of M1 on noise is A times greater than that of M2
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 46
Gain-of-two current mirrors
VDD
II IO
1/2:1
W/L
W/L
W/L
VDD
II IO
1:2
W/L
W/LW/L
CURRENT MIRROR: GAIN SCHEMES
VDD
ii io==Aii
......
VDD
iiio==ii/A
......
Gain=A
Gain= 1/A
ii
io==ii/(NM)
.....
.
......N
M
Gain=1/(NM)
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 47
A SELF-BIASED CURRENT SOURCE – 1
21 2 2
1
11 1
f f f
Si i i
S Nα
= + + =
2
2 2
2
1 11 1 ln
1 1
fXf f
t f
iVi i
i
αα
φ
+ − = + − + + + −
Applying UICM to both M1 & M2
SELF-CASCODE MOSFET (SCM)
Sat.
Triode
2 xI NI=
M1
M2
( )2 2 2
1 1 2( ) ( 1)
S f r x
S f f x
I i i NI
I i i N I
− =
− = +
2 1f ri i=
0
2
2 2
X Xf
S SH
NI NIi
I S I= =where
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 48
A SELF-BIASED CURRENT SOURCE – 2
1 1
1 1 ln
1 1
X
even SHX X X
t even SH even SH X
even SH
I
S IV I I
S I S I I
S I
α
αφ
+ −
= + − + +
+ −
1 0.01 S =
2 0.01 S =IX
IX
2IX
SCM1,2
11 1even
odd
S
S Nα
= + +
/X t
V φ
/X SHI I
SCM1,2 SCM3,4
2
30.01S
α ==
4
18.71.13S
α ==
310 S =
4 1.13 S =IX
IX
2IX
SCM3,4
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 49
VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS)1
9 ln( )ref S t
V V JKφ= +
1 B. Gilbert, AICSP vol. 38, pp. 83-101, Feb. 2004
When both M8 & M9 operate in WI:
89
8 8
8
1 11 1 ln
1 1
fref S
f f
t f
JKiV VJKi i
iφ
+ −− = + − + + + −
A SELF-BIASED CURRENT SOURCE – 3
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 50
Vx
VFCMVx
A SELF-BIASED CURRENT SOURCE – 4
/X tV φ
/X SHI I
SCM1,2SCM3,4
VFCM is a positive feedback circuit →→→→return ratio must be < 1 for stability
1
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 51
A SBCS – 5: DESIGNOutput current: Iref=10 nA
ISHn-channel≅100 nA, ISHp-channel≅40 nA
21 2
1
11 1 3
S
S Nα −
= + + =
1 30 11 30 1 10 ln 2.93
1 10 1
X
t
V
φ
+ −= + − + + = + −
2(4)
2(4) 2(4)
2(4)
1 11 1 ln
1 1
fX
f f
t f
iVi i
i
αα
φ
+ − = + − + + + −
VFCM
Let us choose
if3(4) <<1 (WI)
2.93
3 4 3 4ln 18.7X
t
Veα α
φ− −≅ ⇒ = ≅
4 43 4
3 3
11 1 8.85
1
S S
S Sα −
= + + ⇒ =
=10 nA
2 2 2 2 110 nA 1 nA 0.01
S f SI i I S S= → = → = =
Let us choose 4 3 3 4/ 0.01f fi i α −= =
4 4 4 410 nA 1 A 10
S f SI i I Sµ= → = → =
43
1.138.85
SS = =
if2 = 10, S2= S1
Let us choose
if3=0.187 →→→→
1
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 52
A SBCS – 6: DESIGN
S if ir
M1 0.01 30 10
M2 0.01 10 0
M3 1.13 0.187 0.01
M4 10 0.01 0
M8, M8(a) 1 0. 1 0
M9, M9(a) 1 0. 1 0
MP (all) 2.5 0.1 0
4 10S =
VFCM
=1
=10 nA
21 0.0S =
2.93X t
V φ= 2.93X t
V φ=
3 1.13S =1 1 0.0S =
Summary
Core area in 0.35µm CMOS ≈≈≈≈ 0.02 mm2
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 53
A SBCS – 7 : IOUT vs. VDD AT CONSTANT T
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 54
A FOLDED CASCODE AMPLIFIER - 1
IT
ioM1 M2
M3 M4
M5 M6
M7 M8
M9 M10
M11
+ -
ITIT
VDD
GND
to VB3
+
vo
-CL
vi1 vi2
to VB2
to VB1
to VB4
V-I converter Current sources
1:1
High-Ro
current mirror
M3 & M4 – common-gate configurationIT/2 IT/2
VB3 & VB4 are such that M9(10)
& M5(6) operate on the edge
of saturation
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 55
IT
ioM1 M2
M3 M4
M5 M6
M7 M8
M9 M10
M11
+ -
IT IT
VDD
GND
to VB3
+
vo
-
CL
vi1 vi2
to VB2
to VB1
to VB4
VDD
IRE
F
M16
M1
2
GND
M1
3
M1
4 M1
5
VB
1
VB2
VB3
VB4
M17 M18
0.5 µµµµm CMOS
ISHN ≅≅≅≅ 40 nA, ISHP ≅≅≅≅ 16 nA, nN ≅≅≅≅ nP ≅≅≅≅ 1.2,
VEN=VEP=10 V/µµµµm, VT0N=0.7 V, VT0P=-0.9 V,
. =2.5 fF/µµµµm2
oxC′
CL=1 pF, VDD=5 V, IREF=0.6 µµµµA.
Transistor W
(µm)
L
(µm)
ID
(µA)
if
M1,M2, M5-M8 12.5 1 3 15
M3,M4 5 1 3 15
M9,M10 10 1 6 15
M11 25 1 6 15
M12-M14 10 4 0.6 15
M15 6 16 0.6 100
M17, M18 4 4 0.6 15
M16 7.5 50 0.6 100
A FOLDED CASCODE AMPLIFIER - 2
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 56
IT
ioM1 M2
M3 M4
M5 M6
M7 M8
M9 M10
M11
+ -
IT IT
VDD
GND
to VB3
+
vo
-
CL
vi1 vi2
to VB2
to VB1
to VB4
ISHN ≅≅≅≅ 40 nA, ISHP ≅≅≅≅ 16 nA, nN ≅≅≅≅ nP ≅≅≅≅ 1.2,
VEN=VEP=10 V/µµµµm, =2.5 fF/µµµµm2, CL=1 pFoxC′
Transistor W
(µµµµm)
L
(µµµµm)
ID
(µµµµA)
if
M1,M2, M5-M8 12.5 1 3 15
M3,M4 5 1 3 15
M9,M10 10 1 6 15
( ) ( )11 1
2 /1 1
SHP
m f
t
I W Lg i
nφ= + − =40 µA/V
Amplifier transconductance
Output conductance
Voltage gain
0 1 / 5,330 V/VV m oA g G= ≅
A FOLDED CASCODE AMPLIFIER - 3
10 2 6
4 4 8 8
0.6 0.3 0.3
/ / 48 / 0.3 48 / 0.3
7.5 nA/V
ds ds ds
o
ms ds ms ds
o
g g gG
g g g g
G
+ +≅ + = +
≅
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 57
IT
ioM1 M2
M3 M4
M5 M6
M7 M8
M9 M10
M11
+ -
IT IT
VDD
GND
to VB3
+
vo
-
CL
vi1 vi2
to VB2
to VB1
to VB4
Transistor W
(µµµµm)
L
(µµµµm)
ID
(µµµµA)
if
M1,M2, M5-M8 12.5 1 3 15
M3,M4 5 1 3 15
M9,M10 10 1 6 15
1 / 40 /1 A/V/pF
= 40 Mrad/s
m LGB g C µ= =
ISHN ≅≅≅≅ 40 nA, ISHP ≅≅≅≅ 16 nA, nN ≅≅≅≅ nP ≅≅≅≅ 1.2,
VEN=VEP=10 V/µµµµm, . =2.5 fF/µµµµm2, CL=1 pFoxC′
Gain-bandwidth product
Slew rate
max
6 V/ so T
L
V ISR
t Cµ
∆= = =
∆
Offset voltage
( ) ( ) ( ) ( )2 2
2 2 2 25 9
01 05 09
1 1
m m
OS T T T
m m
g gV V V V
g gσ σ σ σ
≅ + +
( )
( ) ( )
2 2
0
5 1 9 1
2 2
01,5,9
/ ; 10 mV m
/ 1 / 2
8, 8, 10 mV 7.5 mV
T VT VT
m m m m
T OS
V A WL A
g g g g
V V
σ µ
σ σ
= = ⋅
= =
= → ≅
Pairs M3-M4 & M7-M8 contribute negligibly to the offset voltage
A FOLDED CASCODE AMPLIFIER - 4
(*)
(*) : For this design IT=2.5*ITmin
ISCAS 2010 CMOS Analog Design Using All-Region MOSFET Modeling 58
IT
ioM1 M2
M3 M4
M5 M6
M7 M8
M9 M10
M11
+ -
IT IT
VDD
GND
to VB3
vi1 vi2
to VB2
to VB1
to VB4
NOISE ANALYSIS
2 2 2 2
1 5 92no n n ni i i i
f f f f
≅ + + ∆ ∆ ∆ ∆
PSD of the output noise current
Pairs M3-M4 & M7-M8 contribute negligibly to amplifier noise
A FOLDED CASCODE AMPLIFIER - 5
2/
(pA/ Hz)
noi f∆
(kHz)f
2.5
10