CML RapidIO SerDes (HIPA 21000) IP core - HDL Design House · 2017. 12. 6. · (HIPA 21000) IP core...
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Current Mode Logic RapidIO SerDes (HIPA 21000) IP core Description Rapid IO is a leading serial communication standard in embedded systems. The use of Rapid IO supporting IP cores speeds the design cycle, increases design quality and allows greater degree of innovation, enabling companies to reduce design costs and create market differentiation. Although this IP is designed to be used with SRIO 2.1 HIP3100 IP core (developed by HDL Design House), it can be used by any digital interface which satisfies timing parameters. The HIPA 21000 is qualified to operate in industrial temperature range (-40°C to 85°C). In order to save power in case of no data transfer, the device can be driven in power down mode. Serial data transfer rate is to be chosen between five different values: 1.25 Gbaud/s, 2.5Gbaud/s, 3.125Gbaud/s, 5Gbaud/s, 6.25Gbaud/s. HDL Design House provides IP cores for reuse along with IP core customization services to meet specific customer needs. This customization service includes migration to another technology ven- dor. Optimized for today’s SoC designs, these IP cores are supported with full documentation, including architectural specifications and detailed test specification. Full integration support is available. CML RapidIO SerDes (HIPA 21000) IP core HDL Design House, Golsvortijeva 35, Belgrade, Serbia Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com HIPA21000 -1.0 DS.REV.1.0 12.10.2010 Key Features: · Single 1.8V power supply voltage · Extracted clock from received data is available · Rapid IO standard 2.1 is supported. Data rate from 1.25Gbaud/s to 6.25 Gbaud/s are possible · Operating temperature satisfies industrial temperature range (-40°C to 85°C) · Adaptable data transfer rate · Parallel data 20 bit wide · Modular design · Minimal external components · Programmable Tx pre-emphasis and Rx post-equalization · 8b/10b encoding support · Digital interface operating at frequency up to 312.5 MHz The use of IP cores in ASIC, FGPA and system-on-chip(SoC) designs has become a critical methodology as compa-nies struggle to address the need for rapid prototypingand production. Reusable, drop-in components with prede-fined functionality, IP cores speed the design cycle, increasedesign quality and allow a greater degree of innovation,enabling companies to reduce design costs and create mar-ket differentiation.HDL Design House provides a set of IP cores for reusealong with IP core customization services to meet specificcustomer needs. Optimized for today’s SoC designs, theseIP cores are supported with full documentation, includingarchitectural and micro-architectural specifications, synthesisscripts, detailed test plans, test case definitions andtest bench descriptions. This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
Transcript of CML RapidIO SerDes (HIPA 21000) IP core - HDL Design House · 2017. 12. 6. · (HIPA 21000) IP core...
Current Mode Logic RapidIO SerDes(HIPA 21000) IP core DescriptionRapid IO is a leading serial communication standard inembedded systems. The use of Rapid IO supporting IP coresspeeds the design cycle, increases design quality and allowsgreater degree of innovation, enabling companies to reducedesign costs and create market differentiation. Although this IP is designed to be used with SRIO 2.1 HIP3100IP core (developed by HDL Design House), it can be used byany digital interface which satisfies timing parameters. TheHIPA 21000 is qualified to operate in industrial temperaturerange (-40°C to 85°C). In order to save power in case of no data transfer, the device can be driven inpower down mode. Serial data transfer rate is to be chosen between five different values: 1.25Gbaud/s, 2.5Gbaud/s, 3.125Gbaud/s, 5Gbaud/s, 6.25Gbaud/s. HDL Design House provides IP cores for reuse along with IP core customization services to meetspecific customer needs. This customization service includes migration to another technology ven-dor. Optimized for today’s SoC designs, these IP cores are supported with full documentation,including architectural specifications and detailed test specification. Full integration support isavailable.
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Key Features:
· Single 1.8V power supply voltage
· Extracted clock from received data isavailable
· Rapid IO standard 2.1 is supported. Datarate from 1.25Gbaud/s to 6.25 Gbaud/s arepossible
· Operating temperature satisfies industrialtemperature range (-40°C to 85°C)
· Adaptable data transfer rate
· Parallel data 20 bit wide
· Modular design
· Minimal external components
· Programmable Tx pre-emphasis and Rxpost-equalization
· 8b/10b encoding support
· Digital interface operating at frequency upto 312.5 MHz
The use of IP cores in ASIC, FGPA and system-on-chip(SoC) designs has become a critical methodology as compa-nies struggle to address the need for rapid prototypingand production. Reusable, drop-in components with prede-fined functionality, IP cores speed the design cycle, increasedesign quality and allow a greater degree of innovation,enabling companies to reduce design costs and create mar-ket differentiation.HDL Design House provides a set of IP cores for reusealong with IP core customization services to meet specificcustomer needs. Optimized for today’s SoC designs, theseIP cores are supported with full documentation, includingarchitectural and micro-architectural specifications, synthesisscripts, detailed test plans, test case definitions andtest bench descriptions.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Block diagramFunctional block diagram is presented on the Figure 1
Figure 1: Rapid IO SerDes block diagram
Benefits
· Easy to use
· Simplifies design verification process
· Reduces development costs
· Speeds time-to-market with new SoCs
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Functional descriptionThe HIPA 21000 is 20-bit serializer/deserializer designed to transmit and receive data over differen-tial back-planes at clock speed from 312.5MHz. The following sections describe each state of theoperation.
RESET MODEThe device needs to be in reset at both power up and some time after, in order to set device in pre-defined state. Signal RES active high has to be provided from the user. In reset mode PLL is inactive.
SYNCHRONIZATION MODEAfter the signal RES is driven low (inactive), PLL starts to lock itself to the input referent clock. Aftertime tLCK, system clock (clock at which data are sent) is fully synchronized with referent clockwhich is presented in Figure 2. data input is observed and locking clock with serial data start.
Output clock is phase synchronized with incoming data. This clock can be used by digital interface.
Figure 2: System clock locked with reference clock
STANDARD OPERATION MODEThe receiver is activated, data are received and system clock is phase synchronized with incomingdata after the time tREADY . Typical timing diagram in that case is presented in Figure 3.
During the time tREADY, the start messages are received and after the time tREADY, SerDes isready for transmitting and receiving data. It is important to notice that the Rapid IO standard sup-ports automatic baud-rate detection. SerDes cannot detect baud rate automatically. It should bedone by digital interface; SRIO21 IP core has such possibilities. Possible baud rates are:
· 25 Gbaud/s · 5 GBaud/s · 125 GBaud/s· 5 GBaud/s· 25 Gbaud/s
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Figure 3: system clock synchronized with incoming data
and those are the possible frequencies at which input data are sampled on the receiver part, oroutput data sent at the transmitter part. Parallel data frequency is 20 times lower than the serialdata baud rate. Data rate can be chosen with signals CDRcon<0:2>, more details are given inTable 1.
POWER-DOWN MODEIn order to achieve significant power saving, power-down mode is implemented. Driving the pinPD high, this mode is activated. In this mode, VCO and all high speed digital logic doesn't work.After the signal PD is inactive, some time tPDREC is needed in order for the device to be fully oper-able.
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Table 1: Signal description
1To be connected to digital interface2Should be connected to internal analog part3To be connected to the pads
Absolute maximal ratings
(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damageto the device. These are stress ratings only, and functional operation of the device under these orany other conditions beyond those indicated as recommended operating conditions is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.
Recommended operating conditions
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Table 2: Absolute maximal ratings
Table 3: Recommended operating conditions
(1)In design there are three power supply contacts and three ground contacts, one is for the digitalpart (CMOS) and two for the other part of the chip.
Electrical characteristics
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Table 4: Electrical characteristics
SWITCHING CHARACTERISTICS
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Table 5: Switching characteristics
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Figure 4: Output driver test circuit with output timing diagram
Figure 5: Deserializer delay time diagram
Figure 6: Serializer time diagram
Application information
PACKAGINGThe performance of the HIPA 21000 IP core is affected by the characteristic of the chosen package.It is important that package parasitic parameters (inductance, resistance,...) are small enough toreduce signal degradation.Special care should be taken when choosing a pin order so that any interference between inputand output is avoided as much as possible. It is important to simulate the exact package modelwith a circuit simulator to make sure that the best possible choice is made.
DIFFERENTIAL TRACES AND TERMINATION
The performance of the HIPA 21000 is also affected by the characteristics of the transmissionmedium. Use controlled-impedance media and termination at the receiving end of the transmis-sion line with the media’s characteristic impedance. Use balanced cables such as twisted pair or differential traces that are ran close together. A bal-anced cable picks up noise together and appears to the receiver as common mode. Differentialreceivers reject common-mode noise. Keep cables or traces matched in length to help reduceskew.Running the differential traces close together helps cancel the external magnetic field, as well asmaintain a constant impedance. Avoiding sharp turns and reducing the number of vias also helps.
TOPOLOGIESTypical application is that SerDes operate together one with the other. In this case, one is masterwhich initiates transfer and the other is slave. One possible solution is presented in Figure 7.
Both input and output should be closed with characteristic impedance (typically 100Ohm differen-tially or 50Ohm single-ended).
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Figure 7: Typical application example
DIGITAL INTERFACE
The HIPA 21000 should be connected to the proper digital interface which has to fulfill several con-ditions:to be able to adjust data rate at the communication channel. to be able to operate with clock up to 312.5MHzto be able to adjust both input and output equalizers.
Connecting diagram between the SerDes (HIPA 21000) and digital block is presented in Figure 8.and summarized in the table 6.
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
Figure 8: SerDes and digital block connection diagram
HDL Design House Representatives
For complete list of HDL Design House representatives visit following link:http://www.hdl-dh.com/sales_rep.html
Contact Information
CML RapidIO SerDes(HIPA 21000) IP core
HDL Design House, Golsvortijeva 35, Belgrade, Serbia
Phone: +381 11 414 55 55 Fax: +381 11 414 55 59 Email: [email protected] On-line: http://www.hdl-dh.com
HIPA21000 -1.0 DS.REV.1.0
12.10.2010
©2010, HDL Design House. All other trademarks are the property of their respective owners.
HDL Design HouseGolsvortijeva 35,Belgrade, SerbiaPhone: +381 11 414 55 55Fax: +381 11 414 55 59Email: [email protected]://www.hdl-dh.com
Table 6: Summarized interface signals
