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Collaboration is Materially Important to Semiconductor Innovation Gregg Bartlett Chief Technology Officer

Strategic Materials Conference October 17, 2013

Agenda The Need for Materials Innovation

Technology Challenges Economic Realities

A Collaborative Approach

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Market needs drive new requirements: Performance, Power, Cost (PPC)

Multicore processors

High resolution screens

Thinner form factors

Higher data rates, longer battery life

The Convergence is Here

Communication Computing Consumer

Navigation Imaging Video

Performance* Power Cost/Area

A4 A5 A6 A7

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The impact of scaling

28nm 20nm 14nm 10nm

Die Scaling

28nm 20nm 14nm 10nm

Total Power@ Iso_freq

28nm 20nm 14nm 10nm

Fmax@ Vnom

PPA Active battery life GDPW Fmax @ Vnom

Technology Architecture Metrics28nm

20nm

14nm

10nm

14XM Cortex A9 Dual-Core

0.600

2.000

0.200 0.400 0.600 0.800 1.000Relative Total Power

14XM-9T

28SLP-12TRe

lati

ve P

erf

orm

ance

62% Power Reduction

61% Performance Increase

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2D scaling can ‘only’ take us so far…

Device and packaging innovations combined with scaling will keep roadmap alive and well

Perf

orm

ance

, Den

sity

Gate Oxide Limit

Planar CMOS

Bipolar

Bipolar Power Limit

Atomic Dimension

Limit

3D Devices & 3D chip stacking Adv. Power Mgt

Sapphire eDRAM

Emerald eDRAM

Package

1980 1990 2000 2010 2020

Planar Device Limit

Planar CMOS w/ material & memory

innovations

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Driving the leading-edge process roadmap…

2003 2005 2007 2009 2011 2013 2015

Single CESL

90nm

65nm

45/40nm

32SOI

28nm

20nm

<100> Wafer Orientation For Low Cost Enhancement

DSL Stressors In Production eSiGe For PFET

Enhancement

HKMG For Leakage Reduction

Production Development

130nm

Fully depleted device

* In collaboration with ST

2017

14nm

10nm

7nm 28FDSOI*

Path-Finding

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Innovations in silicon manufacturing new materials enable innovation

11 Elements

+4 Elements

+45 Elements (Potential)

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Innovations are driven in three areas

Collaboration is Essential to Success

Economics and Environmental Friendliness

Improving Device Performance

Scaling Dimensions

Evolving Connectivity

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Improving performance is about shrinking and expanding BEOL materials innovations in the ‘good old days’ Device and channel levels drive future improvements. Novel materials innovations = device performance improvements.


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CVD W

MOCVD TiN

CoSI2

Stress Liner

Si-C

SiGe channel

Si-P

Low-K ESL

Ultra Low-K

ULK Cap

Eless Cu

MIS

Dual Si2

Cu Contact

Dual Si2

AIR GAP

Porous LK

Cu Alloys

Electroless Cu

Sel Metal caps

Porous LK

New Cu BM

Cu Alloys

Eless Cu

Fin FET

Multiple EWF

Si-50%Ge

Ge MOS

ALD Metals

Replacement Metal Gate

High K

Metal Gate

Gate First Stress Liner

Si-Ge

FTEOS ILD

Cu Barriers

Cu wiring

Bulk Si

Al Wires

Si Strain

ILD Cu caps FTEOS ILD

SOI

Low K ILD

CoWP cap

CPI

Si orientation

MIM CAP

TSVs

MIM CAP II

TiSSi2

ALD W

NiPtSi

Technology Node

350 250 180/130 90 65 /45 45/32 28/20 14/beyond

BEOL Contacts Device Channel

Device performance: planar to FinFET

Density Scaling

Gate Pitch

Scaling

Contact Width

Scaling

Contact Resistance

Increase (Active power

needs to increase)

Gate Length Scaling

Ioff Increase (Stand-by

power increase)

FinFETs

0

50

100

150

200

250

300

Phys

ical

dim

ensi

ons

[nm

] Technology node [nm]

Gate pitch

Gate+2Spacers

22 32 45 65 90 14

CO

NTA

CT

CO

NTA

CT

SUBSTRATE

G

Gate pitch

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Source-Drain engineering: stress

• Selective epi of SiGe replacing Si fin in S/D area adds stress to PMOS FinFET channel.

• Stress benefit saturates for fin recess ~20nm below STI surface – 3D modeling

Fin

S/D Epi Fin Height=30nm Fin width=14nm


Migration from planar to FinFETs was enabled with novel materials • In the last few years, the transistor migrated from SOI + Gate First metal gate to FinFET +

RMG, for improved performance.

• While both integrations utilize NiPtSi, CVD TiN, ALD HK, and W contacts, additional novel materials innovations enable this transition.

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2011

ALD Barrier

High K

Rep Metal Gate

FinFETs

2013

Si-Ge SiGe Channel

High K

Gate First

CVD W

NiPtSi

CVD TiN

CVD W

NiPtSi

CVD TiN

Examples: challenges with material changes

• NiSi was under development by for >4 years before NiPtSi was inserted into HVM – NiSi advantages: Lower Rs, lower thermal budget, formation on Si-Ge, linewidth independent – NiSi challenges: Fast diffusion and NiSi2 is stable phase (and will form!)

• Pt additions to NiSi increase the thermal stability

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Diff

ract

ed A

ngle

(2q)

J. Patton et al, ISSM (2004)

“Nickel Silicide Technology”, C. Lavoie, C. Detravenier and P.R. Besser, in Silicide Technology for Integrated Circuits (2005)

S. Thompson et al., IEEE IEDM, 3.2.1 (2002)

100 200 300 400 500 600 700 800 900Temperature ( C)

0

50

100

150

200

250

Resis

tance

(arb.

units

)

Ni-Si

Co-Si

CoSiCo2Si

CoSi2

Metal RichPhases NiSi NiSi2

o

The development of a manufacturable process requires a fundamental understanding of technology interactions

Metallization challenges: • Cu barriers must be thin, continuous, low resistivity • ALD barriers reduce line resistance • Void-less Cu fill • Pre-clean prior to barrier metal deposition • Cu grain size and texture control

Dielectric challenges: • Lower k dielectrics:

• poorer mechanical stability • moisture sensitive

• Topography and planarity from CMP • Cap layer deposition process and material type

Reliability: BTS, TDDB, EM, SM

Metal/via patterning and etch: • straight and smooth sidewalls •tapered line and via profile • residuals at via bottom

Example = BEOL

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Economic effects of innovations

R&D must deliver technologies which meet the performance expectations of the customer. Innovations are implemented when the value of the improvement is greater than its cost.

Economics

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cost value

Advanced technology costs are rapidly escalating

Economics

Fab Cost

Chip Design Cost

Process Development Cost

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Technology complexity makes equipment a greater proportion of overall fab costs

Economics

SOURCE: VLSI

Breakdown of Equipment Costs

30%

20%

15%

10%

10%

5%

5%

5%

0% 10% 20% 30%

Lithography

Etch

PVD

CVD

Metrology

Implant

CMP

Diffusion

Historical Breakdown of Fab Costs

70% 70% 75% 80% 85%

30% 30% 25% 20% 15%

0%

20%

40%

60%

80%

100%

90nm 65nm 45nm 32nm 20nm

Facilities Equipment

0%

100%

50%

90nm 65nm 45nm 32nm 20nm

Facilities Equipment

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Materials are becoming the largest cost contributor

Economics

• Equipment depreciation is flattening out

• Rising R&D costs have been dealt with by consolidation

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Cost of materials ($/wafer) is increasing over time

Economics

The increase in cost of materials to build a processor from 32/28nm to <20nm technology is driven mostly by new materials innovations (i.e. ALD).

32nm <20nm

Graphic used with permission from Mike Corbett, Linx Consulting, Inc. 23

EUV Lithography – extreme materials management

* H. Levinson, J. Micro/Nanolithography (2009)

Exposure Tool Cost vs. Time*

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EUV tool depreciation:

$47/minute

Reflective masks on mutli-layer films Complex light sources

• 1-2 megawatt electrical power consumption

• Cooling water: >700 gallons per minute

• 1 gram of ultrapure tin consumed for each wafer exposure, roughly 2000kg/yr

Economics

EUV lithography is disruptive due to the amount of materials innovation Lithography materials innovations are dramatic with EUV.

Technology Node

250 180/130 90 65 /45 45/32 28/20/14 <10

Low CTE mirrors

CaF2 added a Lens material

Mulilayer masks

Mo/Si + Ru + TaN or TaBN + TaN or TaNO

Solvent TBAH developer

Chemically amplified

resists

HMDS adhesion promoters

I-line Hg

365nm

DUV Kr + F + Ne

248nm

Dry Ar + F

193nm

EUV CO2 + Sn

13nm

Immersion H20, Ar + F

193nm

inorganic metal oxide

resists

Fused Silica Quartz

Lens

TMAH developer

Organic underlayers

Scaling Dimensions

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BEUV Gd, Tb 6.5nm

New materials and mechanisms are driving memory innovation


• Mainstream memory technology: Si-based and unchanged for many generations

• Materials innovations are at the heart of novel memory development.

• All future technologies include new materials with new memory mechanisms.

Technology Node

250 180/130 90 65 /45 45/32 28/20 14/beyond

RRAM

MeOx with novel electrode

eDRAM HfOx

Phase Change Memory

GeSbTe

STT-RAM

CoFeB, PtMn, Ru, Co, Pd, Pt, Ta, MgO, L1 multilayers

SRAM Si/oxide

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DRAM Si/HK

FLASH SONOS

Metal oxides for RRAM applications

Binary metal oxides: • NiOx, TiOx, ZrOx, HfOx, CuOx, AlOx, TaOx, ZnOx,

WOx, NbOx, MoOx, MnOx, CeOx, GdOx, SnOx, CoOx, MgOx, VOx, …

Complex metal oxides: • SrTiO3, SrRuO3, SrZrO3, … • PrCaMnO3, LaCaMnO3, LaSrMnO3, …

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Materials innovations driving connectivity on and off chip


While materials changes can be costly, scaling of dimensions and performance needs have necessitated materials innovations in packaging.

Technology Node

250 180/130 90 65 /45 45/32 28/20 14/beyond

CPI

Cu Polyimide Interposers

3D stacks

White bumps

20um solid Cu TSVs

10um Cu TSVs 6um Cu TSVs

<3um TSVs

Cu/W Fill with alternate B/S

Low K isolation

Cu oxide Interposers

Tight pitch

Nitride Passivation

Conformal Cu TSVs

Organic Passivation

BCB

Evaporated High-Pb bumps

Pb-plated bumps

Eutectic Sn-Ag bumps

50 um TSVs

Fine pitch Cu pillars

Cu µ-bumps

Direct bond Cu-Cu

Solder-tip Cu pillars

Oxide Passivation

Sn-Ag plated bumps

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20nm technology with integrated TSVs at GLOBALFOUNDRIES

TSV

Mo

du

le

TSV ETCH

TSV LITHO

TSV CLEAN

TSV CVD

TSV PVD

TSV ECP

TSV CMP

BEOL

Si

FEOL

WAFER E-TEST

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Packaging is evolving to new dimensions Advanced Packaging Will Drive Continued Cost Growth

Silicon Partitioning

with Interposers

Market: FPGA

Memory Cube

Market: Server and Computing

Logic + Memory on Interposer

Market: GPU, CPU,

Network Processors

Wide I/O Memory on

Apps Processor

Market: Mobile, Tablet

Heterogeneous Stacking

Market: Mobile, CPU

2011 2013 2014 2016 2017?

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Most of the cost growth is in the backend Packaging costs are on the rise

Economics

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Actions to reduce chemical use and emissions

Environmental Friendliness

• Ozone Depleting Substances – Phased-out in 1990’s

• Ethylene Glycol Ethers – Phased-out in 1990’s

• PFC Gases (high Global Warming Potential) – 1999 – WSC agrees to reduce emissions 10% below 1995 – Solutions: NF3 chamber clean, alternate etch gases – 2012: Emissions ~40% below 1995

• Lead and other heavy metals - Hg, Cd, Cr(VI) – “Pb-free” packaging to address EU RoHS Directive

• PFOS (Perfluorooctylsulfonates) – WSC eliminated non-critical uses – Developed new photo-acid generators – 2010: Emissions reduced 99%

• Enclosed Tools and Processes

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Need to evaluate environmental aspects of new materials during R&D


• EHS challenges: – CNTs, other Engineered Nanomaterials – III-V materials – Reactive precursors – Chemical data gaps

• SRC, SEMATECH and CNSE are collaborating with SIA to address EHS research needs

• SRC membership model allows suppliers and non-members to join EHS research program

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Conflict minerals usage and supply


Source: EICC

GLOBALFOUNDRIES uses:

Ta: PVD targets, precursors W: PVD targets, WF6 gas

Au: PVD targets Sn: Plating solutions

We are Conflict-free for Ta

Further supply chain

cleansing is needed to reach

full conflict-free status

60%

36%30%

9%

0%

20%

40%

60%

80%

100%

Tantalum Tin Tungsten Gold

% Consumed in Electronics

e.g. Ta PVD targets Ta precursors

15%8% 4% 1%

0%

20%

40%

60%

80%

100%

Tantalum Tin Tungsten Gold

% Supplied from Congo Region

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Materials innovations require early collaboration between tool suppliers, materials suppliers, and GLOBALFOUNDRIES

Engaging early, deeply, openly, and comprehensively

Collaborative Innovation

Tapping global talent

Jointly develop new technologies and manufacturing solutions

Focused on shared success

Time to Everything!

Research Development

Electrical testing, Yield HVM

Materials Supply (substrates, resists, gases, abatement, slurry, targets,

precursors, chemicals, and packaging mat’ls)

HVM tooling (Chambers, Platforms,

Productivity)

Unit process Integration

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Collaborative Models An enabling and sustainable model

1990s 1980s 2012+

IDM – Design & Manufacturing

Collaborative Device Manufacturing

Foundry Manufacturing

Fabless Design

Collaborative: Design flow development

Manufacturing supply chain Customer engagement model

Business practices

Key Technology Elements: Leading edge (28nm, 20nm, 14nm)

2.5D, 3D TSV, BSI, Bump, Assembly Development Eco-system Partners Supply chain initiatives

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It takes an ecosystem Multi-lateral collaboration is critical to driving continued innovation

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The next wave of challenges will require even more collaboration

‘Normal economics’ are dead

Value proposition shifting toward PPC

Alternative scaling opportunities

(2.5/3D)

Packaging

Pilot lines and HVM timing driven by 193i and EUV

lithography

G450C

450mm

FDSOI

FinFETs

NanoWires

III-V

Device Architectures/

Materials Cost

Multi-pattern immersion

EUV Source power

Tool availability

Litho/EUV

Cost –Time to Everything, Moore’s Law, SCM Security, Talent, IP Security

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Summary

• Novel materials innovations drives enhanced performance.

• Leading-edge nodes are seeing an explosion of new materials.

• Materials innovations present technological and economical challenges which can only be overcome through collaboration.

• Only collaboration can these materials innovations which drive performance and reliability be introduced seamlessly at an affordable cost and on time.

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cost value

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