Class Notes Digital Lec16

8/7/2019 Class Notes Digital Lec16

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August 03, 2010

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Telephone :

PABX : 9661920-73/4980

DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING

UNIVERSITY OF DHAKA

DHAKA-1000, BANGLADESH

FAX: 880-2-8615583

E-MAIL: [email protected]

Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

Logic Families:There are various approaches used to produce different types of digital integrated circuit. Each such fundamentalapproach is called logic family. Different logic functions, when fabricated in the form of an IC with the same approach,will have identical electrical characteristics. These characteristics include

(I) supply voltage range,(II) speed of response,(III) power dissipation,(IV) input and output logic levels,(V) current sourcing and sinking capability,(VI) fan-out and

(VII) noise margin.The set of digital ICs belonging to the same logic family are electrically compatible with each other.When the output of an IC belonging to a certain family feeds the inputs of another IC belonging to a different family,an interface technique must be established to ensure compatibility.The entire range of digital ICs is fabricated using either bipolar devices or MOS devices or a combination of the two.Logic families that are in widespread use include

(I) transistor transistor logic (TTL),(II) emitter coupled logic (ECL),(III) NMOS family (using N-channel MOSFETs),(IV) CMOS family (using both N- and P-channel MOSFETs) and(V) Bi-CMOS logic family (uses both bipolar and MOS devices).

[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

Characteristic Parameters:Some of the parameters used to characterize different logic families are discussed below.

Fig.: Currents and voltages in the two logic states HIGH and LOW.VIH(min) High-Level Input Voltage: The minimum voltage level required for a logical 1 at an input.VIL(max) Low-Level Input Voltage: The maximum voltage level required for a logic 0 at an input.

VOH(min) High-Level Output Voltage: The minimum voltage level at a logic circuit output in the logical 1 state underdefined load conditions.VOL(max) Low-Level Output Voltage: The maximum voltage level at a logic circuit output in the logical 0 state underdefined load conditions.IIH High-Level Input Current: The current that flows into an input when a specified high-level voltage is applied tothat input.IIL Low-Level Input Current: The current that flows into an input when a specified low-level voltage is applied to thatinput.IOH High-Level Output Current: The current that flows from an output in the logical 1 state under specified loadconditions.

IOH IIH

VOH VIH

IOL IIL

VOL VIL

+5V

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August 03, 2010

`~ivjvcbx twc,G,we,G, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

Current Sourcing:

Fig.: Current sourcing action.When the output of gate 1 is in the HIGH state, it supplies a current I IH to the input of gate 2, which acts essentially asa resistance to ground. Thus, the output of gate 1 is acting as a source of current for the gate 2 input. This is referredto as current sourcing action.Current Sinking:

Fig.: Current sinking action.Here the input circuitry of gate 2 is represented as a resistance tied to +V CC. When the gate 1 output goes to its LOWstate, current will flow from the input circuit of gate 2 back through the output resistance of gate 1 to ground. Thus, in

the LOW state the circuit output that drives the input of gate 2 must be able to sink a current IIL coming from thatinput.

TTL NAND Gate:TTL is a logic family implemented with bipolar process technology that combines or integrates NPN transistors, PNjunction diodes and diffused resistors in a single monolithic structure to get the desired logic function. The NAND gateis the basic building block of this logic family.

Fig.: Basic TTL NAND gate and diode equivalent of Q1.

LOW

LOW

+VCC

VOH

IIH

Driving gate

Load gate

1

2

HIGH

HIGH

+VCC

VOL

IIL

Driving gate

Load gate

1

2

+5V

Q2

R14k

D4

D3

D2

A

BQ1

A

BInputs

OutputX

Q1

Vcc=+5V

R31k

Q4

D1

R4

130

R21.6k

R14k

Q3

Q2

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August 03, 2010

`~ivjvcbx twc,G,we,G, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad Lecturer APECE DU (url: sazzadmsi webs com)

The characteristics of TTL inputs come from the multiple-emitter configuration of transistor Q 1. Diodes D2 and D3represent the two E-B junctions of Q1, and D4 is the C-B junction. Forward biasing either or both of these diodejunctions will turn on Q1. Only when all junctions are reverse biased will the transistor be off.On the output side of the circuit, transistors Q3 and Q4 are in a totem-pole arrangement. The job of Q3 is to connectVCC to the output, making a logic HIGH. The job of Q4 is to connect the output to ground, making a logic LOW.

Circuit Operations:

Fig.: The NAND gate in its LOW output state.With inputs A and B both at +5V, diodes D2 and D3 are off and they will conduct almost no current.The +5V supply will push current through R1 and D4 into the base of Q2, which turns on.Current from Q2s emitter will flow into the base of Q4 and turn Q4 on.The flow of Q2 collector current produces a voltage drop across R2 that reduces Q2s collector voltage to a low valuethat is insufficient to turn Q3 on.Q2s emitter is at 0.7V relative to ground due to Q 4s E-B forward voltage and Q2s collector is at 0.1V relative to itsemitter due to VCE(sat). This 0.8V at Q3s base is not enough to forward-bias both Q3s E-B junction and diode D1.With Q3 off, there is no current coming from the +5V terminal through R 4. With Q4 on, Q4s ON-state resistance will below (1 to 25). So the output terminal X will be at a very low voltage.[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

+5V

+5V

D3

D2 D4

+5V

R31k

Q4

D1

R4

130

R2

1.6k

R1

4k

Q3

Q2

OFF

OFFOFF

ON

ON

Y

X

VOL0.4V

ON

A

B

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Class Notes Digital Lec16

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