Class Notes Digital Lec15

8/7/2019 Class Notes Digital Lec15

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August 01, 2010

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Telephone :

PABX : 9661920-73/4980

DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING

UNIVERSITY OF DHAKA

DHAKA-1000, BANGLADESH

FAX: 880-2-8615583

E-MAIL: [email protected]

Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

Programmable Array Logic:PAL architecture has a programmable AND array at the input and a fixed OR array at the output.The number of programmable AND gates is usually smaller than the number required to generate all possibleminterms of the given number of input variables. The OR array is fixed and the AND outputs are equally dividedbetween available OR gates.

Fig.: Internal architecture of a PAL device.Figure shows the internal architecture of a PAL device that has four input lines, an array of eight AND gates at theinput and two OR gates at the output.A programmable AND gate array at the input is fed with various input variables and their complements. It allows anyof the input variables or their complements to appear at the inputs of any of the AND gates in the array. Each of the

AND gates generates a minterm of a user-defined combination of input variables and their complements.Outputs from the programmable AND array feed an array of hard-wired OR gates. Each OR gate is fed from a subsetof AND gates in the array. This implies that the sum-of-product Boolean functions generated by each of the OR gatesat the output will have only a restricted number of minterms depending upon the number of AND gates from which itis being fed.Outputs from the PAL device are available both as OR outputs as well as complemented outputs.

D C B A

Hard-wired OR-array

Y1 Y2

Programmable AND-array

Lec-15, Pg-01


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`~ivjvcbx twc,G,we,G, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.


Example:

A B C D P Q R S

0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 1

1 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 0 x x x x1 0 1 1 x x x x1 1 0 0 x x x x1 1 0 1 x x x x1 1 1 0 x x x x1 1 1 1 x x x x

Table shows the function of a converter. Starting with the Boolean expression for the four outputs (P, Q, R, S),minimize them using Karnaugh maps and then hardware-implement this converter with a suitable PLD with PALarchitecture.Solution:

From the given function table, the Boolean expressions for the four outputs can be written as follows.DCBADCBADCBADCBADCBAP ............... ++++=

DCBADCBAQ ...... +=

DCBADCBADCBADCBADCBADCBAR .................. +++++=

DCBADCBADCBADCBAS ............ +++=

Fig.: Karnaugh maps.Karnaugh maps for the four outputs P, Q, R and S are shown in the figure. The minimized Boolean expressions aregiven by the equations

ACBDBP ++= ..

CBQ .=

CBR +=

DCBDADCBDCBAS ........ +++=

0

1

x

x

1 x 0

x 0

0 0

0 x0

0

x

00

00

01 11 10

01

11

10

AB

CD0

1

x

x

0 x 1

x 1

0 1

1 x0

0

x

00

00

01 11 10

01

11

10

AB

CD0

1

x

x

1 x 0

x 0

1 1

1 x1

0

x

00

00

01 11 10

01

11

10

AB

CD0

0

x

x

0 x 1

x 0

0 1

0 x1

1

x

00

00

01 11 10

01

11

10

ABCD

Lec-15, Pg-02


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August 01, 2010

`~ivjvcbx twc,G,we,G, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.


Fig.: Programmed PAL.For the given function a PAL device is needed that has

(I) four OR gates at the output there are four output functions.(II) 16 AND gates in the programmable AND array each of the OR gates is to be hard wired to only a subset ofprogrammable AND arrays and one of the output functions has four product terms, and

A B C D

Hard-wired OR-array

P Q R S

Programmable AND-array

Lec-15, Pg-03


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August 01, 2010

`~ivjvcbx twc,G,we,G, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad Lecturer APECE DU (url: sazzadmsi webs com)

(III) eight inputs there are four input variables. Each AND gate in the array will have eight inputs to cater forfour variables and their complements.

Figure above shows the architecture of the programmed PAL device where an unprogrammed interconnectionindicated by a cross (x) is a make connection.As the P output has only three product terms, the fourth input to the relevant OR gate need to be applied a logic 0input. This is achieved by feeding the inputs of the corresponding AND gate with all four variables and theircomplements.[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

Lec-15, Pg-04

Class Notes Digital Lec15

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